“VLSI LAB MANUAL”

Prepared By
Dr.Narayana Swamy Ramaiah
Assoc.Prof, Dept of ECE
AMIT,Arba Minch

Reviewed By
Dr.Raja
Assoc.Prof, Dept of ECE
AMIT,Arba Minch

Approved By
Prof.Eyassu Dilla
Head, Dept of ECE
AMIT,Arba Minch

Department of Electrical and Computer Engineering

ARBA MINCH UNIVERISTY,
ARBA MINCH INSTITUTE OF TECHNOLOGY
Jan 2017
Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:
Start →All Programs →Xilinx ISE 10.1→Project Navigator

Note:Your start-up path is set during the installation process and may differ from the one above.

Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.

To create a new project:

1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created
automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the
next section, your new project will be complete.

Creating a VHDL Source

Create a VHDL source file for the project as follows:

1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name .
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source
file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the counter
displays in the Source tab, as shown below:

The next step in creating the new source is to add the behavioral description for the counter.

1. Place the cursor just below the begin statement within the counter architecture.
2. Add the following line below y <= a AND b;
3. Save the file by selecting File → Save.

Check the Syntax of your VHDL source - Synthesize Your Code

When source files are complete, the next step is to check the syntax of the design. Syntax errors and
typos can be found using this step.

1. Select the counter design source in the ISE Sources window to display the related processes in
the Processes for Source window.
2. Click + next to the Synthesize-XST process to expand the hierarchy.
3. Double-click on the Synthesize -XST process.
4. When an ISE process completes, you will see a status indicator next to the process name.
1. If the process completed successfully, a green check mark appears.
2. If there were errors and the process failed, a red X appears.
3. A yellow exclamation point means that the process completed successfully, but some
warnings occurred.
4. An orange question marks means the process is out of date and should be run again.
5. Look in the Console tab of the Transcript window and read the output and status messages
produced by any process you run.
6. You must correct any errors found in your source files. If you continue without valid syntax, you
will not be able to simulate or synthesize your design.
 7. You would like to see "Process 'synthesis' completed successfully". or "Process 'Check Syntax'
completed successfully".

Design Simulation - Simulate the Module Using the ISE Simulator

Create a Test Bench for Simulation

In this section, you will create a test bench waveform containing input stimulus you can use to simulate
the and gate module. This test bench waveform is a graphical view of a test bench. It is used with
simulator to verify that the counter design meets both behavioral and timing design requirements. You
will use the waveform editor to create a test bench waveform (TBW) file.

1. Select the andgt HDL file in the Sources in Project window.

2. Create a new source by slecting project -> New Source.
3. In the New Source window, select Test Bench Waveform as the source type, and
type andtestbench in the File Name field.
4. Make sure the box for Add to Project is checked.
5. Click Next.
6. The source File dialog box shows that you are associating the test bench with the source file:
andgt. Click Next.
7. Click Finish.
You need to set the initial values for test bench waveform in the Initialize Timing dialog box
before the test bench waveform editing window opens.

8. Fill in the fields in the Initialize Timing dialog box using the information below:
o Clock Time High: 20 ns.
o Clock Time Low: 20 ns.
o Input Setup Time: 10 ns.
o Output Valid Delay: 10 ns.
 o Initial Offset: 100 ns.
o Global Signals:GSR (FPGA). Note: The GSR value of 100 is added to the Initial Offset
value automatically.
o initial Length of Test Bench: 1000 ns.
o Leave the remaining fields with their default values.
9. Click Finish to open the waveform editor.

The blue shaded areas are associated with each input signal and corresponding to the Input
Setup Time in the Initialize Timing dialog box. In this design, the input transitions occur at the
edge of the blue cells located under each rising edge of the CLOCK input.

10. Look at the following picture for the setup of the DIRECTION port.

11. Selct File -> Save to save the waveform.

12. Select the Behavioral Simulation in the Source window.
13. On the Sources in Project Window, the TBW file andtestbench.tbw is automatically added to
your project.

Simulating Behavioral Model (ISE Simulator)

To run the integrated simulation process in ISE:

1. Select the andtestbench waveform in the Sources in Project window. You can see Xilinx ISE
Simulator processes in the Processes for Source window.
2. Double-click on the Simulate Behavioral Model process in the Project window. The ISE
Simulator opens and run the simulation to the end of the test bench.

Here is the ISE window showing the simulation results.

Introduction to VHDL

It is a hardware description language that can be used to model a digital system at many levels of
abstraction ranging from the algorithmic level to the gate level. The system may be a single gate
to a complete digital electronic system.

VHDL is a hardware description language used in electronic design automation to describe

digital and mixed-signal system such as field-programmable gate arrays and integrated circuits.
VHDL can also be used as a general purpose parallel programming language.

It can be considered a combination of following languages as:

a) Sequential language
b) Concurrent language
c) Net list language
d) Timing language
e) Waveform Generation language

Need of VHDL

The requirement for it was generated in 1981 under VHSIC program. In this program a number
of US companies were involved in designing VHSIC chips for DoD (defense department).

Most of the companies were using different hardware description to describe and develop their
IC, as a result different vendors could not efficiently exchange designing with one another. Also
they were provided DoD, descriptions of their chips in different hardware description language.
Reuse was also an issue, thus a need for a standard language for design and documentation of the
digital system was generated.

Capabilities of VHDL
1. It is used as an exchange medium between different chip vendors and CAD tool users.
2. It can be used for communication medium between different CAD and CAE tools.
3. Digital system can be modeled a set of interconnected components. Each component in
turn van be modeled a s set of interconnected components further.
4. It supports flexible design methodologies: Top-down Bottom-up mixed
5. It is not technology specific but it is capable of supported technology specific features.
6. It supports both synchronous and asynchronous timing modules.
7. It is an IEEE and ANSI standard.
8. It supports three basic different description styles.
9. It supports a wide range of abstraction levels ranging from abstract behavioral descriptors
to vary precise gate level descriptions.
10. It has element that make large scale design modeling easier such as components,
functions and procedure and package.
11. It is publically available, human readable and above all, it is not proprietary.
Package:

It provides convenient mechanism to store and share declarations that are common across many
design units standard package used-IEEE std_logic_1164. It is decided by IEEE and ANSI.

Hardware abstraction:

VHDL is used to describe a model for digital hardware device. This model specifies the external
view of device and one or more internal views. The internal views of the device specify the
functionality or the structure while the external vies specifies the interface of device through
which it communicate with other modes in environment.Figure 1.1 shows hardware device and
corresponding software of the device.

In VHDL each device model is treated as a distinct representation of unique device, called an
entity.Figure 1.2, shows VHDL view of hardware device that has multiple device models, with
each device model representing an entity. Each entity is described using one model, which
contains one external view and one or more internal view.
VHDL provides 5 different primary constructs called the design units. They are-

1. Entity Declaration
2. Architecture Body
3. Configuration Declaration
4. Package Declaration
5. Package Body

1. Entity Declaration:
It describes the external view of

entity. Ex.-Input-output signal

names

2.Architecture Body:

It contains internal description of entity.

Ex.- A set of inter connected components that represents the structure of entity or set of
concurrent or sequential statements that represent the behavior of entity.

3. Configuration Declaration:

It is used to create an entity; it specifies the binding of one architecture body from many
architecture bodies that may be associated with the entity. It may also specify the binding of
components used in selected architecture body to other entities. An entity may have number
of different configuration.

4. Package Declaration:

A package declaration is used to store a set of common declarations like components, types,
procedures, and functions. These declarations can then be imported into other design units
using a context clause.

5. Package Body:

A package body is primarily used to store the definitions of functions and procedures that
were declared in the corresponding package declaration, and also the complete constant
declarations for any deferred constants that appear in the package declaration. Therefore, a
package body is always associated with a package declaration.

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 10
 Experiment No.-1
Aim: Write VHDL code for basic gates: AND, OR, NOT.

Apparatus: Xilinx ISE 9.2i software

AND Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity andgt is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end andgt;

architecture Behavioral of andgt is

begin

c <= a AND b;

end Behavioral;

Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 11
OR Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity orgt is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end orgt;

architecture Behavioral of orgt is

begin

c <= a OR b;

end Behavioral;

Simulation Output

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 12
NOT Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity notgt is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end notgt;

architecture Behavioral of notgt is

begin

b <= NOT a;

end Behavioral;

Simulation Output

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 13
 Experiment No.-2
Aim: Write VHDL code for universal logic gates: NAND, NOR and XOR, XNOR gates
using basic gates.

Apparatus: Xilinx ISE 9.2i software

NAND Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nandgt is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nandgt;

architecture Behavioral of nandgt is

begin

c <= a NAND b;

end Behavioral;

Simulation Result

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 14
NOR Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity norgt is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end norgt;

architecture Behavioral of norgt is

begin

c <= a NOR b;

end Behavioral;

Simulation Result

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 15
XOR Gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorgt is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xorgt;

architecture Behavioral of xorgt is

begin

c <= a XOR b;

end Behavioral;

Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 16
 Experiment No.-3
Aim: Write VHDL code for 2:1 mux using other basic gates.
A multiplexer is a device that allows multiple input signals and produces a single output signal. the
multiplexer used selects the input line to be sent to the output. The digital code is applied to the
selected inputs to generate respective output.

s c
0 a
1 b

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2t1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
c : out STD_LOGIC);
end mux2t1;

architecture Behavioral of mux2t1 is

begin

process (a,b,s)
begin

if (s='0')
then

c <= a;

else

c <= b;

end if;
end process;
end Behavioral;

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 17
Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 18
 Experiment No.-4
Aim: Write VHDL code for 2:4 decoders.

The decoder is an electronic device that is used to convert digital signal to an analogue
signal. It allows single input line and produces multiple output lines. The decoders are used
in many communication projects that are used to communicate between two devices. A
decoder is a combinational circuit that converts binary information from n inputs line to a
maximum of 2^n unique output lines. For example, if we give 2 inputs that will produce 4
outputs by using 4 by 2 decoder.

E A B D3 D2 D1 D0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder2_4 is
Port ( d_in : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (3 downto 0));
end decoder2_4;

architecture Behavioral of decoder2_4 is

begin

process(en,d_in)
begin
if (en = '0')
then
d_out <= "ZZZZ";
else
case d_in is
when "00" => d_out <= "0001";
when "01" => d_out <= "0010";
when "10" => d_out <= "0100";
when "11" => d_out <= "1000";
when others => null;
end case;
end if;
end process;
end Behavioral;

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 19
 Simulation Results:

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 20
 Experiment No.-5
Aim: Write VHDL code for 4:2 encoder.

An encoder is an electronic device used to convert an analogue signal to a digital signal such as a
BCD code. It has a number of input lines, but only one of the inputs is activated at a given time and
produces an N-bit output code that depends on the activated input. The encoders and decoders
are used in many electronics projects to compress the multiple number of inputs into smaller
number of outputs. The encoder allows 2 power N inputs and generates N-number of outputs. For
example, in 4-2 encoder, if we give 4 inputs it produces only 2 outputs.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder is
port( a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0) );
end encoder;

architecture bhv of encoder is

begin
process(a)
begin
case a is
when "1000" => b <= "00";
when "0100" => b <= "01";
when "0010" => b <= "10";
when "0001" => b <= "11";
when others => b <= "ZZ";
end case;
end process;
end bhv;
Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 21
VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 22
 Experiment No.-6
Aim: Write VHDL code for Half-adder, full-adder.

An adder, also called summer, is a digital circuit that performs addition of numbers. In
many computers and other kinds of processors, adders are used not only in the arithmetic logic
units, but also in other parts of the processor, where they are used to calculate addresses, table
indices, increment and decrement operators, and similar operations.

The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The
carry signal represents an overflow into the next digit of a multi-digit addition.

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full
adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is
a bit carried in from the previous less-significant stage. The full adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. bit binary numbers.

Half adder

------------------------------------------------------------
-- Note : This VHDL program is a structural description of
-- the interactive Half Adder. The program shows every gate in the circuit and the
-- wires linking the gates. It is very important to
-- learn structural design (RTL) strategies because
-- as your assignments become larger and larger,
-- knowledge of register transfer level (RTL) design
-- strategies become indispensable.
------------------------------------------------------------

-- Here we define the AND gate that we need for

-- the Half Adder

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 23
library ieee;
use ieee.std_logic_1164.all;

entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;

architecture func of andGate is

begin
F <= A and B;
end func;
--*=========================================================
--Here we define the XOR gate that we need for
-- the Half Adder

library ieee;
use ieee.std_logic_1164.all;

entity xorGate is
port( A, B : in std_logic;
F : out std_logic);
end xorGate;

architecture func of xorGate is

begin
F <= A xor B;
end func;
--*=========================================================
-- At this point we construct the half adder using
-- the AND and XOR gates
library ieee;
use ieee.std_logic_1164.all;

entity halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end halfAdder;

architecture halfAdder of halfAdder is

component andGate is -- import AND Gate

port( A, B : in std_logic;
F : out std_logic);
end component;

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 24
 component xorGate is -- import XOR Gate
port( A, B : in std_logic;
F : out std_logic);
end component;

begin
G1 : xorGate port map(A, B, sum);
G2 : andGate port map(A, B, Cout);
end halfAdder;

Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 25
 Experiment No.-7
Aim: Write VHDL code for full-adder.

Full Adder – Structural Style

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ha is
Port ( a,b : in std_logic;
s,c : out std_logic);
end ha;

architecture ha_dataflow of ha is

begin

s <= a xor b;
c <= a and b;

end ha_dataflow;

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 26
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fa_str is
Port ( a,b,cin : in std_logic;
s,cout : out std_logic);
end fa_str;

architecture fa_struct of fa_str is

component ha
port (a,b:in std_logic;
s,c: out std_logic);
end component;

signal t1,t2,t3 : std_logic;

begin
h1: ha port map (a,b,t2,t1);
h2: ha port map (t2,cin,s,t3);
cout <= t1 or t3;
end fa_struct;

Full adder- Behavioural Style

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fulladder is
port (abc: in std_logic_vector(2 downto 0);
sum, carry: out std_logic);
end fulladder;

architecture behavioral of fulladder is

begin
process(abc)
begin
case (abc) is
when”000”=>sum<=’0’; carry<=’0’;

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 27
 when”001”=>sum<=’1’; carry<=’0’;
when”010”=>sum<=’1’; carry<=’0’;
when”011”=>sum<=’0’; carry<=’1’;
when”100”=>sum<=’1’; carry<=’0’;
when”101”=>sum<=’0’; carry<=’1’;
when”110”=>sum<=’0’; carry<=’1’;
when”111”=>sum<=’1’; carry<=’1’;
when others=>null;
end case;
end process;
end behavioral;

Simulation Results

Experiment No.-8
VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 28
Aim: Write VHDL code for D Flipflop.

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop. The D flip-
flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge
of the clock). That captured value becomes the Q output. At other times, the output Q does not
change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dflipflop is
Port ( d_in : in STD_LOGIC;
clock : in STD_LOGIC;
d_out : out STD_LOGIC);
end dflipflop;

architecture Behavioral of dflipflop is

begin

process(d_in, clock)

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 29
 begin

-- clock rising edge

if (clock='1' and clock'event) then

d_out <= d_in;
end if;
end process;
end Behavioral;

Simulation Results

VLSI Lab Manual, Dept of ECE, AMIT Dr.Narayana Swamy Ramaiah Page 30