10.

Sequential Circuit Analysis

o Reading Assignment
o Objectives n Sequential Circuit Models: Chapter 8, sections 8.1.1, 8.1.2,
n Thissection introduces synchronous sequential circuits with and 8.11 in Brown & Vranesic.
the following goals: n Mealy and Moore Models: Chapter 8, section8.3
u Give a precise definition of synchronous sequential circuits.
u Introduce several structural and behavioral models for synchronous n Blocking & Non-blocking Assignment statements: Chapter
sequential circuits. 7, section 7.12.3 & 7.12.4 in Brown & Vranesic.
u Demonstrate by example how to analyze synchronous sequential n Verilog representation of sequential circuits: Chapter 8,
circuits by deriving their behavior from a structural description.
sections 8.4.1, 8.4.4, 8.4.7 in Brown & Vranesic.
u Demonstrate how to represent the behavior of a synchronous
sequential circuit with Verilog.

Elec 326 10.1 Sequential Circuit Analysis Elec 326 10.2 Sequential Circuit Analysis

10.1. Synchronous Sequential Circuits o Sequential Circuit Canonical Form

o Definition. A sequential circuit is said to be a Input
•• ••
Output
Signals Combinational Signals
synchronous sequential circuit if it satisfies the •
Logic
•

Network
following conditions: ••
•
••
•

n There is at least one flip-flop in every loop

n All flip-flops have the same type of dynamic clock Current
FF
Next
State • State
n All clock inputs of all the flip-flops are driven by the same Signals
••
Signals
clock signal. FF

CLK

n Any synchronous sequential circuit can be drawn in this

form by pulling the flip-flops to the bottom of the figure
(think of the lines as elastic). Since all loops have a flip-
flop in them, this will leave the remaining circuit without
loops, and hence combinational.

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1
 n There are two versions of this model called the Mealy 10.2. Synchronous Sequential Circuit Models
Model and the Moore model. The only difference is in the
way the output signals are generated. o Structural
u Mealy Model: Outputs depend on current state and inputs n Logic diagram
u Moore Model: Outputs only depend on current state. n Excitation Equations
n Output equations
o Behavioral
n Transition and output equations
n Transition table
n State table
n State diagram (graph)
o SSC Analysis: Derive one of the behavioral models
from an instance of a structural model
o SSC Synthesis: Derive a structural model from one of
the behavioral models
Mealy Model Moore Model

Elec 326 10.5 Sequential Circuit Analysis Elec 326 10.6 Sequential Circuit Analysis

10.3. Analysis Examples n Derive the transition equations from the excitation
equations:
o Example # 1 u Use the characteristic equation for JK flip-flops:

X J Q
Q0 Q* = JQ' + K'Q
u The resulting transition equations are:
1 K Q Y

Q0* = J0•Q0' + K0'•Q0 = (X'+ Q1')•Q0' + 0•Q0

Q Q1
J
= X'•Q0' + Q0'•Q1'
K Q Q1* = J1•Q1' + K1'•Q1 = Q0•Q1' + (X+ Q0)'•Q1
CK
= Q0•Q1' + X'•Q0'•Q1

n Derive the excitation and output equations: n Construct the transition table from the transition equations:
Q1, Q0 X=0 X=1 X=0 X=1
J0 = K0 = 00 01 01 0 0
J1 = K1 = 01 10 10 0 0
10 11 00 0 1
11 00 00 1 0
Y= Q1* Q0* Y

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 n Construct the state table and state diagram from the o Example #2
transition table:
u Assign 0 to 00, 1 to 01, 2 to 10, and 3 to 11 giving the following
state table and diagram

Q1, Q0 X=0 X=1 X=0 X=1 Q X=0 X=1 X=0 X=1

0 0 01 01 0 0 0 1 1 0 0
0 1 10 10 0 0 1 2 2 0 0
1 0 11 00 0 1 n Derive the excitation and output equations:
2 3 0 0 1
1 1 00 00 1 0 3 0 0 1 0
Q1* Q0* Y Q* Y
Transition Table State Table D2 =
D1 =
D0 =
Y =

State Diagram
Elec 326 10.9 Sequential Circuit Analysis Elec 326 10.10 Sequential Circuit Analysis

n Construct the excitation/transition table from the n Construct the state table from the transition table
excitation/transition equations: u Let 000 = A, 001 = B, 010 = C, 011 = D, 100 = E, 101 = F,
110 = G, 111 = H
u Note that since D flip-flops are used, the sets of excitation and Q2 Q1 Q0 X=0 X=1 X=0 X=1
transition equations are the same. Therefore the transition table is 0 0 0 000 100 0 1
obtained by plotting the excitation equations. 0
0
0
1
1
0
100
001
000
101
1
0
0
1
Transition Table: 0 1 1 101 001 1 0
Q2 = Y = X⊕Q2 ⊕Q0; Q1 = Q2; Q0 = Q1; 1 0 0 110 010 1 0
1 0 1 010 110 0 1
1 1 0 111 011 1 0
Q2 Q1 Q0 X=0 X=1 X=0 X=1 1 1 1 011 111
Q2* Q1* Q0*
0
Y
1

0 0 0 000 100 0 1 Q X=0 X=1 X=0 X=1

0 0 1 100 000 1 0 A A E 0 1
0 1 0 001 101 0 1 B E A 1 0
0 1 1 101 001 1 0 C B F 0 1
1 0 0 110 010 1 0 State Table: D F B 1 0
1 0 1 010 110 0 1 E G C 0 1
1 1 0 111 011 1 0 F C G 1 0
1 1 1 011 111 0 1 G H D 1 0
H D H 0 1
Q2* Q1* Q0* Y Q* Y
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 n Construct the state diagram from the state table o Example #3 (Problem 7.18)
Q X=0 X=1 X=0 X=1 EN
J Q J Q MAX
A A E 0 1 Q0 Q1
B E A 1 0 K Q K Q
State Table: C B F 0 1 CLK
D F B 1 0
E G C 0 1
F C G 1 0
n Derive the excitation and output equations:
G H D 1 0
H D H 0 1
J0 = K0 =
Q* Y
J1 = K1 =

MAX =

n Derive the transition equations from the excitation equations:

State Diagram:
Q0* = J0•Q0' + K0'•Q0 =

Q1* = J1•Q1' + K1'•Q1 =

Elec 326 10.13 Sequential Circuit Analysis Elec 326 10.14 Sequential Circuit Analysis

n Construct the transition table from the transition equations: n Construct the state diagram from the state table:
u Transition Equations: Q0* = En•Q0' + EN'•Q0
Q1* = EN•Q0•Q1' + EN'• Q1 +•Q0'•Q1 Q EN=0 EN=1 EN=0 EN=1
0 0 1 0 0
Q1 Q0 EN=0 EN=1 EN=0 EN=1 State Table: 1 1 2 0 0
00 0 0 0 1 0 0 2 2 3 0 0
01 0 1 1 0 0 0 3 3 0 0 1
10 1 0 1 1 0 0 Q* MAX
11 1 1 0 0 0 1
Q1* Q0* MAX
n Construct the state table from the transition table:
State Diagram:

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o Example #4 n Derive the transition equations from the excitation
n Logic Diagram equations:
Q0* = J0•Q0' + K0'•Q0
J Q J Q Z
= (X•Q1'•Q0')•Q0' + (X•Q1)'•Q0
Q0 Q1 = X•Q1'•Q0' + X'•Q0 + Q1'•Q0
K Q K Q

X Q1* = J1•Q1' + K1'•Q1

CLK
= (X•Q0)•Q1' + (X•Q1•Q0')'•Q1
= (X•Q0•Q1' + (X' + Q1' + Q0)•Q1
n Derive the excitation equations = X•Q0•Q1' + X'•Q1 + Q0•Q1
n Derive the transition table from the transition equations:
J0 = Q1 Q0 X=0 X=1
J1 = 00 00 01 0
01 01 1 1 0
K0 =
10 10 00 1
K1 = 11 11 10 1
Q1* Q0* Z

Elec 326 10.17 Sequential Circuit Analysis Elec 326 10.18 Sequential Circuit Analysis

n Derive the state table from the transition table: 10.4. Synchronous Sequential Circuits & Verilog
u Where 00 = A, 01 = B, 10 = C, 11 = D o Blocking vs. non-blocking assignment statements
n Write code for the following circuit (a 2-bit shift register)
Q X=0 X=1 Q1 Q2
D D Q D Q
A A B 0 Q Q

B B D 0 Ck

C C A 1 n First try
D D C 1 module bexample (D, Ck, Q1, Q2);
Q* Z input D, Ck;
output Q1, Q2;
reg Q1, Q2; Q1
D D Q
n Derive the state diagram from the state table: always @(posedge Ck) Ck Q
begin
Q1 = D; Q2
D Q
Q2 = Q1; Q
end
endmodule

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 n The assignment statements in the previous example are n The following module using blocking assignments will
called blocking. They have the following properties: realize the circuit in the previous example:
u The assignment symbol is the equal sign (=). module nbexample (D, Ck, Q1, Q2);
u Multiple assignment statements in the same always block are input D, Ck;
executed in the order written. output Q1, Q2;
reg Q1, Q2;
l In other words a blocking assignment statement will “block” until the Q1 Q2
D D Q D Q
assignment is complete before going to the next statement. always @(posedge Ck) Q Q
l Hence Q1 first gets D and then Q2 gets the new value of Q1 in the previous begin
example. Q1 <= D; Ck
Q2 <= Q1;
n What we need is an assignment that does not change the end
state variables until the inputs of all of them have been
computed. This is called a non-blocking assignment and endmodule
has the following properties: n As a general rule, it is best to use non-blocking
u The assignment symbol is <= assignments for the state variables of a sequential circuit
u All statements are evaluated using the values the variables have and use blocking assignments in combinational logic
when the always block is entered. modules.
u Only when the always block terminates are the variables updated
with their new values.

Elec 326 10.21 Sequential Circuit Analysis Elec 326 10.22 Sequential Circuit Analysis

o Verilog description of example #1 o Alternate description of example 1

module example1a (Ck, X, Q, Y);
input Ck, X;
module example1 (Ck, X, Q, Y); output Y;
input Ck, X;
output Y; output [1:0] Q;
output [1:0] Q; reg [1:0] Q, NXST;
reg [1:0] Q; reg Y;

always @(posedge Ck) always @(posedge Ck)

case (Q) Q <= NXST;
0: Q <= 1;
1: Q <= 2; always @(Q or X)
2: if (X) Q <= 0; case (Q)
else Q <= 3;
3: Q <= 0; 0: begin NXST = 2'b01; Y = 0; end
default: Q <= 2'bxx; 1: begin NXST = 2; Y = 0; end
endcase 2: if (~X) begin NXST = 3; Y = 0; end
else begin NXST = 0; Y = 1; end
assign Y = ((Q == 2) & X) | ((Q == 3) & ~X); 3: begin NXST = 0; if (~X) Y = 1; else Y = 0; end
endcase
endmodule
endmodule

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o Another Example o Alternate description of previous example:
module simple (Clock, Resetn, w, z); module simple (Clock, Resetn, w, z);
input Clock, Resetn, w; input Clock, Resetn, w;
output z; output z;
reg [2:1] y, Y; reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
always @(w or y) // Define the next state combinational logic
case (y) always @(negedge Resetn or posedge Clock) // Define the sequential block
A: if (w) Y = B; if (Resetn == 0) y <= A;
else Y = A; else
B: if (w) Y = C; case (y)
else Y = A; A: if (w) y <= B;
C: if (w) Y = C;
else y <= A;
else Y = A;
default: Y = 2'bxx; B: if (w) y <= C;
endcase else y <= A;
C: if (w) y <= C;
always @(negedge Resetn or posedge Clock) // Define the flip-flops else y <= A;
if (Resetn == 0) y <= A; default: y <= 2'bxx;
else y <= Y; endcase
assign z = (y == C); // Define output logic
assign z = (y == C); // Define output
endmodule
endmodule

Elec 326 10.25 Sequential Circuit Analysis Elec 326 10.26 Sequential Circuit Analysis

10.5. Tips & Tricks 10.7. Review

o Pick useful names for the states in the state table and
digrams o Sequential circuit models:
n Canonical form
u Mealy vs. Moore models
10.6. Pitfalls
n Excitation & output equations
o Treating the clock as an input signal in the behavior n Transition equations & transition table
models
n State table and state diagram
o Misinterpreting the Mealy output signals in state
diagrams o Verilog models
n Blocking vs. non-blocking assignment statements
o The treatment of clocks in all the models.

Elec 326 10.27 Sequential Circuit Analysis Elec 326 10.28 Sequential Circuit Analysis