7. Combinational-Circuit Building Blocks 7.1.

Signal Names
o Objectives o Choose signal names to:
n Indicate an action that is controlled (RESET, LOAD)
This chapter introduces several logical networks that are n A condition that is detected (READY, ERROR)
useful as buliding blocks for larger systems. The objectives of
this section are to: n The type of data carried on a bus (DATA, ADDRESS)
n Discuss naming conventions for digital signals.
o The Active Level for a signal is the level (high or low)
that causes the indicated action to occur. It is the level
n Define and demonstrate the operation of decoders, encoders that causes the signal to be asserted.
and multiplexers, including their use as universal gate
n Active Level notation:
networks.
High Low
n Demonstrate how Verilog can be used to model the RESET+ RESET-
behavior of these networks. RESET RESET*
RESET RESET/
o Reading Assignment RESET /RESET
RESET RESET_L
n Chapter 6 of the text by Brown and Vranesic. The last one is used in the text.

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o Active Levels for Pins

o Signal Names and Equations
n The active level symbols (/, * or -) are just other symbols
in the name, not negation operators.
n Only signal names should appear on the left side of an
equation
o Signal names can be combined with logical operators
to form the right side of an equation.

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 7.2. Decoders o Binary Decoders
o Decoders are used to map code words from one code into code n The most common decoders are binary decoders that
words from another code. translate the binary number code into a one-hot or 1-out-of-
o Decoders usually have enable inputs in addition to the code n code.
word inputs. n If there are n input terminals, then a complete decoder has
n When one or more of the enable inputs are deasserted, the outputs all 2n output terminals.
take on a default value. n There may be less than a complete decoding (e.g., decimal
u The default is usually 0 if the outputs are asserted high and 1 if they are numbers)
asserted low.
n Example: 2-to-4 binary decoder.
u The default could also be the high impedance state for tri-state outputs.
n When the enable inputs are all asserted, decoder translates an input
code into an output code.

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o Examples of decoder chips o Cascading Binary Decoders

o Exercise: How could you use the 74LS139 to

implement a 3-to-8 decoder?

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 7.3. Verilog Descriptions of Decoders o Verilog descriptions of a 2-to-4 decoder constructed from five
copies of the dec2to4 module:
o The Verilog Case Statement
n This statement can be used within always blocks to select
one of serveral alternatives. module dec2to4(W, Y, En);
input [1:0] W;
n General form: Case (expression) input En;
alternative 1: statement; output [0:3] Y;
alternative 2: statement; reg [0:3] Y;
.
. always @(W or En)
. case ({en,W})
alternative 3: statement; 3’b100: Y = 4’b1000;
[default: statement]; 3’b101: Y = 4’b0100;
endcase 3’b110: Y = 4’b0010;
3’b111: Y = 4’b0001;
default: Y = 4’b0000;
u The statement associated with the first alternative to match the
value of the expression is executed. endcase

u If the expression does not match any alternative and there is a endmodule
default statement, it is executed;

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o Alternate description of dec2to4:

o Verilog if-then-else statements: module dec2to4(W, Y, En);
n This is a convention branch statement with the following input [1:0] W;
syntax: input En;
if (conditional_expression) if (conditional_expression) output [0:3] Y;
statement; statement; reg [0:3] Y;
else
statement; always @(W or En)
begin
if (En==0)
n A chain of sequential tests can be constructed as follows: Y = 4’b0000;
else
if (conditional_expression) case (W)
statement; 0: Y = 4’b1000;
else if 1: Y = 4’b0100;
statement; 2: Y = 4’b0010;
else if 3: Y = 4’b0001;
statement endcase
else end
statement;
endmodule

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o Verilog description of a 4-to-16 decoder constructed as a tree o The Verilog “for loop”
of 2-to-4 decoders:
n Syntax:
module dec4to16 (W, Y, En); for (initial_index; terminal_index; increment) statement;
input [3:0] W; n Example: A 2-to-4 binary decoder specified using the for
input En; loop.
output [0:15] Y; module dec2to4 (W, Y, En);
wire [0:3] M; input [1:0] W;
input En;
dec2to4 Dec1 (W[3:2], M[0:3], En); output [0:3] Y;
dec2to4 Dec2 (W[1:0], Y[0:3], M[0]); reg [0:3] Y;
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]); integer k;
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);
dec2to4 Dec5 (W[1:0], Y[12:15], M[3]); always @(W or En)
for (k = 0; k <= 3; k = k+1)
endmodule if ((W==k) && (En==1))
Y[k] = 1;
else
Y[k] = 0;
endmodule

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o Binary Decoders as Minterm Generators 7.4. Multiplexers (MUX)

Realize F = SX,Y,Z(1, 4, 7) with a decoder: o Also called Data Selectors
o Example: 4-to-1 MUX

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o Examples Of Multiplexer Chips o Cascading multiplexers

o Exercise: How could we use the 74LS153 to

implement an 8-to-1 multiplexer?

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7.5. Verilog Descriptions of Multiplexers o Description of a 4-to-1 MUX using conditional

o The Verilog Conditional Operator: operators:
n This is essentially the C conditional operator
module mux4to1 (w0, w1, w2, w3, S, f);
conditional_expression ? true_expression : false_expression input w0, w1, w2, w3;
n Example: input [1:0] S;
output f;
u A = (B<C) ? (D+5) : (D+2);
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
o Description of a 2-to 1 MUX using a conditional operator
endmodule
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;

assign f = s ? w1: w0;

endmodule

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o Description of a 4-to-1 MUX using if-then-else o Description of a 4-to-1 MUX using a case statement:
statements:
module mux4to1 (W, S, f);
module mux4to1 (W, S, f); input [0:3] W;
input [0:3] W; input [1:0] S;
input [1:0] S; output f;
output f; reg f;
reg f;
always @(W or S)
always @(W or S) case (S)
if (S == 0) 0: f = W[0];
f = W[0]; 1: f = W[1];
else if (S == 1) 2: f = W[2];
f = W[1]; 3: f = W[3];
else if (S == 2) endcase
f = W[2];
else if (S == 3) endmodule
f = W[3];

endmodule

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o Verilog description of a 16-to-1 MUX constructed as a tree of o Multiplexers as Function Generators

4-to-1 decoders:
module mux16to1 (W, S, f, M);
input [0:15] W;
input [3:0] S;
output f;
output [3:0] M;
wire [0:3] M;

mux4to1 Mux1 (W[0:3], S[1:0], M[0]);

mux4to1 Mux2 (W[4:7], S[1:0], M[1]);
mux4to1 Mux3 (W[8:11], S[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S[3:2], f);

endmodule

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 o Realizing a 4-variable function with a 3-to-8 Decoder 7.6. Encoders
o Encoders are code translators that perform a
transformation that is the inverse of a decoder
transformation.
o Binary encoders
n Binary decoders translate from the binary code to the one-
hot code.
n Binary encoders translate from the one-hot code to the
binary code.

Binary Binary One-Hot

Code Encoder Code

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n Implementation of a 8-to-3 binary encoder o Priority Encoders

n A priority encoder has n inputs and Èlog2n˘ outputs.
n The output signals are a binary number such that its value
is the highest index value of all the inputs that are 1.
n Example: 4-to-2 priority encoder:

w3 w2 w1 w0 y1 y0 z
0 0 0 0 d d 0 y1 = w3’•w2 + w3
0 0 0 1 0 0 1
0 0 1 x 0 1 1 y2 = w3’•w2’•w1 + w3
Y2 = w7 + w6 + w5 + w4 0 1 x x 1 0 1
z = w0 + w1 + w2 + w3
1 x x x 1 1 1
Y1 = w7 + w6 + w3 + w2
Y0 = w7 + w5 + w3 + w1
n What is the purpose of the signal z?

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 n Verilog description of a priority encoder:
o The Verilog casex and casez statements
module priority (W, Y, z);
n The x and/or z values in the alternatives of a regular case input [3:0] W;
statement must match exactly corresponding x and/or z output [1:0] Y;
signals in the controlling expression of the for loop. output z;
reg [1:0] Y;
n The z value is treated as a don’t care in the alternatives of a reg z;
casez statement.
always @(W)
n Both the x and z values are treated as a don’t cares in the begin
z = 1;
alternatives of a casex statement. casex (W)
n The alternatives do not have to be mutully exclusive in the 4’b1xxx: Y = 3;
4’b01xx: Y = 2;
casex and casez statements. 4’b001x: Y = 1;
u The first matching alternative has priority and is selected. 4’b0001: Y = 0;
default: begin
z=0;
Y = 2’bxx;
end
endcase
end
endmodule
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7.7. Tips & Tricks 7.9. Review

o Use multiplexers and decoders to implement combinational o Active signal levels and signal assertions.
logic functions.
n Enable signals
o Match negative assertion of signals with bubbles
o The relationship between binary decoders and
7.8. Pitfalls minterms.
o The relationship between multiplexers minterms.
o Multiplexer and decoder outputs are usually asserted o Verilog procedural statements and “always” blocks
low.
n if-then-else
o Getting the wrong assignment of variables to the n case, casez and casex
select inputs of a multiplexer or decoder when using
it to realize truth tables. n for loop

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