Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Determination of Various Performance Parameters

using CMOS and CNT via 4T Schmitt Trigger
Yogesh Giri Goswami Nikhil Saxena
PG Scolar Assistant professor
Department of Electronics & Communication Department of Electronics & Communication
Engineering, ITM (GOI) Gwalior Engineering, ITM (GOI) Gwalior
Gwalior, India Gwalior, India

Abstract:- Schmitt trigger is used to augment noise with the inverter, it was determined that the former exhibited
protection of a circuit of broaden delay and power better noise sensitivity than the later. The reason behind it
consumption. The main function of Schmitt trigger is used being that they are exhibited better transition threshold voltage
to decreasing noise issue in the circuit. In this current [6]. Further, the threshold voltage of Schmitt trigger (6T)
paper, the comparison of two techniques, CMOS and CNT circuit is VH during the input signal from VDD to GND and
based transistors of Schmitt trigger in 32nm technology is the same i.e. the conventional Schmitt trigger threshold
compared regarding various performance factors being voltage is found to be VL when the input signal travels down
power consumption, delay, hysteresis loss, leakage current from GND to VDD [7]. The comparison of the same with
etc. In this paper the Schmitt trigger is used in such a comparators is indicated using the DC transfer characteristics.
method that via making an adjustment in the voltage its In the comparators, they are able to exhibit only one switching
premature is enhanced by the output as the time threshold but on the contrary, Schmitt trigger exhibits various
conversion and the consumption of the power is less thus and different switching threshold value for both types of input
decreasing the output delay. The complete circuit signal edges being positive and negative both. This
functioning of Schmitt Trigger is replicated and performed aforementioned property is known as hysteresis. The Schmitt
on the Spice tool for both CMOS and CNT transistors in trigger can be work as a comparator providing positive
32nm technology. The results exhibit that CNT 4T feedback in the circuit [9]. Therefore, to acquire these
Schmitt Trigger reduces the consumption of power, approaches, Schmitt trigger modifications in the structure are
leakage as well as output delay thereby obtaining better to be made and then this technology can be completely
efficiency and results over CMOS based circuit. implemented at the level of circuit. The parameters of Schmitt
trigger have been examined through spice tools in the circuit.
Keywords:- 4T Schmitt Trigger, CMOS, CNT, Power Further, the feature of hysteresis, in Schmitt trigger, masks
Consumption, Leakage, Delay, Hysteresis loss, SPICE Tool. some of the unwanted transient pulses over the input. On
based over the above, there was a requirement of the effective
I. INTRODUCTION and efficient designing of the hardened memory elements
which were based on Schmitt trigger. In this circuit when we
The digital signal cannot be defined directly by the increased the input capacity of the critical nodes, then the
digital circuit; there are several reasons behind it being the power consumption was also increased [11][12].
time of rise and fall, they also exhibit a little bit of noise sense
because of the proceeding circuitry, so for maintaining all the According to the property of hysteresis, Schmitt trigger
critical conditions and signal, there is a need of a specified is to remove noisy signal and gives reliable signals in the
clean up device which is known as Schmitt trigger [3]. When circuit. The aforementioned can be well-defined for those
level of input crosses the predetermined threshold level, then systems exhibiting high performance and low power. The
the output level is changed. This directly indicates that the former is the one in which when the input is rising and finally
output level is dependent over the input level. For solving reaches the UTP voltage and the latter is the point at which the
mainly the problem of noise, the device named as Schmitt input which is falling finally reaches LTP voltage. And when
trigger is used in the circuit of analog and digital in the form the input lies amongst these two pints then its value is retained
of wave shaping device [4]. The main function of this drive is by output. The hysteresis thickness is too determined between
driving or converting load with fast switching the low loss and gap of UTP and LTP voltage. If, the CMOS technology
supply of power. This Schmitt trigger is basically used to feature size is scaled down in nanometer scales, then the
decrease the noise sensitivity and enhance the control state i.e. channel effects which are short will become more critical as
on/off state [5]. Conversion of a slow differentiating analog the dimensions of the device and the supply voltage cannot be
signal voltage into the maximum possible binary states is the similarly scaled. There are several limitations also which
main working of Schmitt trigger. But, this conversion is further creates foundations regarding the scaling of the CMOS
dependent over the voltage; earn that whether this type of technology as demanding high intensity and the applications
voltage is above or below the recommend threshold voltage. which are energy efficient. The limitations for the
On comparing the conventional Schmitt trigger circuit (6T) aforementioned are being power density and the current

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Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
leakages which are high and the issues which are related to regarding the performances at low consumption and reducing
reliability. To overcome these limitations, some of the the leakage issues also within this 32nm ranges [17].
successful innovations being MOS/SOI structures have
already been suggested and implemented. But at the nanolevel II. LITERATURE REVIEW
or the nanoscale, for overcoming these serious issues, there is
a requirement of alternative materials and nano devices. There Mogaddham et.al stated in 2017 that the buffer of
are several emerging nano devices which are and can be used Schmitt trigger via carbon nanotube FET for the applications
for resolving these serious issues being CNTFET, which is of low power consumption. According to them, the
exactly similar to MOSFET; they both share similar structures susceptibility of the transient faults or the soft errors was more
and electrical features of the devices. In this new era of possible in the nanoscale circuits as they had the charge
CNTFET, the existence of CMOS is still prevailing in the already stored in their nodes which were sensitive. Therefore,
current technology. There are several designs which are being they stated that it is really challenging to design low-cost
used amongst them is robust circuit design which is becoming designs of the circuits when it is concerned with nanoscale
popular and crucial in this nano-scale technology era, and is storage cells. It can be further described low power hardened
further counted as one amongst the most promising alternative latch design circuit using Schmitt trigger. They did not
technology being CNTFET [14][15][16]. enhanced up sizing or enhancing the input capacitance instead
they determined the hysteresis mechanism of proposed
There is a lot of ongoing research worldwide to Schmitt trigger buffer. The simulations results can be
accomplish the novel design of Schmitt triggers with determine Stanford CNTFET model in 16 nm technology.
improvised performances within the limited sizes. The main Their results dictated that their proposed technology lowered
suffering with the conventional Schmitt triggers is the design the power delay product by 90% and enhanced the robustness
challenges regarding the op- amp and the consumption of compared to the PVT variations with most effective and
power is high. So, for reducing these two issues the Schmitt efficient CNTFET based counterparts. There proposed
triggers were synthesized using the CMOS technology. The hardened latch tolerance was also considerable for multiple
mostly used Schmitt trigger was constructed by Dokic in node upset, the results were confirmed by the simulations.
1984. He designed the four transistors amongst or in between There was 68% higher critical charge found for the proposed
the grounds and the power rails. But, these designs failed their hardened latch, therefore enhancing the reliability and further
working for the low voltage applications. So, in 2001 change decreasing the 16 of the smaller areas when compared to all its
et.al constructed multilayer Schmitt trigger, involving large counterparts [1].
and huge variations of voltage amongst the two threshold
voltages. Instead the main requirement of the structure was as Saxena et.al in 2016 stated the designs of Schmitt trigger
before, the 4T between the power rails and the ground. Thus, which was based over the sink logic. The authors presented
if failed again working for low voltages applications. In 2005 the paper using 3 COMS and CNT transistors in 32nm
Chen and Ming constructed a Schmitt trigger which was technology. The comparative analyses were investigated. The
basically based on the design of Dokic working below 3.3V in circuit used by them was 6T. The tool used by them was H
enmity of high voltage gates bearing more stress. Further, now Spice and the technology used was 32 nm nodes. They
the research work started for the reduction of weights and size investigated some common parameters for evaluation. They
of transistor technology with efficient analog processing of the analyzed the circuits for various separate inputs being pulse,
signal. These circuits were of the digital and the analog types. waveform, damped, inputs which were triangular and
Digitally, the implementation and the designing of the circuits exponential. They calculated and investigated about the
is easy as compared to the same in the analog domain, it is average power, propagation delay and the consumption of the
quite risky and challenging too. So, for the further formulation power. They also analyzed the sensitivity of the temperature.
of the structures and task several technologies have been Finally they evaluated the hysteresis curves of Schmitt trigger
utilized being TTL, CMOS, Bi-CMOS etc. being one of the based over the sing logic with all inputs. The results displayed
efficient technologies also, they exhibit some limitations and higher gains when compared to the inverters which were
drawbacks regarding the ranges of the frequency, signal actively loaded [18].
disturbances due to minor current, the tunneling effect, as the
existing CMOS technology could not attain the satisfying Saxena et.al in 2015 stated that for acquiring the better
results when specifically behavior was concerned. Therefore, consumption of power, magnitude, speed, reliability and
these types of limitations and drawbacks were improved in hysteresis was attained by CMOS device. The main aim of the
CNTFET that can be accepted worldwide as an analog and Schmitt trigger according to the authors was lowering the
digital signal circuit. This technology named as CNTFET power dissipation and enhancing the compatibility with the
exhibits the ideal and efficient response of circuits within a supply of power accommodating with the low voltage, and the
transistor with 32nm range. The better results can also be capable result was to decrease the power dissipation which
obtained via this technology keeping the ranger low than 32 was counted to the device. The authors have compared the
nm also. This technology has illustrated excellent and efficient presentation of 6T and 4T Schmitt trigger. The 6T is the
results and is functioning as a boon for the electronic industry conventional six transistors and the 4T is the four transistors.
This is further performed in such a way that as its voltage is

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Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
adjusted, the premature is increased and the output is ended. in this paper. This type of transistor is cylindrical form whose
Thus the delay of the output is reduced because of the less length (L) and width (W) dimension is 32nm. Working
consumption of power and conversion of time. It can principal of both MOSFET and CNTFET technology can
performed and reproduced the circuit using MATLAB tool in work in 32 nm The Schematic design of CNT based 4T
180 nm and 90 nm technology exhibiting the results of delay Schmitt trigger as shown in figure 3.
reduction by 12.3% and power to reduce by 24% in 6T
Schmitt trigger [8].

III. CMOS SCHMITT TRIGGER

Fig 3:- CNT 4T Schmitt trigger circuit

Power supply voltage and threshold voltages both are

condensed to the mount of CMOS technologies. When
trimming in threshold voltage results in a mount of sub
Fig 1:- CMOS 4T Schmitt trigger circuit threshold to run current in the circuit. In fashionable physical
science style, high performance integrated circuits (ICs), quite
CMOS based Schmitt trigger as seen in figure 1. In this five hundredth of the whole on mode energy is dissipated
kind of Schmitt trigger contains of four CMOS based because of the run power, with additional transistors integrated
transistor to be used then it is called 4T Schmitt trigger. on-chip, run currents will speedily govern the whole power
CMOS based Schmitt trigger contain of two part first one is consumption of high performance ICs. Relation between
PMOS and second one is NMOS. In this circuit PMOS device leakage current and power is given by
is connected to voltage (Vdd) and NMOS device to the ground
(Gnd). Schmitt trigger can work as inverting comparator when Pleak  Ileak .Vdd (1)
we applied low input signal to get high output and vice-versa
throughout the circuit. The schematic representation of 4T
Schmitt trigger in figure 2. In this relation we have to determine leakage power as
well as leakage current. When supply voltage is 1V then
leakage power and leakage current are same but in opposite
direction. Hysteresis is the characteristics of the Schmitt
trigger to improve quality of given circuit, in which threshold
voltage changed when the input is going to rise or fall of
circuit [2]. Physical phenomenon breadth is given by ∆H; on
the other way physical phenomenon is that the differentiate
between the sign level at that a Schmitt trigger is standby
mode and active mode (OFF and ON) state

H  VH  VL (2)

Fig 2:- Schematic design of 4T Schmitt trigger with net listing Table 1 represents Comparative performance parameters of
Schmitt Trigger with CMOS and CNT transistor in 32 nm.
IV. PROPOSED DESIGN

As given in figure 2 represent schematic design of 4T

Schmitt trigger in CMOS, transistor P is connected between
point (1) and point (2). Point 1 is supply voltage (Vdd) and
Point 2 represents output of the circuit, transistor N1 is B/w
point 2 and 3, N2 and N3 is between point 3 and ground (Gnd)
of circuit. CNT based transistors technology to replace
MOSFET into CNTFET. There is lot of drawbacks in CMOS
based transistor to overcome this limitation through CNTFET

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ISSN No:-2456-2165
Schmitt
trigger
Performance Schmitt Trigger CNT
parameters CMOS based based

Technology 32 nm 32 nm
Supply
voltage 1V 1V
Leakage
power 149.82pW 107pW
Leakage
current 149.82pA 107pA
Average
power 49.07nW 32.67nW

Hysteresis loss 360mV 130mV

Fig 5:- 4T Schmitt trigger waveform in CNTFET technology
Propagation
Delay 65.93ns 62.31ns Efficiency is the fraction of output value to the input
value of any circuit. High efficiency means that fewer power
Table 1.
drains and also the input provide and fewer temperature
buildups, granting little lighter power provides and structure
V. SIMULATION RESULTS AND DISCUSSIONS
enclosures. Potency is meanly measured as
The simulation waveform result of 4T Schmitt trigger
using CMOS and CNTFET at 32nm technology with the help Efficiency  Output
Input *100
of spice tools as seen in figure 4 and figure 5. (3)

Efficiency of 4T trigger Schmitt to be better in CNTFET

in comparison of CMOS based technology because decrease
in power consumption and hysteresis loss. The simulation
result to be determined with the help SPICE device.

VI. CONCLUSION

In this paper to compare both CMOS and CNT

transistors at 32nm technology in 4T Schmitt trigger design
for performance parameters like the power consumption,
delay, hysteresis, leakage current etc. The complete circuit
work of 4T Schmitt trigger is performed on the SPICE Tool
for both CMOS and CNT transistors. The results of CNT 4T
Schmitt trigger reduces the power consumption is 28.51% and
hysteresis loss is reduce to 63.88% over CMOS based
technology. From the inferences made the idea of the research
have been integrated through the CNT based transistors
concept gives more efficiency than the CMOS based
transistors technology because the planned Latch are designed
Fig 4:- 4T Schmitt trigger waveform in CMOS technology victimization Schmitt trigger arrangement such the physical
phenomenon property is used to induce higher performance
Simulation waveform result of 4T Schmitt trigger using against clanging input signals. Additionally the look is
CNTFET technology noise immunity of signal and hysteresis benefited with the distinctive properties of CNTFETs at an
loss to be reduced in comparison of CMOS technology as optimized nanometric vary of sixteen nm. Proposed circuits
clearly seen in the waveform of CNTFET technologies in have easy structure with solely half-dozen transistors which
figure 5. ends up into less delay and less power consumption
throughout the operation.

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ISSN No:-2456-2165
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