UNIT I BIASING OF DISCRETE BJT AND MOSFET

1.1 Introduction

BJT consists of 2 PN junctions. It has three terminals: emitter, base and

collector. Transistorcan be operated in three regions, namely cut-off, active and
saturation by applying proper biasing conditions.

Region of Emitter Base Collector Base

Operation Junction Junction
Cut-off Reverse biased Reverse biased
Active Forward biased Reverse biased
Saturation Forward biased Forward biased
• Active:
– Most important mode, e.g. for amplifier operation and switching
application
– The region where current curves are practically flat.
• Saturation:
– Barrier potential of the junctions cancels each other out causing a
virtual short.
– Ideal transistor behaves like a closed switch.
• Cutoff:
– Current reduced to zero
– Ideal transistor behaves like an open switch.
In order to operate transistor in the desired region we have to apply
external d.c. voltages of correct polarity and magnitude to the two junctions of
the transistor. This is nothing but the biasing of the transistor.
When we bias a transistor we establish a certain current and voltage
conditions for the transistor. These conditions are known as operating conditions
or d.c. operating point or quiescent point. The operating point must be stable for
proper operation of the transistor. However, the operating point shifts with
changes in transistor parameters such as β, Ico and VBE. As transistor parameters
are temperature dependent, the operating point also varies with changes in
temperature.

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1.2 Need for biasing

Fig.1.1 (a)
Bias establishes the DC operating point for proper linear operation of an
amplifier. If an amplifier is not biased with correct DC voltages on the input and
output, it can go into saturation or cutoff when an input signal is applied. Figure
1.1 shows the effects of proper and improper DC biasing of an inverting
amplifier. In part (a), the output signal is an amplified replica of the input signal
except that it is inverted, which means that it is 1800 out of phase with the input.
The output signal swings equally above and below the dc bias level of the output,
VDC(out).

Fig.1.1 (b), (c)

Improper biasing can cause distortion in the output signal, as illustrated in
parts (b) and (c). Part (b) illustrates limiting of the positive portion of the output
voltage as a result of a Q-point (dc operating point) being too close to cutoff.
Part (c) shows limiting of the negative portion of the output voltage as a
result of a de operating point being too close to saturation.

1.3 Load line and Variation of quiescent point

Biasing is the application of dc voltages to establish a fixed level of current

and voltage. For transistor amplifiers the resulting dc current and voltage establish
an operating point on the characteristics that define the region that will be
employed for amplification of the applied signal. Since the operating point is a
fixed point on the characteristics, it is also called the quiescent point (abbreviated
Q-point). The operating point of a device, also known as bias
2
 point, quiescent point, or Q-point, is the point on the output characteristics that
shows the DC collector–emitter voltage (Vce) and the collector current (Ic) with
no input signal applied.
Consider the fixed bias circuit,

Fig 1.2
We have

We can draw a straight line on the graph of IC versus VCE which is having slope -
1/Rc.To determine the two points on the line we assume VCE = VCC and VCE =0
a) When VCE =VCC ; IC =0 and we get a point A
b) When VCE=0 ; IC=VCC/RC and we get a point B

The figure below shows the output characteristic curves for the transistor in CE
mode. The DC load line is drawn on the output characteristic curves. Load line -
To draw load line, we have to find saturation current and the cutoff voltage.
Saturation point - The point at which the load line intersects the characteristic
curve near thecollector current axis is referred to as the saturation point . At this
point of time, the current through the transistor is maximum and the voltage
across collector is minimum for a given value of load. So, saturation current for
the fixed bias circuit, Ic (sat) =Vcc/Rc .
Cutoff point -The point where the load line intersects the cutoff region of the
collector curvesis referred as the cutoff point (i.e. end of load line). At this point,
collector current is approximately zero and emitter is grounded for fixed bias
circuit. so, Vce (cut) = Vc = VccOperating point - The "Q point" for a
transistor amplifier circuit is the point along itsoperating region in a "quiescent ",
where no input signal gets amplified.

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 The figure below shows the output characteristic curves for the transistor in CE
mode with points A and B, and line drawn between them. The line drawn
between points A and B is called d.c load line. The d.c word indicates that only
d.c conditions are considered, i.e input signal is assumed to be zero.

Fig 1.3
The d.c load line is a plot of IC versus VCE. For a given value of Rc and a given value
of Vcc. So, it represents all collector current levels and corresponding collector
emitter voltagesthat can exist in the circuit. Knowing any one of Ic, I B, or VCE , it is
easy to determine the other two from the load line. The slope of the d.c load line
depends on the value of RC.
It is the negative and equal to reciprocal of the RC.
Applying KVL to the base circuit, we get

The intersection of curves of different values IB of with d.c load line gives
different operating points. For different values of IB, we have different
intersection points such as P, Q and R.
Selection of operating point

The operating point can be selected at different positions on the d.c load
line, near saturation region, near cut-off region or at the centre, i.e in the active
region. The selection of operating point will depend on its application. When
transistor is used as an amplifier, the Q point should be selected at the center of
the d.c. load line to prevent any possible distortion in the amplified output signal.

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 Case 1
Biasing circuit is designed to fix a Q point at point P which is very near to
the saturation region as shown in figure below 1.14. It results collector current is
clipped at the positive half cycle. i.e. distortion is present at the output. Therefore,
point P is not a suitable operating point.

Case 2
Biasing circuit is designed to fix a Q point at point R as shown in Fig.
Point R is very near to the cut-off region. Here, the collector current is clipped
at the negative half cycle. So, point R is also not a suitable operating point.

Case 3
Biasing circuit is designed to fix a Q point at point Q as shown in Fig.. The
output signal is sinusoidal waveform without any distortion. Thus point Q is the
best operating point.

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DC Load Line (Example)

Fig 1.7

The figure 1.7 shows the biasing of transistor in common emitter configuration.

In Figure 1.8, we assign three values to IB and observe what happens to IC

and VCE. First, VBB is adjusted to produce an IB of 200 A, as shown in Figure
1.8(a), Since IC = βDC IB, the collector current is 20 mA, as indicated, and

VCE = VCC - IcRc = 10 V - (20 mA) (220 Ω) = 10 V - 4.4 V =

5.6V .
This Q-point is shown on the graph of Figure 1.3(b) as Q1.

Next, as shown in Figure 1.8(b), VBB is increased to produce an IB of 300 µA and

an Ic of 30mA.
VCE = 10 V - (30 mA) (220 Ω) = 10V – 6.6 V = 3.4 V

The Q-point for this condition is indicated by Q2 on the graph.

Finally.as in Figure 1.8 (c), VBB is increased to give an IB of 400 µA and an Ic of
40 mA.

VCE = 10 V - (40 mA) (220 Ω) = 10 V - 8.8 V

= 1.2 V Q3 is the corresponding Q-point on
the graph.
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 Figure 1.8
Notice that when IB increases, Ic increases and VCE decreases. When IB
decreases, Ic decreases and VCE increases. As VBB is adjusted up or down, the
dc operating point of the transistor moves along a sloping straight line, called
the DC load line, connecting each separate Q-point.

Figure 1.9

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At any point along the line, values of IB, Ic, and VCE can be picked off the graph,
as shown in Figure1.9.
The dc load line intersects the VCE axis at 10 V. The point where VCE = VCC. This
is the transistor cutoff point because IB and IC are zero (ideally). Actually, there is
a small leakage current, ICBO , at cutoff as indicated, and therefore VCE is slightly
less than 10 V but normally this can be neglected.
The dc load line intersects the IC axis at 45.5 mA ideally. This is the transistor
saturation point because IC is maximum at the point where VCE = 0 V and IC =
VCC / RC.
Actually, there is a small voltage (VCE (sat)) across the transistor, and I C(sat)
is slightly less than 45.5 mA, as indicated in Figure 1.4. Note that Kirchhoff's
voltage law applied around
the collector loop gives,
VCC - ICRC - VCE = 0.
These results in a straight line equation for the load line of the form y = mx + b as
follow:
IC = - (1/RC) VCE +VCC / RC
Where, - (1/RC) is the slope and VCC/ RC is the y-axis intercept point.

Variation of quiescent point due to hFE variation within manufacturers

tolerance

It is clear that the biasing circuit should be designed to fix the operating
point or Q point at the center of the active region. But only fixing of the operating
point is not sufficient. While designing the biasing circuit, care should be taken
so that the operating point will not shift into an undesirable region (i.e. into cut-
off or saturation region). Designing the biasing circuit to stabilize the Q point is
known as bias stability.
Two important factors are to be considered while designing the biasing
circuits which are responsible for, shifting the operating point.

I. Temperature
1) Ico: The flow of current in the circuit produces heat at the junctions.
This heatincreases the temperature at the junctions". We know that the minority
carriers are temperature dependent. They increase with the temperature. The
increase in the minority carriers increases the leakage current ICE0,

Specifically, ICB0 doubles for every 10°C rise in temperature. Increase in I CE0 in
turn increases the collector current

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The increase in IC further raises the temperature at the collector junction and the
same cycle repeats. This excessive increase in IC shifts the operating point into
the saturation region, changing the operating condition set by biasing circuit.
As the power dissipated within a transistor is predominantly the Power
dissipated at its collector base junction, the power dissipation is given as

The increase in the collector current increases the power dissipated at the
collector junction. This, in turn further increases the temperature of the junction
and hence increasesthe collector current. The process is cumulative. The excess
heat produced at the collector base junction may even burn and destroy the
transistor. This situation is called 'Thermal runaway’ of the transistor. For any
transistor, maximum Power dissipation is always a fixed value. That is known as
maximum power dissipation rating of a transistor. This value is specified by the
manufacturer in data sheet. If this limit is crossed, the device will fail.
2) VBE: Base to emitter voltage VBEchanges with temperature at the rate of
2.5mV/°CBase current, IB depends upon VBE .As base current IB depends on VBE,
and Ic depends on IB, Ic depends on VBE. Therefore collector current Ic. Change
with temperature due to change in VBE. The change in collector current change
the operating point.
3)βdc:βdc of the transistor is also temperature dependent. Asβdc varies, Ic
alsovaries, since Ic = βIB. The change in collector current change the operating
point.
Therefore, to avoid thermal instability, the biasing circuit should be designed to
provide a degree of temperature stability i.e. even though there are temperature
changes, the changes in the transistor parameters (VCE , I CQ , PDmax )should be
very less so that the operating point shifting is minimum in the middle of the
active region.
II) Transistor current gain hFE/β
Eventhough there is tremendous advancement in semiconductor
technology, there are changes in the transistor parameters among different units
of the same type, same number. This means if we take two transistor units of
same fire (i.e. same number, construction, parameter specified etc.) and use them
in the circuit, there is change in the β value in actual practice. The biasing circuit
is designed according to the required β value. But due to change in β from unit to
unit, the operating point may shift.
Figure shows the common emitter output characteristics for two transistors of the
same type. The dashed characteristics are for a transistor whose p is much larger
than that of the transistor represented by the solid curves.
So for stabilizing the operating point the factors discussed so far should be
considered while designing the biasing circuit.

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 Figure: Common emitter output characteristics

1.4 BIASING METHODS

The common biasing circuits used in the bipolar transistor amplifiers are
1. Fixed bias
2. Collector-to-base bias
3. Fixed bias with emitter resistor
4. Voltage divider bias
5. Emitter bias

1.5 Fixed Bias (Base Resistor Bias)

The Figure shows the fixed bias circuit. It is the simplest d.c. bias configuration.
For the d.c. analysis we can replace capacitor with an open circuit because the
reactance of a capacitor for d.c. is
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 In the base circuit,
Apply KVL, we get
VCC = IBRB + VBE
Therefore,
IB = (VCC - VBE)/RB
For a given transistor, VBE does not vary significantly during use. As VCC is of
fixed value, on selection of RB, the base current IB is fixed. Therefore this type is
called fixed bias type of circuit.
In the Collector circuit
Apply KVL, we get
VCC = ICRC + VCE
Therefore,
VCE = VCC - ICRC
The common-emitter current gain of a transistor is an important parameter in
circuit design, and is specified on the data sheet for a particular transistor. It is
denoted as β.
IC = βIB

In this circuit VE =0

Stability factor S for Fixed bias circuit

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Merits:
• It is simple to shift the operating point anywhere in the active region by
merely changing the base resistor (RB).
• A very small number of components are required.

Demerits:
• The collector current does not remain constant with variation in
temperature or power supply voltage. Therefore the operating point is
unstable.
• Changes in Vbe will change IB and thus cause RE to change. This in turn
will alter the gain of the stage.
• When the transistor is replaced with another one, considerable change in
the value of β can be expected. Due to this change the operating point will
shift.
• For small-signal transistors (e.g., not power transistors) with relatively
high values of β (i.e., between 100 and 200), this configuration will be
prone to thermal runaway. In particular, the stability factor, which is a
measure of the change in collector current with changes in reverse
saturation current, is approximately β+1. To ensure absolute stability of the
amplifier, a stability factor of less than 25 is preferred, and so small-signal
transistors have large stability factors.

Usage:
Due to the above inherent drawbacks, fixed bias is rarely used in linear circuits
(i.e., those circuits which use the transistor as a current source). Instead, it is
often used in circuits where transistor is used as a switch. However, one
application of fixed bias is to achieve crude automatic gain control in the
transistor by feeding the base resistor from a DC signal derived from the AC
output of a later stage.

Problems

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1. Design the fixed bias circuit from the load line given in the figure.

2. For the circuit shown in figure. Calculate IB,IC,VCE,VB,VC and VBC.

Assume VBE= 0.7V and β=50.

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3. Design a fixed biased circuit using a silicon transistor having β value of 100. Vcc is
10 Vand dc bias conditions are to be VCE = 5 V and IC = 5 mA,

Solution
Applying KVL to collector circuit,

Applying KVL to base circuit,

4. Calculate the operating point (Q-point)

Base biased CE connection

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 IC = βdc * IB = 100 * 29µA = 2.9 mA

VCE = VCC - (IC * RC) = 15V - (2.9 mA * 3KΩ) = 6.3V

By plotting IC (2.9 mA) and VCE (6.3V), we get the operation point ----> Q-point
(quiescent point) Collector curve with load line and Q – point

5. Draw the load line and Q-point.

base biased CE connection, β=50

Solution:

IC = IB * β = 2.15 mA
VCE = VCC - (RC * IC)= 5.7V

VCE (cut) = VCC = 3.0V

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1.6 Requirements of a biasing circuit
1. Emitter base junction must be forward biased and collector
base junction must be reverse biased. That means the transistor
should be operated in the middle of the active region or Q point
should be fixed at the centre of the active region.
2. Circuit design should provide a degree of temperature stability.
3. Q point should be made independent of the transistor parameters such
as β.

To maintain the Q point stable by keeping IC and VCE constant so that the
transistor will always work in active region, the following techniques are
normally used,
1. Stabilization technique
2. Compensation technique

1.7 Method of stabilizing the Q point

Stabilization technique:
It refers to the use of resistive biasing circuits which allow I B to vary so
as to keep IC relatively constant with variations in ICO, β and VBE.
Compensation technique:
It refers to the use of temperature sensitive devices such as diodes,
transistors, thermistors which provide compensating voltage and current to
maintain Q point stable.

1.8 Stability Factors

It is defined as the degree of change in operating point due to variation in
temperature. There are three variables which are temperature dependent. Three
stability factors are defined asfollows,

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Stability factor S:

17
Stability Factor for Fixed bias circuits:
Stability factor S:

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Stability factor S’:

Relation between S and S’:

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Stability factor S”:

Relation between S and S”:

We know that S = 1+β and S” = IC/β
Multiplying numerator and denominator by (1+β),

S” = IC(1+β)
_____
β(1+β)

S” = IC S
______
β(1+β)

1.9 Collector to Base Bias

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 Figure shows the dc bias with voltage
feedback. It is also called as collector to base bias circuit. It is an improvement
over fixed bias method. In this, biasing resistor is connected between collector and
base of the transistor to provide feedback path.

Circuit analysis:
Base circuit:
Consider the base circuit and applying voltage law then we get,

Only the difference between the equation for IB and that obtained for fixed
bias configuration is βRC, so the feedback path results in a reflection of the
resistance RC to the input circuit.

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 Collector circuit:
Applying KVL to the collector circuit,

VCC – (IC + IB) RC – VCE = 0

VCE = VCC – (IC + IB) RC
If there is a change in β due to piece to piece variation between transistors
or if there is a change in β and I CO due to the change in temperature. So collector
current tends to increase. As a result, voltage drop across RC increases. Due to
reduction in VCE, IB reduces. The result is that the circuit tends to maintain a
stable value of collector current, keeping the Q point fixed.
In this circuit, RB appears directly across input and output. A part of output
is feedback to the input. And increase in collector current decreases the base
current. So negative feedback exists in the circuit. It is also called as voltage
feedback bias circuit

1.10 Modified collector to base bias circuit:

To improve the level of stability, emitter resistance is connected in this

circuit.

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 Base circuit:

Only difference between the equation for IB and that obtained for the fixed bias
configuration is the term β (RC + RE).So feedback path results in a reflection of the
resistanceRC back to the input circuit.
In general,

Where V’ = VCC - VBE

R’ = 0 for fixed bias
R’ = RE for emitter bias
R’ = RC for collector to base bias
R’ = RC + RE for collector to base bias with RE
Collector circuit:
Applying KVL to collector circuit,
VCC – (IC+IB) RC – VCE – IERE = 0
VCE = VCC – IE (RC+RE)
Stability factor S for collector to base bias circuit:
VCC = IC RC – IB(RB+RC) + VBE

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When ICBO, IB and IC changes with no effect on VCC and VBE, the equation
becomes,

S= 1+β
______________
1+β (RC/ (RC+RB))
Collector to base bias circuit is having lesser stability factor than for fixed
bias circuit.
So this circuit provides better stability than fixed bias circuit.

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25
26
27
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 Problem 1:
Locate the operating point of the given circuit with VCC = 15V, hfe = 200.

Solution:
IBQ = VCC - VBE
___________
RB+ (1+β) (RC+RE)
= 15-0.7
________________________
630*103 + (1+200) (4.7*103+680)
ICQ = β IBQ = 200*8.356*10-6
= 1.6712mA
IEQ = ICQ + IBQ = 1.6712*10-3 + 8.356*10-6
= 1.68mA
VCEQ = VCC – IE (RC+RE)
= 15-1.68*10-3 (4.7*103 + 680)
= 5.96V

1.11 Voltage divider bias circuit or self bias circuit:

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 Figure above shows the voltage divider bias circuit. In this, biasing is
provided by three resistors R1, R2 and RE. The resistors R1& R2 act as a potential
divider giving a fixed voltage to base. If collector current increases due to change
in temperature or change in β, emitter current IE also increases and voltage drop
across RE increases thus reducing the voltage difference between base and
emitter. Due to reduction in base emitter voltage, base current and collector
current reduces. So we can say that negative feedback exists in emitter bias
circuit. This reduction in collector current compensates for the original change in
IC.
Circuit analysis:
Basecircuit:

30
Collector circuit:

Simplified circuit of voltage divider bias:

31
 Fig.1.32 Thevenin’s equivalent circuit for voltage divider bias
From above figure, R1 and R2 are replaced by RB and VT.
Where RB is the parallel combination of R=1 and R2

VT is the thevenin’s voltage

Apply KVL,

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Problem 1:
For the given circuit β=100 for silicon transistor. Calculate VCE and IC.

Solution:

Problem 2:
For the given figure find Q point with VCC = 15V, VBE = 0.7V and β = 100.

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Solution:

Stability factor for voltage divider bias:

Stability factor S:

Fig.Thevenin’s equivalent circuit for voltage divider bias

For determining stability factor S for voltage divider bias, consider the
equivalent circuit. Thevenin’s voltage is given by,

R1, R2 are replaced by RB which is the parallel combination of R1 and R2.

Apply KVL to base circuit,

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From above equation, the following points are observed.
1. The ratio RB/RE controls value of stability factor S. If RB/RE<< 1 then it is
reduced to S=
(1+β). 1/ (1+β) = 1
Practically RB/RE not equal to zero. But to have better stability factor S , we have
to keep ratio RB/RE as small as possible.
2. To keep RB/RE small, it is necessary to keep RB small. Due to small value of
R1 and R2, potential divider circuit will draw more current from V CCreducing the
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 life of the battery. Another important aspect is that reducing R B will reduce input
impedance of the circuit, since RB comes in parallel with the input. This reduction
of input impedance in amplifier circuit is not desirable and hence R B cannot be
made very small.
3. Emitter resistance RE is another parameter, it is used to decrease the ratio
RB/RE. Drop across RC will reduce. This shifts the operating point Q which is not
desirable and hence there is limit for increasing RE.
While designing voltage divider bias circuit, the following conditions are to be
satisfied,
S – Small
- Reasonably
RB small
RE - Not very large

4. If ratio RB/RE is fixed, S increases with β. So stability decreases with

increasing
β.
5.Stability factor S is essentially independent of β for small value of S.

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37
 Problem 1:
For the given circuit, VCC = 20V, RC = 2KΩ, β = 50, VBE = 0.2V, R1 = 100KΩ, RE
= 100Ω.

Calculate IB, VCE, IC and stability factor S.

Solution:
R2 is not given. So assume R2 = 10KΩ

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RB = R1*R2
______ = 9.09KΩ
R1+R2
IB = VT-VBE
_____________ = 114µA
RB+ (1+β)RE
IC = βIB = 5.7mA
VCE = VCC – ICRC – (1+β)IBRE
= 8V
S = 1+β
__________________
1+β (RE / (RE+RB))
S = 33

Emitter stabilized bias circuit:

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Circuit analysis:
Base circuit:

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1.12 Compensation technique:
It refers to the use of temperature sensitive devices such as diodes,
transistors, thermistors which provide compensating voltage and current to
maintain Q point stable.

1.12.1 Diode Compensation Techniques

Compensation for VBE:
a) Diode in Emitter Circuit
Diagram shows the voltage divider bias with bias compensation technique.Here,
separate supply VDD is used to keep diode in forward If biased condition. If the diode

41
used in the circuit is of same material and type as the transistor, the voltage across
the diode will have the same
temperature coefficient as the base to emitter voltage VBE . So when VBE changes
by
𝜕𝑉𝐵𝐸 with change in temperature, VD changes by
𝜕𝑉𝐷 and 𝑉𝐷′ = 𝜕𝑉𝐵𝐸 , the changes tend to cancel each other.

Apply KVL to the base circuit of Fig. ,we have

Figure: Stabilization by means of voltage divider bias and diode

Compensation Technique

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As VD tracks VBE with respect to temperature it is clear that IC will be insensitive
to variations in VBE.

Diode in voltage divider circuit

• Diode is connected in series with resistance R2 in the voltage divider

circuit and it is forward biased condition.

When VBE changes with temperature, IC also changes

• To cancel the changes in IC , one diode is used in the circuit for
compensation
• The voltage at the base VB is give as

• Substituting this value in equation IC, we get

•
The changes cancel each other , so the collector current is given as

The changes in VBE. Due to temperature are compensated by changes

in the diode voltage which keeps IC stable at Q point.

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Compensation for ICO:

44
45
 1.12.2 Thermistor Compensation

Fig:1.64 Temperature Vs RT resistance of thermistor

The slope is negative. So we can say that thermistor has negative temperature
coefficient of resistance (NTC). Figure below shows the thermistor compensation
technique.

Fig: Thermistor compensation technique

As shown in the figure above R2 is replaced by thermistor RT in self bias circuit.

With increase of temperature ,RT decreases. Hence the voltage drop across it also
decreases. That is VBE decreases which reduces IB .this will offset the increased
collector current with temperature.

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 The equation shows if there is increase in ICO and decrease in IB
keeps IC almost constant.

Fig below shows another thermistor compensation technique .

Here, thermistor is connected between emitter and Vcc to minimize the

increase in collector current due to changes in ICO, VBE, or beta with
temperature .IC increases with temperature and RT decreases with increase in
temperature. Therefore, current flowing through RE increases, which
increases the voltage drop across it. E - B junction is forward biased. But due
to increase in voltage drop across RE, emitter is made more positive, which
reduces the forward bias voltage VBE. Hence, bias current reduces.

As Ico increases with temperature, IB decreases and hence. IC remains

constant.
Sensistor Compensation technique:

47
 This method of transistor compensation uses temperature sensitive resistive
element, sensistors rather than diodes or transistors. It has a positive temperature
coefficient, its resistance increases exponentially with increasing temperature as
shown in the Fig

𝜕𝑅𝑇
is the temperature coefficient for thermistor and the slope is positive So
𝜕𝑇
we can say that sensistor has positive temperature coefficient of resistance
(PTC).
Fig above shows sensistor compensation R1 is replaced by sensistor RT in self
bias circuit. Now, RT and R2 resistors of the potential divider. As temperature
increases, RT increases which decreases the current flowing through it. Hence
current through R2 decreases which reduces the voltages drop across it. Voltage
drop across R2 is the voltage between base and ground. So VBE reduces which
decreases 16. It means, when ICBO increases with increase in temperature, IB
reduces due to reduction in VBE, maintaining IC fairly constant.

Thermal stability:

48
 Thermal resistance:

Condition for Thermal stability:

49
50
51
52
FET Biasing
• The Parameters of FET is temperature dependent .When temperature
increases drain resistance also increases, thus reducing the drain
current.
• Unlike BJTs, thermal runaway does not occur with FETs
• However, the wide differences in maximum and minimum transfer
characteristics make ID levels unpredictable with simple fixed-gate
bias voltage.
• Different biasing circuits of FET are
1) Fixed bias circuits
2) Self bias circuits
3) Voltage bias circuits

Fixed bias circuits

DC bias of a FET device needs setting of gate-source voltage VGS to give
desired drain current ID . For a JFET drain current is limited by the saturation
current IDS. Since the FET has such a high input impedance that no gate
current flows and the dc voltage of the gate set by a voltage divider or a fixed
battery voltage is not affected or loaded by the FET.

53
Fixed dc bias is obtained using a battery VGG. This battery ensures that the gate is
always negative with respect to source and no current flows through resistor RG and
gate terminal that is IG =0. The battery provides a voltage VGS to bias the N-channel
JFET, but no resulting current is drawn from the battery VGG. Resistor RG is included
to allow any ac signal applied through capacitor C to develop across RG. While any
ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0
volt.
Calculate VGS
For DC analysis IG =0., applying KVL to the input circuits
VGS+ VGG=0

VGS= - VGG

As VGS is a fixed dc supply, hence the name fixed bias circuit

Calculate IDQ
IDQ= IDss(1- VGS/VGp)2
Calculate VDS
This current IDQ then causes a voltage drop across the drain resistor
RD and is given as
VDSQ = VDD – ID RD
Disadvantage
The fixed bias circuit of FET requires two power supplies.

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Self-Bias circuits
Self-Bias circuits is the most common method for biasing a JFET. Self-
bias circuit for N-channel JFET is shown in figure

• The gate source junction of JFET must be always in reverse biased

condition .No gate current flows through the reverse-biased gate-source, the
gate current IG = 0 and, therefore,VG = iG RG = 0

• With a drain current ID, the voltage at the S is

Vs= ID Rs

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1)The gate-source voltage is then

VGS = VG - Vs = 0 – ID RS = – ID RS
So voltage drop across resistance Rs provides the biasing voltage VGs
and no external source is required for biasing and this is the reason
that it is called self-biasing.
2)Calculate IDQ

ID= IDSS(1- VGS/ VP)2

Substituting the value of VGS

ID= IDSS (1+ID RS / VP)2

3)The operating point (that is zero signal ID and VDS) can easily be
determined from equation given below :

VDS = VDD – ID (RD + RS)

Self biasing of a JFET stabilizes its quiescent operating point against

any change in its parameters like transconductance. Any increase in
voltage drop across RS, therefore, gate-source voltage, VGS becomes
more negative and thus increase in drain current is reduced.

Voltage -Divider Bias circuits

The resistors RGl and RG2 form a potential divider across drain supply
VDD. The voltage V2 across RG2 provides the necessary bias. The
additional gate resistor RGl from gate to supply voltage facilitates in
larger adjustment of the dc bias point and permits use of larger valued
RS.

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 The coupling capacitors are assumed to be open circuit for DC analysis
1) The gate is reverse biased so that IG = 0 and gate voltage
VG =V2 = (VDD/R G1 + R G2 ) *RG2
2) Applying KVL to the input circuit we get
VGS = VG – VS = VG - ID RS
3) IDQ= IDSS(1- VGS/ VP)2
4) VDS = VDD – ID (RD + RS)
The operating point of a JFET amplifier using the Voltage -Divider Bias
is determined by

IDQ= IDSS(1- VGS/ VP)2

VDSQ = VDD – ID (RD + RS)
VGSQ = VG – ID RS

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