Topic 11

Logical Effort: Outline

Designing for Speed on the Back of an Envelope

o Introduction

David Harris o Delay in a Logic Gate

[email protected]
o Multi-stage Logic Networks
o Choosing the Best Number of Stages
o Example
Harvey Mudd College
o Asymmetric & Skewed Logic Gates
Claremont, CA
o Circuit Families
o Summary

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Introduction Example

Chip designers face a bewildering array of choices. ? ? ? Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded
processor for automotive applications. Help Ben design the decoder for a
o What is the best circuit topology for a function?
register file: a<3:0> a<3:0> 32 bits
o How large should the transistors be?
o How many stages of logic give least delay?

4:16 Decoder
Decoder specification:

16 words
Register File
Logical Effort is a method of answering these questions: o 16 word register file 16
o Each word is 32 bits wide
o Uses a very simple model of delay
o Back of the envelope calculations and tractable optimization
o Each bit presents a load of 3 unit-sized transistors
o True and complementary inputs of address bits a<3:0> are available
o Gives new names to old ideas to emphasize remarkable symmetries
o Each input may drive 10 unit-sized transistors
Who cares about logical effort?
Ben needs to decide:
o Circuit designers waste too much time simulating and tweaking circuits
o High speed logic designers need to know where time is going in their logic
o How many stages to use?
o How large should each gate be?
o CAD engineers need to understand circuits to build better tools
o How fast can the decoder operate?

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 Outline Delay in a Logic Gate

o Introduction Let us express delays in a process-independent unit:

τ ≈ 12 ps
o Delay in a Logic Gate d abs in 0.18 μm
d = ----------
-
o Multi-stage Logic Networks τ technology
o Choosing the Best Number of Stages Delay of logic gate has two components:
o Example
effort delay, a.k.a. stage effort
o Asymmetric & Skewed Logic Gates
parasitic delay
o Circuit Families d = f+p
o Summary Effort delay again has two components:

logical effort electrical effort

electrical effort = Cout/Cin is sometimes
f = gh called “fanout”

o Logical effort describes relative ability of gate topology to deliver current

(defined to be 1 for an inverter)
o Electrical effort is the ratio of output to input capacitance

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Delay Plots Delay Plots

6 g= 6 g = 4/3
p=
D
Normalized delay: d

5
AN

d= p=2

D
Normalized delay: d
g= 5

AN
N

g=1d = (4/3)h + 2
4 p=
ut

N
r
rte
inp

d= 4 p=1

ut

r
ve

rte
inp
d=h+1
2-

3
in

ve
2-
effort How about a 3

in
2 delay 2-input NOR? effort
2 delay
1
parasitic delay 1
parasitic delay
1 2 3 4 5
Electrical effort: h = Cout / Cin 1 2 3 4 5
Electrical effort: h = Cout / Cin

o d = f + p = gh + p o d = f + p = gh + p
o Delay increases with electrical effort o Delay increases with electrical effort
o More complex gates have greater logical effort and parasitic delay o More complex gates have greater logical effort and parasitic delay

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 Computing Logical Effort A Catalog of Gates

DEF: Logical effort is the ratio of the input capacitance of a gate to the input Table 1: Logical effort of static CMOS gates
capacitance of an inverter delivering the same output current. Number of inputs
Gate type
o Measured from delay vs. fanout plots of simulated or measured gates 1 2 3 4 5 n

o Or estimated, counting capacitance in units of transistor width: inverter 1

NAND 4/3 5/3 6/3 7/3 (n+2)/3
NOR 5/3 7/3 9/3 11/3 (2n+1)/3
a NOR2: multiplexer 2 2 2 2 2
2 4 Cin = 5
b XOR, XNOR 4 12 32
2 2 g = 5/3
x 4 Table 2: Parasitic delay of static CMOS gates
x
Gate type Parasitic delay
x
a 2 inverter pinv p inv ≈ 1
1
a 1 parasitic delays
n-input NAND npinv
Inverter: NAND2: b depend on diffusion
2 1 n-input NOR npinv capacitance
Cin = 3 Cin = 4
g = 4/3 n-way multiplexer 2npinv
g = 1 (def)
2-input XOR, XNOR 4npinv

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Example Example

Estimate the frequency of an N-stage ring oscillator: Estimate the frequency of an N-stage ring oscillator:

Logical Effort: g = Logical Effort: g≡1

Electrical Effort: h = C out
Electrical Effort: h = --------- = 1
Parasitic Delay: p = C in

Stage Delay: d = Parasitic Delay: p = p inv ≈ 1

Oscillator Frequency: F = Stage Delay: d = gh + p = 2 A 31 stage ring
oscillator in a
1 1 0.18 μm process
Oscillator Frequency: F = ------------------- = ----------- oscillates at about
2Nd abs 4N τ 670 MHz.

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 Example Example

Estimate the delay of a fanout-of-4 (FO4) inverter: Estimate the delay of a fanout-of-4 (FO4) inverter:
d d

Logical Effort: g = Logical Effort: g≡1

Electrical Effort: h = C out The FO4 inverter
Electrical Effort: h = --------- = 4
Parasitic Delay: p = C in delay is a useful
metric to characterize
Stage Delay: d = Parasitic Delay: p = p inv ≈ 1 process performance.

Stage Delay: d = gh + p = 5 1 FO4 delay = 5τ

This is about 60 ps
in a 0.18 μm process.

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Outline Multi-stage Logic Networks

o Introduction Logical effort extends to multi-stage networks:

o Delay in a Logic Gate
10
x y
o Multi-stage Logic Networks z 20
o Choosing the Best Number of Stages
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
o Example
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
o Asymmetric & Skewed Logic Gates
o Circuit Families
o Summary o Path Logical Effort: G = ∏ gi Don’t define

o Path Electrical Effort:

C out (path)
H = ---------------------
C in (path)
-
H = ∏ hi
because we don’t
know hi until the
o Path Effort: F = ∏ fi = ∏ g i h i design is done

Can we write F = GH ?

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 Branching Effort Branching Effort

No! Consider circuits that branch: No! Consider circuits that branch:
15 G = 15 G =1
H = H = 90 / 5 = 18
90 GH = 90 GH = 18
5 5
h1 = h1 = (15+15) / 5 = 6
15 h2 = 15 h2 = 90 / 15 = 6
90 F = = GH? 90 F = 36, not 18!

Introduce new kind of effort to account for branching within a network:

C on path + C
o Branching Effort: off path
b = ---------------------------------------------
-
C on path

o Path Branching Effort: B = ∏ bi Note:

Now we can compute the path effort:

∏ hi = BH ≠ H
in circuits that branch
o Path Effort: F = GBH

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Delay in Multi-stage Networks Determining Gate Sizes

We can now compute the delay of a multi-stage network: Gate sizes can be found by starting at the end of the path and working backward.
o At each gate, apply the capacitance transformation:
o Path Effort Delay: DF = ∑ fi C out • g i
PF = ∑ pi
i
o Path Parasitic Delay: C in = ----------------------
-
i ˆf

o Path Delay: DF = ∑ di = D F + P o Check your work by verifying that the input capacitance specification is satis-
fied at the beginning of the path.
We can prove that delay is minimized when each stage bears the same effort:
ˆf = g h = F 1 ⁄ N
i i
Therefore, the minimum delay of an N-stage path is:
1⁄N
NF +P
o This is a key result of logical effort. Lowest possible path delay can be found
without even calculating the sizes of each gate in the path.

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 Example Example

Select gate sizes y and z to minimize delay z Select gate sizes y and z to minimize delay z
9C 9C
from A to B y from A to B y
z z
A 9C A 9C
C C
Logical Effort: G = y z 3 y z
B Logical Effort: G = (4 ⁄ 3) B
9C 9C
Electrical Effort: H = C out
Branching Effort: B = Electrical Effort: H = --------- = 9
C in
Path Effort: F = Branching Effort: B = 2•3 = 6
Best Stage Effort:
ˆf = Path Effort: F = GHB = 128
Delay: D = ˆf = F 1 ⁄ 3 ≈ 5 Work backward for sizes:
Best Stage Effort:
9C • (4 ⁄ 3)
z = ----------------------------- = 2.4 C
Work backward for sizes: 5
z = Delay: D = 3 • 5 + 3 • 2 = 21 • ( 4 ⁄ 3)
y = 3z
---------------------------- = 1.92 C
y = 5

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Outline Choosing the Best Number of Stages

o Introduction How many stages should a path use?

o Delay in a Logic Gate o Delay is not always minimized by using as few stages as possible
o Multi-stage Logic Networks o Example: How to drive 64 bit datapath with unit-sized inverter
o Choosing the Best Number of Stages
Initial driver
1 1 1 1
o Example 8 4 2.8
o Asymmetric & Skewed Logic Gates
16 8
o Circuit Families
o Summary 22.6

Datapath load
64 64 64 64
Fastest
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
1⁄N 1⁄N
D = NF + P = N ( 64 ) + N assuming polarity doesn’t matter

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 Derivation of the Best Number of Stages Best Number of Stages (continued)

Suppose we can add inverters to the end of a path without changing its function. p inv + ρ ( 1 – ln ρ ) = 0 has no closed form solution.
o ˆ
How many stages should we use? Let N be the value of N for least delay. o Neglecting parasitics (i.e. pinv = 0), we get the familiar result that ρ = 2.718 (e)
Logic Block: N-n1 extra inverters o For pinv = 1, we can solve numerically to obtain ρ = 3.59
n1 stages How sensitive is the delay to using exactly the best number of stages?
Path effort F
1 .6

D(N) / D(N)
n1 1 .5 1
1 .4
1 .2 6
1⁄N
D = NF +
∑ p i + ( N – n 1 ) p inv 1 .2
1 .0
1 .1 5

I like to use
1 ρ=4
(ρ = 2 .4 ) (ρ = 6 )
∂D 1⁄N 1⁄N 1⁄N
------- = – F ln ( F )+F + p inv = 0
∂N
ˆ 0 .0
1⁄N 0 .5 0 .7 1 .0 1 .4 2 .0
o Define ρ ≡ F to be the best stage effort. Substitute and simplify:
N /N
p inv + ρ ( 1 – ln ρ ) = 0 o 2.4 < ρ < 6 gives delays within 15% of optimal -> we can be sloppy

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Outline Example

o Introduction Let’s revisit Ben Bitdiddle’s decoder problem using logical effort:
a<3:0> a<3:0> 32 bits
o Delay in a Logic Gate
o Multi-stage Logic Networks

4:16 Decoder

16 words
o Choosing the Best Number of Stages Decoder specification:
Register File
o Example o 16 word register file 16
o Asymmetric & Skewed Logic Gates o Each word is 32 bits wide
o Circuit Families o Each bit presents a load of 3 unit-sized transistors
o Summary o True and complementary inputs of address bits a<3:0> are available
o Each input may drive 10 unit-sized transistors

Ben needs to decide:

o How many stages to use?
o How large should each gate be?
o How fast can the decoder operate?

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 Example: Number of Stages Example: Number of Stages

How many stages should Ben use? How many stages should Ben use?
o Effort of decoders is dominated by electrical and branching portions o Effort of decoders is dominated by electrical and branching portions
o Electrical Effort: H = o Electrical Effort:
32 • 3- = 9.6
H = --------------
o Branching Effort: B = 10
o Branching Effort: B = 8 because each address input
If we neglect logical effort (assume G = 1), controls half the outputs

o Path Effort: F =
If we neglect logical effort,
Remember that the best stage effort is about ρ = 4 o Path Effort: F = GBH = 8 • 9.6 = 76.8
o Hence, the best number of stages is: N =
Remember that the best stage effort is about ρ = 4
o Hence, the best number of stages is: N = log 476.8 = 3.1
o Let’s try a 3-stage design

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Example: Gate Sizes & Delay Example: Gate Sizes & Delay

Lets try a 3-stage design using 16 4-input NAND gates with G = Lets try a 3-stage design using 16 4-input NAND gates with G = 1 • 2 • 1 = 2
a0a0 a1a1 a2a2 a3a3 a0a0 a1a1 a2a2 a3a3
10 unit input capacitance 10 unit input capacitance

y out0 y out0
z z
96 unit wordline 96 unit wordline
capacitance capacitance

y out15 y out15
z z

o Actual path effort is: F = o Actual path effort is: F = 2 • 8 • 9.6 = 154 Close to
o Therefore, stage effort should be: f = o Therefore, stage effort should be: f = ( 154 ) = 5.36
1⁄3 4, so f is
reasonable
o Gate sizes: z = y = o z = 96 • 1 ⁄ 5.36 = 18 y = 18 • 2 ⁄ 5.36 = 6.7
o Path delay: D = o D = 3f + P = 3 • 5.36 + 1 + 4 + 1 = 22.1

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 Example: Alternative Decoders Outline

Table 3: Comparison of Decoder Designs

o Introduction
Design Stages G P D
o Delay in a Logic Gate
NAND4; INV 2 2 5 29.8
INV; NAND4; INV 3 2 6 22.1
o Multi-stage Logic Networks
INV; NAND4; INV; INV 4 2 7 21.1
o Choosing the Best Number of Stages
NAND2; INV; NAND2; INV 4 16/9 6 19.7 o Example
INV; NAND2; INV; NAND2; INV 5 16/9 7 20.4 o Asymmetric & Skewed Logic Gates
NAND2; INV; NAND2; INV; INV; INV 6 16/9 8 21.6 o Circuit Families
INV; NAND2; INV; NAND2; INV; INV; INV 7 16/9 9 23.1
o Summary
NAND2; INV; NAND2; INV; INV; INV; INV; INV 8 16/9 10 24.8

We underestimated the best number of stages by neglecting the logical effort.

o Logical effort facilitates comparing different designs before selecting sizes
o Using more stages also reduces G and P by using multiple 2-input gates
o Our design was about 10% slower than the best

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Asymmetric Gates Asymmetric Gates

Asymmetric logic gates favor one input over another. Asymmetric logic gates favor one input over another.
Example: suppose input A of a NAND gate is most critical. Example: Suppose input A of a NAND gate is most critical:
o Select sizes so pullup and pulldown still match unit inverter o Select sizes so pullup and pulldown still match unit inverter
o Place critical input closest to output o Place critical input closest to output

2 2
2 2
x
x a 4/3
a 4/3
4 b
4 b
Effort on A
o Logical Effort on input A: g A = 10 ⁄ 9 goes down at
o Logical Effort on input A: gA = expense of
o Logical Effort on input B: gB = 2 effort on B and
o Logical Effort on input B: gB = total gate effort
o Total Logical Effort: g tot = g A + g B = 28 ⁄ 9
o Total Logical Effort: g tot = g A + g B

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 Symmetry Factor Skewed Gates

In general, consider gates with arbitrary symmetry factor s: Skewed gates favor one edge over the other.
o s = 1/2 in symmetric gate with equal sizes Example: suppose rising output of inverter is most critical.
2 2
o s = 1/4 in previous example
x
o Downsize noncritical NMOS transistor to reduce total input capacitance
a 1/(1-s)
2 2 1
1/s b x x x
Logical effort of inputs: a 1/2 a 1 a 1/2
1
------------ + 2
1
--- + 2
1
-------------------- + 4
1 –s s s (1 – s) HI-Skewed inverter
Unskewed w/ Unskewed w/
gA = ---------------------- gB = ------------- g tot = ------------------------------ equal rise equal fall
3 3 3
Compare with unskewed inverter of the same rise/fall time to compute effort.
o Critical input approaches logical effort of inverter = 1 for small s
o Logical Effort for rising (up) output: gu =
o But total logical effort is higher for asymmetric gates
o Logical Effort for falling (down) output: gd =
o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2

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Skewed Gates HI- and LO-Skewed Gates

Skewed gates favor one edge over the other. DEF: Logical effort of a skewed gate for a particular transition is the ratio of the
Example: suppose rising output of inverter is most important. input capacitance of that gate to the input capacitance of an unskewed
inverter delivering the same output current for the same transition.
o Downsize noncritical NMOS transistor to reduce total input capacitance

Skew gates by reducing size of noncritical transistors.

2 2 1
x x x
o HI-Skewed gates favor rising outputs by downsizing NMOS transistors

a a a
o LO-Skewed gates favor falling outputs by downsizing PMOS transistors
1/2 1 1/2
o Logical effort is smaller for the favored input due to lower input capacitance
Skewed inverter
Unskewed w/ Unskewed w/ o Logical effort is larger for the other input
equal rise equal fall
Compare with unskewed inverter of the same rise/fall time Critical rising
effort goes down
o Logical Effort for rising (up) output: gu = 5 ⁄ 6 at expense of
noncritical and
o Logical Effort for falling (down) output: g d = 5 ⁄ 3 average effort
o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2 = 5 ⁄ 4

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 Catalog of Skewed Gates Outline

Inverter NAND2 NOR2

o Introduction
o Delay in a Logic Gate
2 4
gu = 3/2
gd = 3
o Multi-stage Logic Networks
2
2
4 gavg = 9/4 o Choosing the Best Number of Stages
HI-Skew
½ gu = 5/6 1
gu = 1
o Example
gd = 5/3
gavg = 5/4 1
gd = 2 ½
½
o Asymmetric & Skewed Logic Gates
gavg = 3/2
o Circuit Families
o Summary

1 2
gu = 2
1
gd = 1
1
2 gavg = 3/2
LO-Skew
1 gu = 4/3 2
gu = 2
gd = 2/3 1
2
gd = 1 1
gavg = 1
gavg = 3/2

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Pseudo-NMOS Pseudo-NMOS

Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup. Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.
o Resistive pullup must be much weaker than pulldown stack (e.g. 4x) o Resistive pullup must be much weaker than pulldown stack (e.g. 4x)
o Reduces logical effort because inputs must only drive the NMOS transistors o Reduces logical effort because inputs must only drive the NMOS transistors
o However, NMOS current reduced by contention with pullup o However, NMOS current reduced by contention with pullup
o Unequal rising and falling efforts o Unequal rising and falling efforts
o Quiescent power dissipation when output is low o Logical effort can be applied to domino, pseudo-NMOS, and other logic families

2/3 2/3
Example: Pseudo-NMOS inverter Example: Pseudo-NMOS inverter x
x
o Logical Effort for falling (down) output: gd = a
o Logical Effort for falling (down) output: gd = 4 ⁄ 9 a 4/3
4/3
o Logical Effort for rising (up) output: gu = o Logical Effort for rising (up) output: gu = 4 ⁄ 3
o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2 o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2 = 8 ⁄ 9

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 Pseudo-NMOS Gates Dynamic Logic

Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge.
Inverter NAND2 NOR2 o Reduces logical effort because inputs must only drive the NMOS transistors
o Eliminates pseudo-NMOS contention current and power dissipation
2/3 2/3 2/3 o Only the falling (“evaluation”) delay is critical
x x x
4/3
o Downsize noncritical precharge transistors to reduce clock load and power
a 4/3 a 8/3 a 4/3
b

b 8/3 φ
Example: Footless dynamic inverter 1
x
gd = 4/9 gd = 8/9 gd = 4/9 o Logical Effort for falling (down) output: gd = a
gu = 4/3 gu = 8/3 gu = 4/3 1
gavg = 8/9 gavg = 16/9 gavg = 8/9

Robust gates may require keepers and clocked pulldown transistors (“feet”).
Tradeoffs exist between power and effort by varying P/N ratio. o Feet prevent contention during precharge but increase logical effort
o Weak keepers prevent floating output at cost of slight contention during eval

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Dynamic Logic Dynamic Gates

Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge. Inverter NAND2 NOR2
o Reduces logical effort because inputs must only drive the NMOS transistors
φ 1 φ 1 φ 1
o Eliminates pseudo-NMOS contention current and power dissipation
x
x x
o Critical pulldown (“evaluation”) delay independent of precharge size Footless
a
a 1 2 a 1 1 b
gd = 1/3 gd = 2/3 gd = 1/3
b 2
φ 1
Example: Footless dynamic inverter
x
o Logical Effort for falling (down) output: gd = 1 ⁄ 3 a 1
φ 1 φ 1 φ 1
x x x
Footed
Robust gates may require keepers and clocked pulldown transistors (“feet”). a 2 a 3 a 2 2 b

o Feet prevent contention during precharge but increase logical effort gd = 2/3 b 3 gd = 1 gd = 2/3
φ 2 φ 2
o Weak keepers prevent floating output at cost of slight contention during eval φ 3

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 Domino Gates Domino Gates

Dynamic gates require monotonically rising inputs. Dynamic gates require monotonically rising inputs.
o However, they generate monotonically falling outputs o However, they generate monotonically falling outputs
o Alternate dynamic gates with HI-skew inverting static gates o Alternate dynamic gates with HI-skew inverting static gates
o Dynamic / static pair is called a domino gate o Dynamic / static pair is called a domino gate

Example: Domino Buffer Example: Domino Buffer

o Constraints: maximum input capacitance = 3, load = 54 o Constraints: maximum input capacitance = 3, load = 54
o Logical Effort: G= o Logical Effort: G = (1/3) * (5/6) = 5/18
o Branching Effort: B = o Branching Effort: B = 1
o Electrical Effort: H= φ 3 p HI-Skew o Electrical Effort: H = 54/3 = 18 φ 3 p HI-Skew
o Path Effort: F= 54 o Path Effort: F = (5/18) * 1 * 18 = 5 54
a 3 n a 3 n
o Stage Effort: f= o Stage Effort: f= 5 = 2.2
o HI-Skew Inverter: size =
g1 g2 o HI-Skew Inverter: size =54 * (5/6) / 2.2 = 20 g1 = 1/3 g2 = 5/6
o Transistor Sizes: n = p = o Transistor Sizes: n = 4 p = 16

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Comparison of Circuit Families Outline

Assumptions: o Introduction
o PMOS transistors have half the drive of NMOS transistors o Delay in a Logic Gate
o Skewed gates downsize noncritical transistors by factor of two o Multi-stage Logic Networks
o Pseudo-NMOS gates have 1/4 strength pullups o Choosing the Best Number of Stages
Table 4: Summary of Logical Efforts o Example
Inverter g n-input NAND g n-input NOR g o Asymmetric & Skewed Logic Gates
Circuit Style
gu gd gu gd gu gd o Circuit Families
Static CMOS 1 (n+2)/3 (2n+1)/3 o Summary
HI-Skew 5/6 5/3 (n/2+2)/3 (n+4)/3 (2n+.5)/3 (4n+1)/3
LO-Skew 4/3 2/3 2(n+1)/3 (n+1)/3 2(n+1)/3 (n+1)/3
Pseudo-NMOS 4/3 4/9 4n/3 4n/9 4/3 4/9
Footed Dynamic 2/3 (n+1)/3 2/3
Footless Dynamic 1/3 n/3 1/3

Adjust these numbers as you change your assumptions.

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 Summary Method of Logical Effort

Table 5: Key Definitions of Logical Effort Logical effort helps you find the best number of stages, the best size of each gate,
Term Stage expression Path expression and the minimum delay of a circuit with the following procedure:

∏ gi
Logical effort g (seeTable 1) G =
Electrical effort C C
o Compute the path effort: F = GBH
out out (path)
h = --------- H = ---------------------
- ˆ ≈ log F
C in C in (path) o Estimate the best number of stages: N 4
Branching effort n/a ˆ
B = ∏ bi o Estimate the minimum delay: D = N̂F
1⁄N
+P
Effort f = gh F = GBH o Sketch your path using the number of stages computed above
Effort delay f ˆf = F 1 ⁄ N
DF = ∑ fi o Compute the stage effort:

Number of stages 1 o Starting at the end, work backward to find transistor sizes:
N
C out • g i
∑
Parasitic delay p (seeTable 2) P = pi i
C in = ----------------------
-
i ˆf
Delay d = f+p D = DF + P

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Limitations of Logical Effort Conclusion

Logical effort is not a panacea. Some limitations include: Logical effort is a useful concept for thinking about delay in circuits:
o Facilitates comparison of different circuit topologies
o Chicken & egg problem o Easily select gate sizes for minimum delay
how to estimate G and best number of stages before the path is designed o Circuits are fastest when effort delays of each stage are equal and about 4
o Simplistic delay model o Path delay is insensitive to modest deviations from optimal sizes
neglects effects of input slopes o Logic gates can be skewed to favor one input or edge at the cost of another
o Interconnect o Logical effort can be applied to domino, pseudo-NMOS, and other logic families
iteration required in designs with branching and non-negligible wire C or RC
same convergence difficulties as in synthesis / placement problem Logical effort provides a language for engineers to discuss why circuits are fast.
o Maximum speed only o Like any language, requires practice to master
optimizes circuits for speed, not area or power under a fixed speed constraint
A book on Logical Effort is available from Morgan Kaufmann Publishers
o http://www.mkp.com/Logical_Effort
o Discusses P/N ratios, gate characterization, pass gate logic, forks, wires, etc.

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 Delay Plots Example

Estimate the frequency of an N-stage ring oscillator:

6 g = 4/3
p=2

D
Normalized delay: d
5

AN
g=1d = (4/3)h + 2

N
4 p=1

ut

r
rte
inp
d=h+1

ve
2-
3 g≡1

in
Logical Effort:
effort
2 delay C out
Electrical Effort: h = --------- = 1
1 C in
parasitic delay
Parasitic Delay: p = p inv ≈ 1
1 2 3 4 5
Electrical effort: h = Cout / Cin
Stage Delay: d = gh + p = 2 A 31 stage ring
oscillator in a
1 1 0.18 μm process
Oscillator Frequency: F = ------------------- = ----------- oscillates at about
o d = f + p = gh + p 2Nd abs 4N τ 670 MHz.
o Delay increases with electrical effort
o More complex gates have greater logical effort and parasitic delay

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Example Branching Effort

Estimate the delay of a fanout-of-4 (FO4) inverter: No! Consider circuits that branch:
d 15 G =1
H = 90 / 5 = 18
90 GH = 18
5
h1 = (15+15) / 5 = 6
15 h2 = 90 / 15 = 6
90 F = 36, not 18!

Logical Effort: g≡1

Introduce new kind of effort to account for branching within a network:
C out The FO4 inverter
Electrical Effort: h = --------- = 4 C on path + C
C in delay is a useful
metric to characterize o Branching Effort: off path
b = ---------------------------------------------
-
C on path
Parasitic Delay: p = p inv ≈ 1 process performance.

Stage Delay: d = gh + p = 5 1 FO4 delay = 5τ o Path Branching Effort: B = ∏ bi Note:

This is about 60 ps
in a 0.18 μm process. Now we can compute the path effort:
∏ hi = BH ≠ H
in circuits that branch
o Path Effort: F = GBH

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 Example Example: Number of Stages

Select gate sizes y and z to minimize delay z How many stages should Ben use?
9C
from A to B y z o Effort of decoders is dominated by electrical and branching portions
A 9C 32 • 3- = 9.6
C
y o Electrical Effort: H = --------------
3 z B 10
Logical Effort: G = (4 ⁄ 3) 9C o Branching Effort: B = 8 because each address input
C out controls half the outputs
Electrical Effort: H = --------- = 9
C in
Branching Effort: B = 2•3 = 6 If we neglect logical effort,
Path Effort: F = GHB = 128 o Path Effort: F = GBH = 8 • 9.6 = 76.8
ˆf = F 1 ⁄ 3 ≈ 5 Work backward for sizes:
Best Stage Effort: Remember that the best stage effort is about ρ = 4
9C • (4 ⁄ 3)
z = ----------------------------- = 2.4 C
5 o Hence, the best number of stages is: N = log 476.8 = 3.1
Delay: D = 3 • 5 + 3 • 2 = 21 • ( 4 ⁄ 3) o
y = 3z
---------------------------- = 1.92 C Let’s try a 3-stage design
5

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Example: Gate Sizes & Delay Asymmetric Gates

Lets try a 3-stage design using 16 4-input NAND gates with G = 1 • 2 • 1 = 2 Asymmetric logic gates favor one input over another.
a0a0 a1a1 a2a2 a3a3 Example: Suppose input A of a NAND gate is most critical:
10 unit input capacitance o Select sizes so pullup and pulldown still match unit inverter
o Place critical input closest to output

y out0 2 2
z
96 unit wordline x
capacitance
a 4/3

y out15 4 b
z
Effort on A
o Actual path effort is: F = 2 • 8 • 9.6 = 154 Close to o Logical Effort on input A: g A = 10 ⁄ 9 goes down at
expense of
4, so f is o
o Therefore, stage effort should be: f = ( 154 )1 ⁄ 3 = 5.36 reasonable
Logical Effort on input B: gB = 2 effort on B and
total gate effort
o z = 96 • 1 ⁄ 5.36 = 18 y = 18 • 2 ⁄ 5.36 = 6.7 o Total Logical Effort: g tot = g A + g B = 28 ⁄ 9
o D = 3f + P = 3 • 5.36 + 1 + 4 + 1 = 22.1

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 Skewed Gates Pseudo-NMOS

Skewed gates favor one edge over the other. Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.
Example: suppose rising output of inverter is most important. o Resistive pullup must be much weaker than pulldown stack (e.g. 4x)
o Downsize noncritical NMOS transistor to reduce total input capacitance o Reduces logical effort because inputs must only drive the NMOS transistors
o However, NMOS current reduced by contention with pullup
2 2 1 o Unequal rising and falling efforts
x x x o Logical effort can be applied to domino, pseudo-NMOS, and other logic families
a 1/2 a 1 a 1/2

Skewed inverter Unskewed w/ Unskewed w/ 2/3

Example: Pseudo-NMOS inverter x
equal rise equal fall
Compare with unskewed inverter of the same rise/fall time Critical rising o Logical Effort for falling (down) output: gd = 4 ⁄ 9 a 4/3
effort goes down
o Logical Effort for rising (up) output: gu = 5 ⁄ 6 at expense of o Logical Effort for rising (up) output: gu = 4 ⁄ 3
noncritical and
o Logical Effort for falling (down) output: g d = 5 ⁄ 3 average effort o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2 = 8 ⁄ 9
o Average Logical Effort: g avg = ( g u + g d ) ⁄ 2 = 5 ⁄ 4

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Dynamic Logic Domino Gates

Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge. Dynamic gates require monotonically rising inputs.
o Reduces logical effort because inputs must only drive the NMOS transistors o However, they generate monotonically falling outputs
o Eliminates pseudo-NMOS contention current and power dissipation o Alternate dynamic gates with HI-skew inverting static gates
o Critical pulldown (“evaluation”) delay independent of precharge size o Dynamic / static pair is called a domino gate

Example: Domino Buffer

φ 1
Example: Footless dynamic inverter
x
o Constraints: maximum input capacitance = 3, load = 54
o Logical Effort for falling (down) output: gd = 1 ⁄ 3 a
o Logical Effort: G = (1/3) * (5/6) = 5/18
1
o Branching Effort: B = 1
o Electrical Effort: H = 54/3 = 18 φ 3 p HI-Skew
Robust gates may require keepers and clocked pulldown transistors (“feet”). o Path Effort: F = (5/18) * 1 * 18 = 5 54
a 3 n
o Feet prevent contention during precharge but increase logical effort o Stage Effort: f= 5 = 2.2
o Weak keepers prevent floating output at cost of slight contention during eval o HI-Skew Inverter: size =54 * (5/6) / 2.2 = 20 g1 = 1/3 g2 = 5/6
o Transistor Sizes: n = 4 p = 16

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