VHDL – Fundamental concepts

Basic language organisation

fa
a
sum

b
cout
cin

Dept. of E&C, NITKS August 2006

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 fulladder.vhd
entity FullAdder is
port (a, b, cin : in bit; sum, cout : out bit);
end FullAdder;
architecture FullAdder_eqns of FullAdder is
begin
sum <= a xor b xor cin; -- signal assignment
cout <= (a and b) or (a and cin) or (b and cin);
end FullAdder_eqns;

Dept. of E&C, NITKS August 2006

entity - architecture
„ Design entity
„ component of a digital system
„ Entity declaration
„ defines the interface
„ Architecture body
„ defines functionality, allows different implementations

Dept. of E&C, NITKS August 2006

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 entity
entity entity_name is
port (signal_name : mode signal_type;
…..
);
end entity_name;

„ mode - signal direction in out buffer inout

„ port
„ identifier , reserved words - not case sensitive
„ signal_type - built in or user defined
Dept. of E&C, NITKS August 2006

architecture body
architecture fa_eqns of fa is
begin
sum <= a xor b xor cin; -- signal assignment
cout <= (a and b) or (a and cin) or (b and cin);
end fa_eqns;

„ concurrent signal assignment statements

„ assignment operator <=
„ external interface inherited from entity
Dept. of E&C, NITKS August 2006

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 Concurrent signal assignment statements

„ Output changes value whenever any of the

signals on the right change value
„ Textual order has no effect on order of
execution

int1 <= A and not B; int1 <= A and not B;

int2 <= not A and B; z <= int1 or int2;
z <= int1 or int2; int2 <= not A and B;

Dept. of E&C, NITKS August 2006

Logical operators
„ not
„ and or xor xnor nand nor

„ Operator precedence
„ Evaluated left to right
„ Short circuit operators – and, or, nand, nor
„ Need for parentheses

Dept. of E&C, NITKS August 2006

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 architecture
„ As a set of concurrent assignment statements
„ dataflow

„ As a set of interconnected components

„ Structure

„ As a set of sequential statements

„ behaviour

Dept. of E&C, NITKS August 2006

Language organisation

Lib • Design units are conceptually stored in

libraries
DU • Statements are contained in design units
Statements • Statements describe functionality
Expressions • Expressions combine operations with
objects to yield new values
Objects
• Objects hold values of defined data types
Types
• Predefined or user defined data types

Dept. of E&C, NITKS August 2006

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 Design units
„ Primary design units
„ Entity declaration
„ Package declaration
„ Configuration declaration
„ Secondary design units
„ Architecture body
„ Package body

Dept. of E&C, NITKS August 2006

Structural model of a 4 bit adder

Dept. of E&C, NITKS August 2006

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 Structural model of a 4 bit adder
entity Adder4 is
port (A, B: in bit_vector(3 downto 0); Ci: in bit; -- Inputs
S: out bit_vector(3 downto 0); Co: out bit); -- Outputs
end Adder4;

architecture Structure of Adder4 is

component FullAdder
port (X, Y, Cin: in bit;
Sum, Cout: out bit);
end component;
signal C: bit_vector(3 downto 1);
begin --instantiate four copies of the FullAdder
FA0: FullAdder port map (A(0), B(0), Ci, S(0), C(1));
FA1: FullAdder port map (A(1), B(1), C(1), S(1), C(2));
FA2: FullAdder port map (A(2), B(2), C(2), S(2), C(3));
FA3: FullAdder port map (A(3), B(3), C(3), S(3), Co);
Dept.end Structure;
of E&C, NITKS August 2006

„ signal
„ named wire in logic diagram

„ Read or written to within architecture

„ component declaration
„ ports declared as in entity

„ virtual design entities

„ component instantiation
„ creates an instance of the component

„ port map – defines interconnections

„ Positional association
„ FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

„ Named association
„ FA0: FullAdder port map (X => A(0), Y => B(0), Sum
=>S(0), Cin => Ci, Cout => C(1));

Dept. of E&C, NITKS August 2006

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 Behavioral model of adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity vadd is
port (A, B: in unsigned (3 downto 0); -- Inputs
S: out unsigned (4 downto 0);); -- Outputs
end vadd;
architecture behav of vadd is
begin
add: process (A,B)
S <= (‘0’ & A) + (‘0’ & B);
end process add;
end behav;

Dept. of E&C, NITKS August 2006

Mixed Behavior and Structure

„ An architecture can contain both behavioral and
structural parts
„ process statements and component instances

„ collectively called concurrent statements

„ processes can read and assign to signals

„ Example: register-transfer-level model

„ data path described structurally

„ control section described behaviorally

Dept. of E&C, NITKS August 2006

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 Mixed Example - multiplier
multiplier multiplicand

shift_reg

control_ shift_
section adder

reg

product
Dept. of E&C, NITKS August 2006

entity multiplier is
port ( clk, reset : in bit;
multiplicand, multiplier : in integer;
product : out integer );
end entity multiplier;

architecture mixed of mulitplier is

signal partial_product, full_product : integer;
signal arith_control, result_en, mult_bit, mult_load : bit;
begin
arith_unit : entity work.shift_adder(behavior)
port map ( addend => multiplicand, augend => full_product,
sum => partial_product,
add_control => arith_control );
result : entity work.reg(behavior)
port map ( d => partial_product, q => full_product,
en => result_en, reset => reset );
...
Dept. of E&C, NITKS August 2006

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 …
multiplier_sr : entity work.shift_reg(behavior)
port map ( d => multiplier, q => mult_bit,
load => mult_load, clk => clk );
product <= full_product;
control_section : process is
-- variable declarations for control_section
-- …
begin
-- sequential statements to assign values to control signals
-- …
wait on clk, reset;
end process control_section;
end architecture mixed;

Dept. of E&C, NITKS August 2006

Test Benches
„ Testing a design by simulation
„ Use a test bench model
„ an architecture body that includes an instance of
the design under test
„ applies sequences of test values to inputs
„ monitors values on output signals
„ either using simulator

„ or with a process that verifies correct operation

Dept. of E&C, NITKS August 2006

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 Basic Design Methodology
Requirements

RTL Model Simulate

Synthesize

Gate-level
Model Simulate Test Bench

ASIC or FPGA Place & Route

Timing
Model Simulate
Dept. of E&C, NITKS August 2006

Analysis
„ Check for syntax and semantic errors
„ syntax: grammar of the language

„ semantics: the meaning of the model

„ Analyze each design unit separately

„ entity declaration

„ architecture body

„ …

„ best if each design unit is in a separate file

„ Analyzed design units are placed in a library

„ in an implementation dependent internal form
„ current library is called work
Dept. of E&C, NITKS August 2006

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 Elaboration
„ “Flattening” the design hierarchy
„ create ports
„ create signals and processes within architecture body
„ for each component instance, copy instantiated entity and
architecture body
„ repeat recursively
„ bottom out at purely behavioral architecture bodies

„ Final result of elaboration

„ flat collection of signal nets and processes

Dept. of E&C, NITKS August 2006

Elaboration Example
reg4(struct) bit0
d_latch
d0 q0
d q
clk

bit1
d_latch
d1 q1
d q
clk

bit2
d_latch
d2 q2
d q
clk

bit3
d_latch
d3 q3
d q

gate clk
and2
en int_clk
a y
clk
b

Dept. of E&C, NITKS August 2006

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 Elaboration Example
bit0
reg4(struct)
d_latch(basic)
d0 d q q0

clk

bit1
d_latch(basic)
d1 d q q1

clk

bit2
d_latch(basic)
d2 d q q2

clk

bit3
d_latch(basic)
d3 d q q3

gate clk
and2(basic)
en a y int_clk
clk b
process with variables
and statements

Dept. of E&C, NITKS August 2006

Simulation
„ Execution of the processes in the elaborated model
„ Discrete event simulation
„ time advances in discrete steps
„ when signal values change—events
„ A processes is sensitive to events on input signals
„ specified in wait statements
„ resumes and schedules new values on output signals
„ schedules transactions

„ event on a signal if new value different from old value

Dept. of E&C, NITKS August 2006

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 Simulation Algorithm
„ Initialization phase
„ each signal is given its initial value
„ simulation time set to 0
„ for each process
„ activate

„ execute until a wait statement, then suspend

„ execution usually involves scheduling transactions on

signals for later times

Dept. of E&C, NITKS August 2006

Simulation Algorithm
„ Simulation cycle
„ advance simulation time to time of next transaction
„ for each transaction at this time
„ update signal value

„ event if new value is different from old value

„ for each process sensitive to any of these events, or whose

“wait for …” time-out has expired
„ resume

„ execute until a wait statement, then suspend

„ Simulation finishes when there are no further

scheduled transactions
Dept. of E&C, NITKS August 2006

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 Synthesis
„ Translates register-transfer-level (RTL) design
into gate-level netlist
„ Restrictions on coding style for RTL model
„ Tool dependent

Dept. of E&C, NITKS August 2006

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