LMV1090

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LMV1090 Dual Input, Far Field Noise Suppression Microphone Amplifier

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1FEATURES DESCRIPTION
•
23 No Loss of Voice Intelligibility The LMV1090 is a fully analog dual differential input,
differential output, microphone array amplifier
• No Added Processing Delay designed to reduce background acoustic noise, while
• Low Power Consumption delivering superb speech clarity in voice
• Differential Outputs communication applications.
• Excellent RF Immunity The LMV1090 preserves near-field voice signals
• Adjustable 12 - 54dB Gain within 4cm of the microphones while rejecting far-field
acoustic noise greater than 50cm from the
• Shutdown Function microphones. Up to 20dB of far-field rejection is
• Space-Saving 16–Bump DSBGA Package possible in a properly configured and using ±0.5dB
matched microphones.
APPLICATIONS Part of the PowerWise ™ family of energy efficient
• Mobile Headset solutions, the LMV1090 consumes only 600μA of
• Mobile and Handheld Two-Way Radios supply current providing superior performance over
DSP solutions consuming greater than ten times the
• Bluetooth and Other Powered Headsets power.
• Hand-held Voice Microphones
The dual microphone inputs and the processed signal
• Cell Phones output are differential to provide excellent noise
immunity. The microphones are biased with an
KEY SPECIFICATIONS internal low-noise bias supply.
• Far Field Noise Suppression Electrical (FFNSE
at f = 1kHz): 34dB (typ)
• SNRIE 26dB (typ)
• Supply Current: 600μA (typ)
• Standby Current 0.1μA (typ)
• Signal-to-Noise Ratio (Voice band): 65dB (typ)
• Total Harmonic Distortion + Noise: 0.1% (typ)
• PSRR (217Hz): 99dB (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 is a trademark of ~ Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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System Diagram

Far-field noise, > 50 cm Up to 4 cm

Near-Field Voice
Tra LMV1090 Pure analog solution
ffic
N ois provides superior
e performance over DSP
solutions
Lo ud
Music

Analog
Noise
Crowd Noise Near-Field Voice
Cancelling
Block

ts
men
unce
Anno Far field noise reduced by up
to 20 dB in properly configured
o ise and using ±0.5 dB matched
eN Low-cost microphones
chin omnidirectional
Ma
microphones

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Typical Application

VDD
CB
C1 10 nF
1 PF
VDD
REF

Mic
Bias
Bias LPF+

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RIN3 RIN1
1.1 k: 1.1 k: * CLP1
CIN1 Post Amp
Gain
OUT+ Optimized
Mic2+
(6-18 dB) Audio
Pre-Amp
470 nF Gain Ouput
CIN2
Mic2- (6-36 dB)
LPF-
470 nF
CIN3
Mic1+
Pre-Amp * CLP2
470 nF Gain
CIN4 (6-36 dB) Post Amp
Mic1- OUT- Optimized
Gain
(6-18 dB) Audio
470 nF Ouput

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RIN4 RIN2
1.1 k: 1.1 k: 2
Shutdown I C Interface

GND C2
EN SDA SCL
100 nF
2
I CVDD

* The value of the low-pass filter capacitor is application dependent, see the application section for additional information.

Figure 1. Typical Dual Microphone Far Field noise Cancelling Application

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LMV1090

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Connection Diagram
1 2 3 4

A MIC1- MIC1+ MIC2- MIC2+

B GND LPF+ OUT+ REF

Mic
C VDD LPF- OUT-
Bias

2
D EN SDA SCL I CVDD

Figure 2. 16–Bump DSBGA (Top View)

See YZR0016 Package

PIN DESCRIPTIONS
Bump Number Pin Name Pin Function Pin Type
A1 MIC1– Microphone 1 negative input Analog Input
A2 MIC1+ Microphone 1 positive input Analog Input
A3 MIC2– Microphone 2 negative input Analog Input
A4 MIC2+ Microphone 2 positive input Analog Input
B1 GND Amplifier ground Ground
B2 LPF+ Low Pass Filter for positive output Analog Input
B3 OUT+ Positive optimized audio output Analog Output
B4 REF Reference voltage de-coupling Analog Reference
C1 VDD Power supply Supply
C2 LPF- Low Pass Filter for negative output Analog Input
C3 OUT- Negative optimized audio output Analog Output
C4 Mic Bias Microphone Bias Analog Output
D1 EN Chip enable Digital input
D2 SDA I2C data Digital Input/Output
D3 SCL I2C clock Digital Input
2 2
D4 I CVDD I C power supply Supply

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings (1) (2)

Supply Voltage 6.0V
Storage Temperature -85°C to +150°C
Power Dissipation (3) Internally Limited
ESD Rating (4) 2000V
(5)
ESD Rating 200V
CDM 500V
Junction Temperature (TJMAX) 150°C
Mounting Temperature Infrared or Convection (20 sec.) 235°C
Thermal Resistance θJA (DSBGA) 70°C/W
Soldering Information See AN-1112 “microSMD Wafers Level Chip Scale Package.”

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJC, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in the Absolute Maximum Ratings,
whichever is lower. For the LMV1090, TJMAX = 150°C and the typical θJA for this DSBGA package is 70°C/W. Refer to the Thermal
Considerations section for more information.
(4) Human body model, applicable std. JESD22-A114C.
(5) Machine model, applicable std. JESD22-A115-A.

Operating Ratings (1)

Supply Voltage 2.7V ≤ VDD ≤ 5.5V
2 (2)
I CVDD Supply Voltage 1.7V ≤ I2CVDD ≤ 5.5V
TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The voltage at I2CVDD must not exceed the voltage on VDD.

Electrical Characteristics 3.3V (1) (2)

Unless otherwise specified, all limits specified for TA = 25°C, VDD = 3.3V, VIN = 18mVP-P, f = 1kHz, EN = VDD, Pre Amp gain =
20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, f = 1kHz pass through mode.
LMV1090 Units
Symbol Parameter Conditions
Typical (3) Limit (4) (Limits)
VIN = 18mVP-P
63 dB
A-weighted, Audio band
SNR Signal-to-Noise Ratio
VOUT = 18VP-P,
65 dB
voice band (300–3400Hz)
eN Input Referred Noise level A-Weighted 5 μVRMS
VIN Maximum Input Signal THD+N < 1%, Pre Amp Gain = 6dB 880 820 mVP-P (min)

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
(3) Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured
(4) Datasheet min/max specification limits are ensured by test, or statistical analysis.
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Electrical Characteristics 3.3V(1)(2) (continued)

Unless otherwise specified, all limits specified for TA = 25°C, VDD = 3.3V, VIN = 18mVP-P, f = 1kHz, EN = VDD, Pre Amp gain =
20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, f = 1kHz pass through mode.
LMV1090 Units
Symbol Parameter Conditions
Typical (3) Limit (4) (Limits)
Differential Out+, Out-
Maximum AC Output Voltage 1.2 1.1 VRMS (min)
VOUT THD+N < 1%
DC Level at Outputs Out+, Out- 820 mV
THD+N Total Harmonic Distortion + Noise Differential Out+ and Out- 0.1 0.2 % (max)
ZIN Input Impedance 142 kΩ
ZOUT Output Impedance (Differential) 220 Ω
RLOAD 10 kΩ (min)
ZLOAD Load Impedance (Out+, Out-) (5)
CLOAD 100 pF (max)
minimum 6 dB
AM Microphone Preamplifier Gain Range
maximum 36 dB
Microphone Preamplifier Gain 1.7 dB (min)
AMR 2
Adjustment Resolution 2.3 dB (max)
minimum 6 dB
AP Post Amplifier Gain Range
maximum 18 dB
2.6 dB (min)
APR Post Amplifier Gain Resolution 3
3.4 dB (max)
f = 1kHz (See Test Methods) 34 26 dB
FFNSE Far Field Noise Suppression Electrical
f = 300Hz (See Test Methods) 42 dB
Signal-to-Noise Ratio Improvement f = 1kHz (See Test Methods) 26 18 dB
SNRIE
Electrical f = 300Hz (See Test Methods) 33 dB
Input Referred, Input AC grounded
PSRR Power Supply Rejection Ratio fRIPPLE = 217Hz (VRIPPLE = 100mVP-P) 99 85 dB (min)
fRIPPLE = 1kHz (VRIPPLE = 100mVP-P) 95 80 dB (min)
CMRR Common Mode Rejection Ratio input referred 60 dB
1.85 V (min)
VBM Microphone Bias Supply Voltage IBIAS = 1.2mA 2.0
2.15 V (max)
eVBM Mic bias noise voltage on VREF pin A-Weighted, CB = 10nF 7 μVRMS
IDDQ Supply Quiescent Current VIN = 0V 0.60 0.80 mA (max)
VIN = 25mVP-P both inputs
IDD Supply Current 0.60 mA
Noise cancelling mode
ISD Shut Down Current EN pin = GND 0.1 0.7 μA (max)
IDDI2C I2C supply current I2C Idle Mode 25 100 nA (max)
(6)
TON Turn-On Time 40 ms (max)
TOFF Turn-Off Time (6) 60 ms (max)

(5) Ensured by design.

(6) Ensured by design.

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Electrical Characteristics 5.0V (1) (2)

Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 5V, VIN = 18mVP-P, EN = VDD, Pre Amp gain = 20dB, Post
Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF, f = 1kHz pass through mode.
LMV1090 Units
Symbol Parameter Conditions
Typical (3) Limit (4) (Limits)
VIN = 18mVP-P
63 dB
A-weighted, Audio band
SNR Signal-to-Noise Ratio
VOUT = 18mVP-P,
65 dB
voice band (300–3400Hz)
eN Input Referred Noise level A-Weighted 5 μVRMS
VIN Maximum Input Signal THD+N < 1% 880 820 mVP-P (min)
f = 1kHz, THD+N < 1% VRMS (min)
Maximum AC Output Voltage 1.2 1.1
VOUT between differential output
DC Output Voltage 820 mV
THD+N Total Harmonic Distortion + Noise Differential Out+ and Out- 0.1 0.2 % (max)
ZIN Input Impedance 142 kΩ
ZOUT Output Impedance 220 Ω
minimum 6 dB
AM Microphone Preamplifier Gain Range
maximum 36 dB
Microphone Preamplifier Gain 1.7 dB (min)
AMR 2
Adjustment Resolution 2.3 dB (max)
minimum 6 dB
AP Post Amplifier Gain Range
maximum 18 dB
Post Amplifier Gain Adjustment 2.6 dB (min)
APR 3
Resolution 3.4 dB (max)
f = 1kHz (See Test Methods) 34 26 dB
FFNSE Far Field Noise Suppression Electrical
f = 300Hz (See Test Method) 42 dB
Signal-to-Noise Ratio Improvement f = 1kHz (See Test Methods) 26 18 dB
SNRIE
Electrical f = 300Hz (See Test Methods) 33 dB
Input Referred, Input AC grounded
PSRR Power Supply Rejection Ratio fRIPPLE = 217Hz (VRIPPLE = 100mVP-P) 99 85 dB (min)
fRIPPLE = 1kHz (VRIPPLE = 100mVP-P) 95 80 dB (min)
CMRR Common Mode Rejection Ratio input referred 60 dB
1.85 V ( min)
VBM Microphone Bias Supply Voltage IBIAS = 1.2mA 2.0
2.15 V (max)
Microphone bias noise voltage on VREF A-Weighted, CB = 10nF 7 μVRMS
eVBM
pin
IDDQ Supply Quiescent Current VIN = 0V 0.60 0.80 mA (max)
VIN = 25mVP-P both inputs
IDD Supply Current 0.60 mA
Noise cancelling mode
ISD Shut Down Current EN pin = GND 0.1 μA
2 2 2
IDDI C I C supply current I C Idle Mode 25 100 nA (max)
TON Turn On Time (5) 40 mA (max)
TOFF Turn Off Time (5) 60 ms (max)

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The voltage at I2CVDD must not exceed the voltage on VDD.
(3) Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured
(4) Datasheet min/max specification limits are ensured by test, or statistical analysis.
(5) Ensured by design.

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Digital Interface Characteristics I2C_VDD = 2.2V to 5.5V (1) (2)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2C_VDD ≤ 5.5V, unless otherwise specified.
LMV1090 Units
Symbol Parameter Conditions
Typical (3) Limits (4) (5) (Limits)
t1 I2C Clock Period 2.5 µs (min)
t2 I2C Data Setup Time 100 ns (min)
t3 I2C Data Stable Time 0 ns (min)
t4 Start Condition Time 100 ns (min)
t5 Stop Condition Time 100 ns (min)
t6 I2C Data Hold Time 100 ns (min)
2 2
VIH I C Input Voltage High EN, SCL, SDA 0.7xI CVDD V (min)
VIL I2C Input Voltage Low EN, SCL, SDA 0.3xI2CVDD V (max)

(1) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
(2) The voltage at I2CVDD must not exceed the voltage on VDD.
(3) Human body model, applicable std. JESD22-A114C.
(4) Machine model, applicable std. JESD22-A115-A.
(5) Datasheet min/max specification limits are ensured by test, or statistical analysis.

Digital Interface Characteristics I2C_VDD = 1.7V to 2.2V

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
LMV1090 Units
Symbol Parameter Conditions
Typical (1) Limits (2) (Limits)
t1 I2C Clock Period 2.5 µs (min)
t2 I2C Data Setup Time 250 ns (min)
t3 I2C Data Stable Time 0 ns (min)
t4 Start Condition Time 250 ns (min)
t5 Stop Condition Time 250 ns (min)
t6 I2C Data Hold Time 250 ns (min)
2 2
VIH I C Input Voltage High EN, SCL, SDA 0.7xI CVDD V (min)
VIL I2C Input Voltage Low EN, SCL, SDA 0.3xI2CVDD V (max)

(1) Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured
(2) Datasheet min/max specification limits are ensured by test, or statistical analysis.

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Test Methods

LMV1090

Mic2+
LPF
Osc2 470 nF OUT+
Mic2- AC Voltmeter

470 nF

Mic1+

Osc1 470 nF
Mic1-
OUT-
470 nF

Figure 3. FFNSE, NFSLE, SNRIE Test Circuit

FAR FIELD NOISE SUPPRESSION (FFNSE)

For optimum noise suppression the far field noise should be in a broadside array configuration from the two
microphones (see Figure 22). Which means the far field sound source is equidistance from the two microphones.
This configuration allows the amplitude of the far field signal to be equal at the two microphone inputs, however a
slight phase difference may still exist. To simulate a real world application a slight phase delay was added to the
FFNSE test. The block diagram from Figure 17 is used with the following procedure to measure the FFNSE.
1. A sine wave with equal frequency and amplitude (25mVP-P) is applied to Mic1 and Mic2. Using a signal
generator, the phase of Mic 2 is delayed by 1.1° when compared with Mic1.
2. Measure the output level in dBV (X)
3. Mute the signal from Mic2
4. Measure the output level in dBV (Y)
5. FFNSE = Y - X dB

NEAR FIELD SPEECH LOSS (NFSLE)

For optimum near field speech preservation, the sound source should be in an endfire array configuration from
the two microphones (see Figure 23). In this configuration the speech signal at the microphone closest to the
sound source will have greater amplitude than the microphone further away. Additionally the signal at
microphone further away will experience a phase lag when compared with the closer microphone. To simulate
this, phase delay as well as amplitude shift was added to the NFSLE test. The schematic from Figure 17 is used
with the following procedure to measure the NFSLE.
1. A 25mVP-P and 17.25mVP-P (0.69*25mVP-P) sine wave is applied to Mic1 and Mic2 respectively. Once again,
a signal generator is used to delay the phase of Mic2 by 15.9° when compared with Mic1.
2. Measure the output level in dBV (X)
3. Mute the signal from Mic2
4. Measure the output level in dBV (Y)
5. NFSLE = Y - X dB

SIGNAL TO NOISE RATIO IMPROVEMENT ELECTRICAL (SNRIE)

The SNRIE is the ratio of FFNSE to NFSLE and is defined as:
SNRIE = FFNSE - NFSLE (1)

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Typical Performance Characteristics

Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (Note 8), Pre Amp
gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
THD+N THD+N
vs vs
Frequency Frequency
Mic1 = AC GND, Mic2 = 36mVP-P Mic2 = AC GND, Mic1 = 36mVP-P
Noise Canceling Mode Noise Canceling Mode
10 10

1 1
THD+N (%)

THD+N (%)
0.1 0.1

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 4. Figure 5.

THD+N THD+N
vs vs
Frequency Frequency
Mic1 = 36mVP-P Mic2 = 36mVP-P
Mic1 Pass Through Mode Mic2 Pass Through Mode
10 10

1 1
THD+N (%)

THD+N (%)

0.1 0.1

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 6. Figure 7.

THD+N THD+N
vs vs
Input Voltage Input Voltage
Mic1 = AC GND, f = 1kHz Mic2 = AC GND, f = 1kHz
Mic2 Noise Canceling Mode Mic1 Noise Canceling Mode
100 100

10 10
THD+N (%)

THD+N (%)

1 1

0.1 0.1

0.01 0.01
0.001 0.01 0.1 1 0.001 0.01 0.1 1
INPUT VOLTAGE (VP-P) INPUT VOLTAGE (VP-P)

Figure 8. Figure 9.

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Typical Performance Characteristics (continued)

Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (Note 8), Pre Amp
gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
THD+N THD+N
vs vs
Input Voltage Input Voltage
f = 1kHz f = 1kHz
Mic1 Pass Through Mode Mic2 Pass Through Mode
100 100

10 10
THD+N (%)

THD+N (%)
1 1

0.1 0.1

0.01 0.01
0.001 0.01 0.1 1 0.001 0.01 0.1 1

INPUT VOLTAGE (VP-P) INPUT VOLTAGE (VP-P)

Figure 10. Figure 11.

PSRR PSRR
vs vs
Frequency Frequency
Pre Amp Gain = 20dB, Post Amp Gain = 6dB Pre Amp Gain = 20dB, Post Amp Gain = 6dB
VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND
Mic1 Pass Through Mode Mic2 Pass Through Mode
+0 +0
-10 -10
-20 -20
-30 -30
-40 -40
PSRR (dB)

PSRR (dB)

-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 12. Figure 13.

PSRR
vs
Frequency
Pre Amp Gain = 20dB, Post Amp Gain = 6dB Far Field Noise Suppression Electrical
VRIPPLE = 100mVP-P, Mic1 = Mic2 = AC GND vs
Noise Canceling Mode Frequency
+0 50
-10
-20 40
-30
-40
FFNSE (dB)
PSRR (dB)

30
-50
-60
20
-70
-80
10
-90
-100
-110 0
20 100 1k 10k 20k 100 1k 10k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 14. Figure 15.

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Typical Performance Characteristics (continued)

Unless otherwise specified, TJ = 25°C, VDD = 3.3V, Input Voltage = 18mVP-P, f =1 kHz, pass through mode (Note 8), Pre Amp
gain = 20dB, Post Amp gain = 6dB, RL = 100kΩ, and CL = 4.7pF.
Signal-to-Noise Ratio Electrical
vs
Frequency
35

30

25

SNRIE (dB)
20

15

10

0
100 1k 10k
FREQUENCY (Hz)

Figure 16.

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APPLICATION DATA

INTRODUCTION
The LMV1090 is a fully analog single chip solution to reduce the far field noise picked up by microphones in a
communication system. A simplified block diagram is provided in Figure 17.
Preamp Gain Post Amp Gain
(6 dB - 36 dB) (6 dB - 18 dB)

Mic1
OUT+
Analog Optimized
Noise Audio
Cancelling Ouput
Block OUT-
Mic2

Figure 17. Simplified Block Diagram of the LMV1090

The output signal of the microphones is amplified by a pre-amplifier with adjustable gain between 6dB and 36dB.
After the signals are matched the analog noise cancelling suppresses the far field noise signal. The output of the
analog noise cancelling processor is amplified in the post amplifier with adjustable gain between 6dB and 18dB.
For optimum noise and EMI immunity, the microphones have a differential connection to the LMV1090 and the
output of the LMV1090 is also differential. The adjustable gain functions can be controlled via I2C.

Power Supply Circuits

A low drop-out (LDO) voltage regulator in the LMV1090 allows the device to be independent of supply voltage
variations.
The Power On Reset (POR) circuitry in the LMV1090 requires the supply voltage to rise from 0V to VDD in less
than 100ms.
The Mic Bias output is provided as a low noise supply source for the electret microphones. The noise voltage on
the Mic Bias microphone supply output pin depends on the noise voltage on the internal the reference node. The
de-coupling capacitor on the VREF pin determines the noise voltage on this internal reference. This capacitor
should be larger than 1nF; having a larger capacitor value will result in a lower noise voltage on the Mic Bias
output.
Most of the logic levels for the digital control interface are relative to I2CVDD voltage. This eases interfacing to the
micro controller of the application containing the LMV1090. The supply voltage on the I2CVDD pin must never
exceed the voltage on the VDD pin.
Only the four pins that determine the default power up gain have logic levels relative to VDD.

Shutdown Function
As part of the Powerwise™ family, the LMV1090 consumes only 0.50mA of current. In many applications the part
does not need to be continuously operational. To further reduce the power consumption in the inactive period,
the LMV1090 provides two individual microphone power down functions. When either one of the shutdown
functions is activated the part will go into shutdown mode consuming only a few μA of supply current.

SHUTDOWN VIA HARDWARE PIN

The hardware shutdown function is operated via the EN pin. In normal operation the EN pin must be at a 'high'
level (VDD). Whenever a 'low' level (GND) is applied to the EN pin the part will go into shutdown mode disabling
all internal circuits.

Gain Balance and Gain Budget

In systems where input signals have a high dynamic range, critical noise levels or where the dynamic range of
the output voltage is also limited, careful gain balancing is essential for the best performance. Too low of a gain
setting in the preamplifier can result in higher noise levels while too high of a gain setting in the preamplifier will
result in clipping and saturation in the noise cancelling processor and output stages.
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The gain ranges and maximum signal levels for the different functional blocks are shown in Figure 18. Two
examples are given as a guideline on how to select proper gain settings.
Pre Amp Gain
Post Amp Gain
Gain (Max. 0 dB)
(6 dB - 18 dB)
(6 dB - 36 dB)

Analog OUT+
Mic1 Optimized
Noise
or Audio
Cancelling
Mic2 Ouput
Block OUT-

Maximum Maximum Maximum Maximum

AC Input AC Input AC Intput AC Output
Voltage Voltage Voltage Voltage
<440 mVpp <1.6 Vpp <1.6 Vpp <3.2 Vpp

Figure 18. Maximum Signal Levels

Example 1
An application using microphones with 50mVP-P maximum output voltage, and a baseband chip after the
LMV1091 with 1.5VP-P maximum input voltage.
For optimum noise performance, the gain of the input stage should be set to the maximum.
1. 50mVP-P +36 dB = 3.1VP-P.
2. 3.1VP-P is higher than the maximum 1.4VP-P allowed for the Noise Cancelling Block (NCB). This means a
gain lower than 29.5dB should be selected.
3. Select the nearest lower gain from the gain settings shown in Table 4, 28dB is selected. This will prevent the
NCP from being overloaded by the microphone. With this setting, the resulting output level of the Pre
Amplifier will be 1.26VP-P.
4. The NCB has a gain of 0dB which will result in 1.26VP-P at the output of the LMV1091. This level is less than
maximum level that is allowed at the input of the post amp of the LMV1091.
5. The baseband chip limits the maximum output voltage to 1.5VP-P with the minimum of 6dB post amp gain,
this results in requiring a lower level at the input of the post amp of 0.75VP-P. Now calculating this for a
maximum preamp gain, the output of the preamp must be no more than 0.75VP-P.
6. Calculating the new gain for the preamp will result in <23.5dB gain.
7. The nearest lower gain will be 22dB.
So using preamp gain = 22dB and postamp gain = 6dB is the optimum for this application.

Example 2
An application using microphones with 10mVP-P maximum output voltage, and a baseband chip after the
LMV1090 with 3.3VP-P maximum input voltage.
For optimum noise performance we would like to have the maximum gain at the input stage.
1. 10mVP-P + 36dB = 631mVP-P.
2. This is lower than the maximum 1.5VP-P so this is OK.
3. The NCB has a gain of 0dB which will result in 1.5VP-P at the output of the LMV1091. This level is lower than
maximum level that is allowed at the input of the Post Amp of the LMV1091.
4. With a Post Amp gain setting of 6dB the output of the Post Amp will be 3VP-P which is OK for the baseband.
5. The nearest lower Post Amp gain will be 6dB.
So using preamp gain = 36dB and postamp gain = 6dB is optimum for this application.

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I2C Compatible Interface

The LMV1090 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line are uni-directional. *The LMV1090 and the master can communicate at clock
rates up to 400kHz. Figure 19 shows the I2C Interface timing diagram. Data on the SDA line must be stable
during the HIGH period of SCL. The LMV1090 is a transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition
(Figure 20). The data line is 8 bits long and is always followed by an acknowledge pulse (Figure 21).

I2C Compatible Interface Power Supply Pin (I2CVDD)

The LMV1090 I2C interface is powered up through the I2CVDD pin. The LMV1090 I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C Interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.

I2C Bus Format

The I2C bus format is shown in Figure 21. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH is generated, alerting all devices on the bus that a device address is being written to the bus. The
7-bit device address is written to the bus, most significant bit (MSB) first followed by the R/W bit, R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LMV1090 is a WRITE-ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the mater device release SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LMV1090 receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK)
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LMV1090 sends another ACK bit. Following the
acknowledgement of the last register data word, the master issues a STOP bit, allowing SDA to go high while
SCL is high.

Figure 19. I2C Timing Diagram

*The data line is bi-directional (open drain)

SDA

SCL
S P
START condition STOP condition

Figure 20. I2C Start Stop Conditions

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SCL

SDA START MSB DEVICE ADDRESS LSB W ACK MSB REGISTER DATA LSB ACK STOP

Figure 21. Start and Stop Diagram

Table 1. Chip Address

B7 B6 B5 B4 B3 B2 B1 B0/W
Chip Address 1 1 0 0 1 1 1 0

Table 2. I2C Register Description

Address
Reg. Bits Description Default
B[7]
Gain setting for the pre amplifier from 6dB up to 36dB in 2dB steps
0000 6dB
0001 8dB
0010 10dB
0011 12dB
0100 14dB
0101 16dB
0110 18dB
0111 20dB
[3:0] 0000
1000 22dB
1001 24dB
1010 26dB
1011 28dB
0 A 1100 30dB
1101 32dB
1110 34dB
1111 36dB
Gain setting for the post amplifier from 6dB to 18dB in 3dB steps
000 6dB
001 9dB
010 12dB
011 15dB
[6:4] 100 18dB 000
101 18dB
110 18dB
111 18dB
111 18dB

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Table 2. I2C Register Description (continued)

Address
Reg. Bits Description Default
B[7]
B[0] = mute mic 1 and B[1] = mute mic 2
[1:0] 00
( 0 = microphone on)
Mic enable bits, B[3] = enable Mic 2, B[2] = enable Mic 1
[3:2] 00
(1 = enable), B3 and B2 both 0 = disable Mic 1 and Mic 2
Mic select bits
1 B 00 Noise cancelling mode
01 Only Mic 1 enabled (pass through)
[5:4] 00
10 Only Mic 2 enabled (pass through)
11 Mic 1 + Mic 2
[6] Not Used

Microphone Placement
Because the LMV1090 is a microphone array Far Field Noise Reduction solution, proper microphone placement
is critical for optimum performance. Two things need to be considered: The spacing between the two
microphones and the position of the two microphones relative to near field source
If the spacing between the two microphones is too small near field speech will be canceled along with the far
field noise. Conversely, if the spacing between the two microphones is large, the far field noise reduction
performance will be degraded. The optimum spacing between Mic 1 and Mic 2 is 1.5-2.5cm. This range provides
a balance of minimal near field speech loss and maximum far field noise reduction. The microphones should be
in line with the desired sound source 'near speech' and configured in an endfire array (see Figure 23) orientation
from the sound source. If the 'near speech' (desired sound source) is equidistant to the source like a broadside
array (see Figure 22) the result will be a great deal of near field speech loss.

NEAR OPTIMIZED
SPEECH LMV1090 SPEECH

WRONG

Figure 22. Broadside Array (WRONG)

OPTIMIZED
1.5~2.5 cm LMV1090 SPEECH

CORRECT
NEAR
SPEECH

Figure 23. Endfire Array (CORRECT)

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Low-Pass Filter At The Output

At the output of the LMV1090 there is a provision to create a 1st order low-pass filter (only enabled in 'Noise
Cancelling' mode). This low-pass filter can be used to compensate for the change in frequency response that
results from the noise cancellation process. The change in frequency response resembles a first-order high-pass
filter, and for many of the applications it can be compensated by a first-order low-pass filter with cutoff frequency
between 1.5kHz and 2.5kHz.
The transfer function of the low-pass filter is derived as:
Post Amplifier gain
H(s) =
sRfCf+1
(2)
This low-pass filter is created by connecting a capacitor between the LPF pin and the OUT pin of the LMV1090.
The value of this capacitor also depends on the selected output gain. For different gains the feedback resistance
in the low-pass filter network changes as shown in Table 3.
This will result in the following values for a cutoff frequency of 2000 Hz:

Table 3. Low-Pass Filter Capacitor For 2kHz

Post Amplifier Gain Setting (dB) Rf (kΩ) Cf (nF)
6 20 3.9
9 29 2.7
12 40 2.0
15 57 1.3
18 80 1.0

A-Weighted Filter
The human ear is sensitive for acoustic signals within a frequency range from about 20Hz to 20kHz. Within this
range the sensitivity of the human ear is not equal for each frequency. To approach the hearing response,
weighting filters are introduced. One of those filters is the A-weighted filter.
The A-weighted filter is used in signal to noise measurements, where the wanted audio signal is compared to
device noise and distortion.
The use of this filter improves the correlation of the measured values to the way these ratios are perceived by
the human ear.
10

-10

-20
dBV

-30

-40

-50

-60

-70
10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 24. A-Weighted Filter

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Measuring Noise and SNR

The overall noise of the LMV1090 is measured within the frequency band from 10Hz to 22kHz using an A-
weighted filter. The Mic+ and Mic- inputs of the LMV1090 are AC shorted between the input capacitors, see
Figure 25.

LMV1090

Mic2+
LPF
470 nF OUT+ A-WEIGHTED
short
Mic2- FILTER AC Voltmeter

470 nF

Mic1+

short 470 nF
Mic1-
OUT-
470 nF

Figure 25. Noise Measurement Setup

For the signal to noise ratio (SNR) the signal level at the output is measured with a 1kHz input signal of 18mVP-P
using an A-weighted filter. This voltage represents the output voltage of a typical electret condenser microphone
at a sound pressure level of 94dB SPL, which is the standard level for these measurements. The LMV1090 is
programmed for 26dB of total gain (20dB preamplifier and 6dB postamplifier) with only Mic1 or Mic2 used. (See
also I2C Compatible Interface).
The input signal is applied differentially between the Mic+ and Mic-. Because the part is in Pass Through mode
the low-pass filter at the output of the LMV1090 is disabled.

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Table 4. Revision History

Rev Date Description
1.0 07/01/09 Initial released.
1.01 07/10/09 Deleted the Limit values (on Zin) from both the 3.3V and 5V EC tables.
1.02 07/30/09 Edited the package dimensions (X1, X2, and X3).
1.03 09/02/09 Deleted the “Measurement Setup” paragraph.
1.04 10/12/09 Text edits.
1.05 10/15/09 Deleted the input limits on Zin (both from the 3.3V and 5.0V).
1.06 10/29/09 Text edits.
1.07 07/02/10 Edited curves 30083357 and 30083358.
I 05/02/13 Changed layout of National Data Sheet to TI format

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 PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

LMV1090TL/NOPB NRND DSBGA YZR 16 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 ZA3
& no Sb/Br)
LMV1090TLX/NOPB NRND DSBGA YZR 16 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 ZA3
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV1090TL/NOPB DSBGA YZR 16 250 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
LMV1090TLX/NOPB DSBGA YZR 16 3000 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV1090TL/NOPB DSBGA YZR 16 250 210.0 185.0 35.0
LMV1090TLX/NOPB DSBGA YZR 16 3000 210.0 185.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA
YZR0016xxx

D
0.600±0.075

TLA16XXX (Rev C)

D: Max = 1.991 mm, Min =1.931 mm

E: Max = 1.991 mm, Min =1.931 mm

4215051/A 12/12

NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.

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