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Waveform: Figure 3: Xor Gate Using Winspice

The document describes logic gates including XOR, XNOR, half adder, and full adder circuits. It includes waveform diagrams and schematic diagrams created using WinSpice and Electric design tools. Truth tables are provided for each logic gate. Karnaugh maps are shown for simplifying logic expressions of half and full adders. Netlists of the half adder and full adder circuits are also included.

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Fritz Fatiga
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84 views

Waveform: Figure 3: Xor Gate Using Winspice

The document describes logic gates including XOR, XNOR, half adder, and full adder circuits. It includes waveform diagrams and schematic diagrams created using WinSpice and Electric design tools. Truth tables are provided for each logic gate. Karnaugh maps are shown for simplifying logic expressions of half and full adders. Netlists of the half adder and full adder circuits are also included.

Uploaded by

Fritz Fatiga
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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WAVEFORM

Figure 3 : XOR Gate using WinSpice

Figure 4: XNOR Gate using WinSpice


SCHEMATIC DIAGRAM

Figure 1: XOR gate Schematic Diagram using Electric

Figure 2: XNOR Schematic Diagram using Electric


TRUTH TABLE

A B C A B C
1 1 0 1 1 1
0 1 1 0 1 0
1 0 1 1 0 0
0 0 0 0 0 1
TABLE 1: XOR Gate Truth TABLE 2: XNOR Gate Truth
Table with Inputs A and B Table with Inputs A and B

Figure 5: XOR Logic Gate Figure 6: XNOR Logic Gate


symbol symbol
WAVEFORM

Figure 3: Half Adder Waveform using WinSpice


Figure 4: FULL ADDER Waveform using WinSpice
SCHEMATIC DIAGRAM

Figure 1: Half Adder Schematic diagram using Electric

Figure 2: Full Adder Schematic Diagram using Electric


TRUTH TABLE
HALF ADDER

A B Carry Sum

1 1 0 0

0 1 0 1

1 0 0 1 Figure 5: Half Adder


Logic Gate Diagram
0 0 1 0
TABLE 1: Half Adder truth
table with 1-bit Binary
number AB and output
Carry and Sum

In complementary;

Carry = A B+A B Sum = AB

Carry =(A+ B )( A +B) Sum = A + B

Carry = A A +AB+ A B + B B

Carry = A B +AB
KARNAUGH MAP
Half Adder Full Adder
Carry Cout
B B C C
A 0 0
AB 0 0
A 0 1
AB 0 1
Sum AB 1 1
B B AB 0 1
A 0 1 Sum
A 1 1
C C
AB 0 1
AB 1 0
AB 0 1
AB 1 0
FULL ADDER
Cin A B Sum Cout
0 0 0 0 0
0 1 0 1 0
0 0 1 1 0
0 1 1 0 1
1 0 0 1 0
1 1 0 0 1
1 0 1 0 1
1 1 1 1 1
Table 2: Full Adder Truth Table with Inputs Cin, A, and B and
Outputs Sum and Cout

Figure 6: Full Adder Logic Gate Diagram

Where; Sum = ABC + A B C +A B C +ABC

Cout = AB + BC +AC
NETLIST
HALF ADDER

*** FACET HALFADDER FROM LIBRARY FATIGA ***


*** FACET CREATED Fri Aug 10 13:29:21 2018
*** VERSION 1 LAST REVISED Fri Aug 10 13:53:46 2018
*** EXTRACTED BY ELECTRIC DESIGN SYSTEM, VERSION 6.03
*** UC SPICE *** , MIN_RESIST 0.000000, MIN_CAPAC 0.000000FF
.OPTIONS NOMOD NOPAGE
*model = bsim3v3
*Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N NMOS
+Level= 8
+Tnom=27.0
+Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=9.36e-8 Wint=1.47e-7
+Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612
+Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2
+Nlx= 3.52291E-08 W0= 1.163e-6
+K3b= 2.233
+Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11
+Rdsw= 650 U0= 388.3203 wr=1
+A0= .3496967 Ags=.1 B0=0.546 B1= 1
+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
+Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9
+Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04
+Cdsc=-2.147181E-05
+Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0
+ Cdscd = 0 Prwg = 0
+Eta0= 1.0281729E-02 Etab=-5.042203E-03
+Dsub= .31871233
+Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03
+Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -
.234
+Pvag= 0 delta=0.01
+ Wl = 0 Ww = -1.420242E-09 Wwl = 0
+ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10
+ Lw = 0 Lwl = 0 Lln = .316394
+ Lwn = 0
+kt1=-.3 kt2=-.051
+At= 22400
+Ute=-1.48
+Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10
+Kt1l=0 Prt=764.3
.model P PMOS
+Level= 8
+Tnom=27.0
+Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=6.23e-8 Wint=1.22e-7
+Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82
+Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677
+Nlx= 1.28e-8 W0= 2.1e-6
+K3b= -0.24 Prwg=-0.001 Prwb=-0.323
+Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11
+ Rdsw= 460 U0= 138.7609
+A0= .4716551 Ags=0.12
+Keta=-1.871516E-03 A1= .3417965 A2= 0.83
+Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03
+Cdsc= 8.937517E-04
+Cdscb= 1.45e-4 Cdscd=1.04e-4
+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
+Eta0= 6.024776E-02 Etab=-4.64593E-03
+Dsub= .23222404
+Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3
+Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09
+Pvag= 0
+kt1= -0.25 kt2= -0.032 prt=64.5
+At= 33000
+Ute= -1.5
+Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0
+Kt1l=0
*** TOP LEVEL FACET: HALFADDER{lay}
** GROUND NET: 0 (net1)
** PORT Carry (network: Carry)
** PORT A (network: A)
** PORT B (network: B)
** PORT Sum (network: Sum)
MQ14 Carry net7 0 0 N L=0.70U W=1.60U
MQ13 net4 net7 Carry net4 P L=0.70U W=3.20U
Cnode1 0 Carry 1F
Cnode9 0 Sum 1F
MQ12 net5 A 0 0 N L=0.70U W=3.20U
MQ11 Sum B net5 0 N L=0.70U W=3.20U
MQ10 net6 net2 0 0 N L=0.70U W=3.20U
MQ9 Sum net3 net6 0 N L=0.70U W=3.20U
MQ4 net2 B 0 0 N L=0.70U W=1.60U
MQ3 net4 B net2 net4 P L=0.70U W=3.20U
MQ2 net3 A 0 0 N L=0.70U W=1.60U
MQ1 net4 A net3 net4 P L=0.70U W=3.20U
MQ8 net7 B Sum net4 P L=0.70U W=6.40U
MQ7 net4 net2 net7 net4 P L=0.70U W=6.40U
MQ6 net7 A Sum net4 P L=0.70U W=6.40U
MQ5 net4 net3 net7 net4 P L=0.70U W=6.40U
** Sources and special nodes:
Vnode10 net4 0 3.300000
Vnode11 B 0 pulse(0 3.3 0 1n 1n 100n 200n)
Vnode13 A 0 pulse(0 3.3 0 1n 1n 50n 100n)
.PRINT TRAN V(Carry) V(B) V(Sum) V(A)
.TRAN 1p 200n 1n 1n
.END
FULL ADDER
*** FACET FULL_ADDER_FINAL FROM LIBRARY FATIGA ***
*** FACET CREATED Sat Aug 11 10:40:52 2018
*** VERSION 1 LAST REVISED Sat Aug 11 11:29:59 2018
*** EXTRACTED BY ELECTRIC DESIGN SYSTEM, VERSION 6.03
*** UC SPICE *** , MIN_RESIST 0.000000, MIN_CAPAC 0.000000FF
.OPTIONS NOMOD NOPAGE
*model = bsim3v3
*Berkeley Spice Compatibility
* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20
.model N NMOS
+Level= 8
+Tnom=27.0
+Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=9.36e-8 Wint=1.47e-7
+Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612
+Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2
+Nlx= 3.52291E-08 W0= 1.163e-6
+K3b= 2.233
+Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11
+Rdsw= 650 U0= 388.3203 wr=1
+A0= .3496967 Ags=.1 B0=0.546 B1= 1
+ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213
+Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9
+Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04
+Cdsc=-2.147181E-05
+Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0
+ Cdscd = 0 Prwg = 0
+Eta0= 1.0281729E-02 Etab=-5.042203E-03
+Dsub= .31871233
+Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03
+Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -
.234
+Pvag= 0 delta=0.01
+ Wl = 0 Ww = -1.420242E-09 Wwl = 0
+ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10
+ Lw = 0 Lwl = 0 Lln = .316394
+ Lwn = 0
+kt1=-.3 kt2=-.051
+At= 22400
+Ute=-1.48
+Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10
+Kt1l=0 Prt=764.3
.model P PMOS
+Level= 8
+Tnom=27.0
+Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07
+Lint=6.23e-8 Wint=1.22e-7
+Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82
+Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677
+Nlx= 1.28e-8 W0= 2.1e-6
+K3b= -0.24 Prwg=-0.001 Prwb=-0.323
+Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11
+ Rdsw= 460 U0= 138.7609
+A0= .4716551 Ags=0.12
+Keta=-1.871516E-03 A1= .3417965 A2= 0.83
+Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03
+Cdsc= 8.937517E-04
+Cdscb= 1.45e-4 Cdscd=1.04e-4
+ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023
+Eta0= 6.024776E-02 Etab=-4.64593E-03
+Dsub= .23222404
+Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3
+Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09
+Pvag= 0
+kt1= -0.25 kt2= -0.032 prt=64.5
+At= 33000
+Ute= -1.5
+Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0
+Kt1l=0
*** TOP LEVEL FACET: FULL_ADDER_FINAL{lay}
** GROUND NET: 0 (net1)
** PORT A (network: A)
** PORT B (network: B)
** PORT Cin (network: Cin)
** PORT Cout (network: Cout)
** PORT Sum (network: Sum)
Cnode2 0 Sum 10F
Cnode4 0 Cout 10F
Mnode19 Cout net3 0 0 N L=0.70U W=1.60U
Mnode20 net6 net3 Cout net6 P L=0.70U W=3.20U
Mnode21 Sum net4 0 0 N L=0.70U W=1.60U
Mnode22 net7 B 0 0 N L=0.70U W=3.20U
Mnode23 net12 Cin 0 0 N L=0.70U W=4.80U
Mnode24 net11 B net12 0 N L=0.70U W=4.80U
Mnode25 net4 A net11 0 N L=0.70U W=4.80U
Mnode26 net8 B 0 0 N L=0.70U W=3.20U
Mnode27 net7 Cin 0 0 N L=0.70U W=3.20U
Mnode28 net7 A 0 0 N L=0.70U W=3.20U
Mnode29 net4 net3 net7 0 N L=0.70U W=3.20U
Mnode30 net8 A 0 0 N L=0.70U W=3.20U
Mnode31 net3 Cin net8 0 N L=0.70U W=3.20U
Mnode32 net9 A 0 0 N L=0.70U W=3.20U
Mnode33 net3 B net9 0 N L=0.70U W=3.20U
Mnode34 net6 net4 Sum net6 P L=0.70U W=3.20U
Mnode35 net14 Cin net4 net6 P L=0.70U W=8.40U
Mnode36 net15 B net14 net6 P L=0.70U W=8.40U
Mnode37 net6 A net15 net6 P L=0.70U W=8.40U
Mnode38 net5 net3 net4 net6 P L=0.70U W=6.40U
Mnode39 net6 Cin net5 net6 P L=0.70U W=6.40U
Mnode40 net6 B net5 net6 P L=0.70U W=6.40U
Mnode41 net6 A net5 net6 P L=0.70U W=6.40U
Mnode42 net6 B net10 net6 P L=0.70U W=6.40U
Mnode43 net10 Cin net3 net6 P L=0.70U W=6.40U
Mnode44 net6 A net10 net6 P L=0.70U W=6.40U
Mnode45 net13 B net3 net6 P L=0.70U W=6.40U
Mnode46 net6 A net13 net6 P L=0.70U W=6.40U
** Sources and special nodes:
Vnode7 net6 0 3.300000
Vnode11 Cin 0 pulse(0 3.3 0 1n 1n 200n 400n)
Vnode12 B 0 pulse(0 3.3 0 1n 1n 100n 200n)
Vnode13 A 0 pulse(0 3.3 0 1n 1n 50n 100n)
.PRINT TRAN V(Sum) V(Cout) V(Cin) V(B) V(A)
.TRAN 1p 400n 1n 1n
.END

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