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Behavioral Modeling: 1. Design A 4:1 MUX

The document provides examples of behavioral modeling in VHDL for common digital logic components including a 4:1 multiplexer, 2:4 decoder, 2-bit comparator, basic 2-bit ALU, and positive edge triggered JK flip flop. For each component, it shows both a behavioral model using case statements and a dataflow model using when/else statements to select outputs based on inputs. The behavioral modeling examples demonstrate using VHDL processes and case statements to model the logic functions of common digital circuits.

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Ishan Darwhekar
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Download as DOCX, PDF, TXT or read online on Scribd
73 views

Behavioral Modeling: 1. Design A 4:1 MUX

The document provides examples of behavioral modeling in VHDL for common digital logic components including a 4:1 multiplexer, 2:4 decoder, 2-bit comparator, basic 2-bit ALU, and positive edge triggered JK flip flop. For each component, it shows both a behavioral model using case statements and a dataflow model using when/else statements to select outputs based on inputs. The behavioral modeling examples demonstrate using VHDL processes and case statements to model the logic functions of common digital circuits.

Uploaded by

Ishan Darwhekar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Behavioral Modeling

1. Design a 4:1 MUX

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity Mux is
port(I3: in std_logic;
I2: in std_logic;
I1: in std_logic;
I0: in std_logic;
S: in std_logic_vector(1 downto 0);
O: out std_logic
);
end Mux;

--------------------Behavioral-----------------------------
architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin

-- use case statement


case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= ‘Z’;
end case;

end process;
end behv1;

---------------------Data Flow---------------------------
architecture behv of Mux is
begin

-- use when.. else statement


O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";

end behv;
2. Design 2:4 Decoder.

entity DECODER is
port(I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;

-------------------- Behavioral --------------------------

architecture behv of DECODER is


begin

-- process statement

process (I)
begin

-- use case statement

case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;

end process;

end behv;

----------------------Dataflow-------------------
architecture when_else of DECODER is
begin

-- use when..else statement

O <= "0001" when I = "00" else


"0010" when I = "01" else
"0100" when I = "10" else
"1000" when I = "11" else
"XXXX";

end when_else;

--------------------------------------------------
3. Design a 2-bit Comparator.

entity Comparator is

port( A: in std_logic_vector(1 downto 0);


B: in std_logic_vector(1 downto 0);
less: out std_logic;
equal: out std_logic;
greater: out std_logic
);
end Comparator;

---------------------------------------------------

architecture behv of Comparator is

begin

process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;

end behv;

---------------------------------------------------
4. Design a basic 2-bit ALU capable of adding, subtracting, anding and oring.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

---------------------------------------------------

entity ALU is

port( A: in std_logic_vector(1 downto 0);


B: in std_logic_vector(1 downto 0);
Sel: in std_logic_vector(1 downto 0);
Res: out std_logic_vector(1 downto 0)
);

end ALU;

---------------------------------------------------

architecture behv of ALU is


begin

process(A,B,Sel)
begin

-- use case statement to achieve


-- different operations of ALU

case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;

end process;

end behv;

----------------------------------------------------
5. Design a positive edge triggered JK flip flop.

library ieee;
use ieee.std_logic_1164.all;

----------------------------------------------

entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

-----------------------------------------------

architecture behv of JK_FF is

-- define the useful signals here

signal state: std_logic;


signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector


input <= J & K;

p: process(clock, reset) is
begin

if (reset='1') then
state <= '0';

elsif (clock’ event and clock=1) then

case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;

end process;

-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;

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