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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

Universal Digital Controller based on FPGA

Nanang Roni W, Dolly Indra, Rhiza S, Sadjad, Syafaruddin

Abstract
There are two approaches in the implementation of digital
controller, The first method, commonly used method is Sp(t) e(t) u(t)
software approach with utilize microprocessor/microcontroller (Controller) Actuator
device. The second method is hardware approach with CPLD +
and FPGA device, this approach has advantages in speed and - Plant
y(t)
parallel processing. sensor

Cyclone IVE EP4CE22F17C6 which is contained in DE0-

Nano module that integrated with ADC 12-bit utilized to Figure 1. Feedback Control System
implemented some of digital controller with data
representation of 10-bit fixedpoint 2’s Complements, as a
interface unit utilized switch and button as input device and Based on figure 1, the section will be constructed in this
LCD as the display or output device. study is control section using FPGA device, the rapid
development of this technology makes a lot of
Digital controller that created was on-off digital controller and companies to produce Chip FPGA, one of the company
PID, on-off controller obtained result of functional simulation is Altera.Corp, one of the chip product is Cyclone IVE
be able to operate as finite state machine and result of timing which complements DE0-Nano module that produced
simulation obtained maximum frequency of 723,07 MHz or by Terrasic from Taiwan [9]. FPGA is a device that
minimumun period of 1,38 ns in order to the whole process of works with discrete signal while control require analog
controller was finished.
signal to actuate and read the output so that need adding
Keywords: a device that is able to conversion analog signal into
FPGA, ADC, PID, On-Off Digital controller discrete signal (A/D Converter) ) [2][6][7]. In DE0-
Nano modules already contained serial ADC component
1. Introduction of 12-bit that is able to conversion with sampling
frequencies of 0.8–3.2 MHz [9].
Automatic control at first used to spacecraft control,
guided missiles, the aircraft rudder, over time has
Automatic control according to control action consist of
become an indispensable part of the process on modern
control of two positions, or "on-off", P control, PI
industrial [1]. Beginning with the use of mechanical and
control and PID control [1][2]. This study aimed to
hydraulic systems on control system and then it
make an automatic control with using a hardware
developments begin is used analog electronics
approach using chip FPGA which can be used to actuate
components after the invention of transistor [1]. The
the control, to test and validate the work of controller
development of digital technology, especially computer
that used in the temperature control system.
that able to finish calculating that complex make it
practical and common utilized into controller system
[2]. In the design of digital-based system, there are two 2. General Design of Control Systems
approaches or methods of design, In the design of Control system is a system that consists of two parts,
digital-based system, there are two approaches or namely: Plant and controller , the second part is
methods of design, software approach use connected by output signal, control signal, reference
microcontroller, digital signal processing (DSP) and signal and feedback signal if the system is built is a
hardware approach use FPGA [4]. feedback control system. Control system is built aims to
control a plant in order to give the desired output.
Today FPGA (Field Programmable Gate Array ) have
been one of alternative solution in control field the To get a control system that work automatically then
previously dominated by microprocessor technology type of controller that built is a feedback controller, that
[3], advantages offered is speed, capable of is controller which utilizes value of error signal from
implementing complex systems function and low power difference between reference signal with output signal
consumption [4]. Automatically control is one of system from plant is given to controller so it can reduce the
use the working principle of control with feedback or value of errors signal.
closed loop [1][5], work by comparing actual signal
from plant with reference signal, difference it then
performed manipulation process so that obtained
control signal used to actuate the control [1][4][6][7].
*) Mahasiswa Program Pasca Sarjana Teknik Elektro UNHAS, Stb. P2700210008
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

lcd is used to display value of reference signal, value of

Ref feedback signal from ADC as well as the digital
(SP) e(kT) Digital u(kT) u(t) Actua
DAC
controller parameter which is given to driver part.
+ Controller tor
- u(t) Table 1: User Interface Module and Controller
Digital Algorithm
y(kT)
Control
clock System
Group Module Explanation
debounced Reduce debounce effect on
Plant electromechanical devices
y(t) y(t) such as buttons, switch.
S/H dan Signal adc_ctrl Operating the device of
sensor
ADC Conditioners ADC128S022 to convert
analog signal to discrete
signal
lcd_ctrl Operating the device of lcd
16x2 to display information
Figure. 2 Diagram of Digital Control System to user
clock_div Lowering the clock
Digital control system is a control system that processes frequency of DE0-Nano
module according to system
the feedback signal and the control signal in the form requirement
of discrete signal, In figure 2, digital control system has transmitter_async Transmit data to PC serially
User Interface
an additional components of S/H and ADC that function using a RS232 protocol
to hold and convert the analog signal y(t) from sensor demux1_4 Decoder 1 to 4 to up and
down the counter module
that previous is adjusted to the specification of ADC mux2_4 Multiplexer 2 to 4 bits to
input become the digital signal. enable registers that would
be changed in its value.
The digital signal is obtained each time the component counter The value enumerators of
up/down to value of registers
of S/H to take analog signal in the time interval kT, the
module
digital signal later is compared with reference signal conf_fip Interpreting the data into a
(Ref(SP)) which produces the error signal (e(kT)), the fixed point format
signal is then used as input digital controller for register Memory of 1 x N-bits to
generating digital control signal (u(kT)) based on the store the value of reference
signal and parameter of
selected algorithm, next it is converted into analog digital controller
control signal (u(t)) using DAC component that will error_calc Value calculation of errors
actuate actuator part to change fissions signal from plant signal.
so that value of errors signal can be minimized. e(kT) = SP – y(kT)
Digital Control
ctrl_on_off On-off controller with
Algorithm
DIP
hysteresis
BUTTON LCD
SWITCH ctrl_pid PID controller with
incremental algorithm
GPIO_0 GPIO_0
GPIO_0
For FPGA interfacing with external device then need to
be made hardware module on the internal FPGA using
FPGA ALTERA hardware language, in this study used verilog. Module
GPIO_0
RS232 Cyclone IVE Driver design is performed with the top-down method, the
EP4C22F17C6 module consist of user interface module is a module to
DE0-NANO
MODULE

handle between a system with human and module of

digital controller algorithm used to run data
GPIO_2
PC
manipulation process to reduce value of errors signal, as
S/H dan PLANT in Table 1.
ADC

3. Design of Plant
To get the dynamic characteristic then need to designed
Figure 3. Digital Controller with DE0-Nano Module
a plant which later can be controlled using universal
digital controller for observed dynamic response and for
Digital controller is part of digital control system, in this
the controller validation process that designed to made
study digital controller is implemented with using
temperature control system, which have been made
hardware approach, namely using DE0-Nano module
previously [6][7].
which integrated components of S/H and ADC.
A plant is built using mica or acrylics material which
As in the picture 3, DE0-Nano module connected with
is shaped beam as in figure.4
button device is used to raising and lowering value of
reference signal (sp) as well as the parameter that
required selected controllers, dip switch is used to select
signal value and the parameter will be set, the working
mode and to select type of digital controller that desired,
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

On/off controller is the controller that works only in two

positions with refer to error signal e(k) which produce
Outside Air [ Tul ] actuation error (u(k)) in a condition that fixed at
minimum and maximum value, the general equation of
Box Mica [Tm ] this controller can be described as equation 1:

Inside Air [Tud ] 𝑢(𝑘) = 𝑆0 𝑓𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑒(𝑘) ≥ 0

𝑢(𝑘) = 𝑆1 𝑓𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑒(𝑘) < 0 (1)

Fan
Heater Sensor
Equation 1 is the ideal condition of an On/Off
controller, to reduce the process of changing condition
of on and off that fast then need additional parameters
such as hysteresis (h), thus obtained the equation 2:

Figure 4: Construction Temperature Control 𝑢(𝑘) = 𝑆0 𝑓𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑒(𝑘) > +ℎ𝑡𝑜𝑝
𝑢(𝑘) = 𝑆1 𝑓𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑒(𝑘) < −ℎ𝑑𝑜𝑤𝑛
Variable state of plant is Tud (air temperature in the 𝑢(𝑘) = 𝑓𝑖𝑥𝑒𝑑 𝑜𝑛 𝑆0 𝑜𝑟 𝑆1 (2)
box) and Tm ( the temperature of mica box), the hot 𝑓𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 |𝑒(𝑘)| < (ℎ𝑡𝑜𝑝 dan ℎ𝑑𝑜𝑤𝑛 )
input to system Q(t) is given by the heater in the form of
an incandescent light bulb and the outside air
temperature (Tul), it raises the heat transfer to the mica Based on the above equation can be made into
box as a material that isolate inside and outside
temperature, the plant which in figure 4, have two finite state machine as in figure 6.
actuators: the heating with incandescent lamp of
5W/12Vdc and cooling using fan of 12Vdc/0,12W
which will be governed by controller to keep in order to reset
the temperature inside the box according with reference 𝑒(𝑘) < ℎ𝑑𝑜𝑤𝑛
signal.

S0 S1
𝑇𝑒𝑚𝑝𝑒𝑟𝑎𝑡𝑢𝑟𝑒

|𝑒(𝑘)| 𝑒(𝑘) > ℎ𝑡𝑜𝑝 |𝑒(𝑘)|

ℎ𝑡𝑜𝑝
< ℎ𝑡𝑜𝑝 𝑎𝑛𝑑 ℎ𝑑𝑜𝑤𝑛 < ℎ𝑡𝑜𝑝 𝑑𝑎𝑛 ℎ𝑑𝑜𝑤𝑛
𝑇𝑎𝑐
ℎ𝑑𝑜𝑤𝑛
Figure 6. Finite State Machine Pengendali Digital on-off
𝑇𝑜
𝑡𝑖𝑚𝑒 𝑡

Finite State Machine dari pengendali on-off pada saat

terjadi reset menempatkan state pada state S0 dimana
Figure 5: Changes in the temperature inside mica box pada state ini mempunyai dua kondisi sebagaimana
persamaan 3.
The initial condition of the system works at room
temperature conditions To, the controller reads 𝐻𝑒𝑎𝑡𝑒𝑟 𝑡𝑢𝑟𝑛 𝑜𝑛 = 1
reference signal input Tac and compare with air 𝑆0 = {
𝐹𝑎𝑛 𝑡𝑢𝑟𝑛 𝑜𝑓𝑓 = 0 (3)
temperature in the box Tud, the difference between both
the signal is a error signal e(t) which is made digital
controller to perform control the action. If the value of then be tested to value of |e(k)| < htop and hdown, then
error signal is positive indicates Tud < Tac, so digital the does not change and if value of e(k) smaller than
controller activates the heater to give increase in heat by hdown then the state will move to State S1 which has
ΔTp. Digital controller monitoring is value of error conditions as in equation 4.
signal if the value e(t) < htop, this condition indicates
Tud = Tac+htop. Then digital controller will be turn off 𝐻𝑒𝑎𝑡𝑒𝑟 𝑡𝑢𝑟𝑛 𝑜𝑛 = 0
the heater and will activate the cooling to throw hot air 𝑆1 = { (4)
𝐹𝑎𝑛 𝑡𝑢𝑟𝑛 𝑜𝑓𝑓 = 1
so that cause decrease in value by ΔTd until the
conditions indicates value of Tud = Tac - hdown or
show the value of e(t) > hdown that is air temperature in
the box Tud > Tac which make digital controller will be And performed testing if value of |e(k)| < htop
turn off the cooling and will activate the heater, work and hdown, then the state does not change, if
principle of plant which is expected as in Figure 5. value of e(k) > htop, then the state will move to
State S0.
4. Controller Design of Digital On/Off
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

5. The Design of Digital PID Controller with the value of u(k) will be latched by Reg3 so
PID controller is a controller that perform the
become u(k-1). The diagram in the figure 7 is a
calculation process with 3 parameters, namely diagram of parallel design which further
proportional, integral and derivative, to implement PID implemented into FPGA chip. Digital PID controller
controller there are 3 algorithms that can be with incremental Algorithm is able to avoid to
implemented, namely velocity Algorithm, positional occur signal accumulation e(k) as well as can
algorithm and incremental algorithm [8] [10] [11]. In switch from manual mode to automatic mode
this study used an incremental algorithm with the
algorithm as in equation 5.
operation is more subtle [11].
6. Universal Digital Controller
𝑢(𝑘) = 𝑢(𝑘 − 1) + 𝐾0 𝑒(𝑘) + 𝐾1 𝑒(𝑘 − 1)
(5) Implementation
+ 𝐾2 (𝑘 − 2)
Implementation of digital controller of the design
with the constant value of K0, K1, K2 is PID
result need other component to complete so can
controller parameters value of incremental
be operated in real, the overall design of the
algorithm that obtained from equation of
system that made reference to the figure 3.
positional Algorithm with relationship in equation
module is used DE0-Nano from Terrasic which
6
includes are already equipped a Cyclone FPGA
𝐾0 = 𝑘𝑝 + 𝑘𝑖 + 𝑘𝑑 chip of EP4C22F17C6 and 12-bit ADC component
𝐾1 = −𝑘𝑝 − 2𝑘𝑑 (6) of ADC128S022, 2 pushbuttons and 4 DIP switchs,
to equip it is added hardware that function as
𝐾2 = 𝑘𝑑 user interface, namely : LCD 16X2, DIP switch,
kp, ki, kd are constants value of positional additional push button and RS-232 converter
Algorithm for proportional ,integral and using MAX232, Other components are heater and
derivative parameters. Based on equation 5 and 6 cooling driver. To operate the device then need to
then architecture of PID controller as in figure 7. be made interface module that implemented into
a FPGA so in it architecture form of universal
digital controller system is able to accommodate
e(k) e(k-1) e(k-2) controller of digital on-off and digital PID
Reg2
Reg1

controller. The overall system architecture of the

controller can be seen in figure 8. Part of user
K1 K2 interface that is formed is debouncer part to clean
influence debounce from mechanical operation of
u(k)
push button component, 2 decoder modules that
work to up and down the value of counter module
K0 which resulted in changing the value of register
u(k-1)
Reg3

clock with depend on pin select (A/B) on the

multiplexer module as in table 2.

Table 2: The Switch function to select counter and

controller
Figure 7: PID controller architecture using Select (A/B) Counter Register active
incremental algorithm 00 Counter _SP Reg SP
01 Counter_C0 Reg of constant 0
Figure 7. PID controller architecture using 10 Counter_C1 Reg of constant 1
incremental algorithm, error signal e(k) is 11 Counter_C2 Reg of constant 2
obtained from difference between reference
signal and feedback signal, all components There is other multiplexer module that has function as
pin to select type of controller will be used depend on
working by using clock signal that arrange pin of select_ctrl as an input multiplexer 2-4 so there are
sampling frequency from the digital PID 4 controllers can be used to active pin-enable on the
controller. At every change of clock signal cause controllers desired.
the value of signal e(k) will be latched by Reg1 so Implementation of on-off controller is done using
that at this cycles the value of e(k) will be stored program of Quartus II Student Edition is a program that
become the value of e(k-1) and the next cycle is issued to accommodate the uses of Chip from Altera,
this program is integrated with the application to
again the value of e(k) will be latched by Reg2 so perform the simulation, there are two simulation that
that will be obtained the value of e(k-2) likewise
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

can be done, namely functional simulation and timing controller is built one clock signal to ensure that
simulation [12][13]. physic time limit can be fulfilled that mean next
clock cycle is done if the entire gate had
Figure 9. Shows Functional testing method
completed its function and digital controller is at
againts DUT (Device Under Test) device, in the
steady state conditions [3] [11].
study is on-off digital controller and PID.
Functional testing is done by to build testbench
component that gives signal to DUT that further

Register
DUT

Wire
responce of DUT is read a net variable in the form
of wire.

Timing simulation is a simulation that is done to Tesbench

know performance of register with using
application timing analyzer is provided by
program of Quartus II Student Edition, namely
maximum frequency that can be used in digital Figure 9: Simulation functional testing method
controller device [3]. As is know that digital

Gambar 8. Diagram RTL Viewer sistem keseluruhan pengendali digital universal dengan pengendali on-off

6.1. Implementation of digital on-off Clk signal is signal for synchronization operations of
controller all components, rst (reset) signal is used to put back
On-off controller had been made before implementation digital on-off controller to state0. Err is error signal,
into FPGA then need to performed simulation while bts_up and bts_down are value of histeresys that
functional testing to get information, whether digital desired.
controller operates with desired logic and timing By providing as in Table 3 and Table 4 then response
simulation to get maximum clock frequency results obtained from digital on-off controller for error
information that can be given to digital controller. signal conditions and reset signal which is performed
changing conditions.
Timing Simulation is done by using TimeQuest timing
analyzer that provided by Quartus II from results Table 3: Stimulus and on-off Digital Controller
simulation obtained the maximum frequency of Response for the conditions of error value changed
Rst Err Bts_up Bts_bwh State (heater/fan)
723.07MHz (1,38 ns period), next step is done 0 6 1 -1 S0 1/0
simulation function with make hardware testbench that 1 6 1 -1 S0 1/0
to give stimulus to digital on-off controller in form clk, 1 5 1 -1 S0 1/0
rst, err, bts_up and bts_down signal. 1 4 1 -1 S0 1/0
1 3 1 -1 S0 1/0
1 2 1 -1 S0 1/0
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

1 1 1 -1 S0 1/0
1 0 1 -1 S0 1/0 Function simulation in figure 10 was done the
1 -1 1 -1 S1 0/1
1 -2 1 -1 S1 0/1
conditions of to rst signal = 0 given on controlling
1 -1 1 -1 S1 0/1 conditions was operating. At the beginning of the rst
1 0 1 -1 S1 0/1 conditions = 0 and err = 6 that give controller output
1 1 1 -1 S0 1/0 response ie heater = 1 and fan = 0 or controller
1 2 1 -1 S0 1/0 conditions lies on state 0 so occur operation of the
1 1 1 -1 S0 1/0
heating to plant, while still being in the state 0 then
1 0 1 -1 S0 1/0
occur rst signal = 0 then the controller toward the state
0 because of plant condition shows signal condition of
By using SIM model of Altera 6.6 obtained functional
bts_down ≤ e(k) ≤ bts_up then the state still remains in
testing results shown in figure 9.
state 0.
How in case of rst conditions = 0 with the controller
Function simulation in figure 9, for error signal
lies on state 1, the conditions based on Tabel 3 that the
conditions was changed resembles the actual plant
state will move from state 1 to state 0 during rst signal
response. Showed the initial condition stimulus signal
= 0, if rst signal = 1 and signal condition of bts_down ≤
namely : err = 0, bts_up = 1 dan bts_down = -1 then
e(k) ≤ bts_up still fulfilled then the controller will return
digital on-off controller gives the response to heater
to the state 1.
output = 1 or ON and fan = 0 or OFF, this conditions
already fulfil finite state machine like the design in
Table 4: Stimulus and on-off digital controller response
figure 6, where after occur reset then the controller
to the conditions performing a reset
toward the state 0. The next step rst signal given value Rst Err Bts_up Bts_bwh State (heater/fan)
equal 1 cause the controller starts working by 0 6 1 -1 S0 1/0
comparing the value of error signal e(k) with bts_up 1 6 1 -1 S0 1/0
and bts_down. From table 2 known that the state 0 5 1 -1 S0 1/0
change when err value = -1 from state 0 to state 1 with 1 4 1 -1 S0 1/0
1 3 1 -1 S0 1/0
the condition of the heater = 0 or OFF and condition
1 2 1 -1 S0 1/0
of fan = 1 or ON in accordance with the design in 1 1 1 -1 S0 1/0
figure 6, ie be at state 1 where err < bts_down 1 0 1 -1 S0 1/0
changing state also occur when err > bts_up ie from 1 -1 1 -1 S1 0/1
state 1 to state 0. The state will not change when signal 0 -2 1 -1 S0 1/0
value of bts_down ≤ e(k) ≤ bts_up accordance with the 1 -1 1 -1 S1 0/1
1 0 1 -1 S1 0/1
conditions of previous state. 1 1 1 -1 S0 1/0
1 2 1 -1 S0 1/0
Functional simulation further is done to know whether 1 1 1 -1 S0 1/0
the function of rst signal can restore the controller of 1 0 1 -1 S0 1/0
digital on-off so can operate as planned in figure 6 ie
each occur rst = 0 then the state back to the state 0.
Testing is done by providing rst signal = 0. By The results of simulation function testing and timing
providing stimulus signal as in Table 4, ie gives rst simulation obtained that the controller working as
signal = 0 when the controller was operating. design of finite state machine in figure 6.

Figure 9: Results of Functional Testing to on-off digital controller conditions that it changed value of errors
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Seminar Teknik Komputer, Kendali dan Elektronika Juni 2014

Figure 10: Results of Testing from digital on-off controller by the changing value of reset
7. CONCLUSION [5] Kuo, Benjamin C, Teknik kontrol automatic jilid I
Universal digital controller can be implemented using (Jakarta: Prenhallindo, 1998).
hardware such as FPGA Altera Cyclone IVE with type [6] Suryadi, “Perancangan dan implementasi modul
of EP4CE22F17C6N that contained in DE0-Nano kontrol temperature berbasis mikrokontroler
module that it is made by Terrasic.corp with ADC PIC16F877”, Skripsi Sarjana Fisika, ITB, 2005.
addition device while to user interface using push [7] Suryadi, Suryadi, dan Khairurijal, “ Implementasi
button and switch as input and LCD 16x2 as display. modul kontrol temperatur menggunakan digital PI
From the results of the study have been built interface controller”, Prosiding seminar Nasional Teknologi dan
user system that is used by us to do parameters Rekayasa Industri SNTRI 07 (Serpong, 11-12 April
configuration and type of desired controller, interface 2007), pp.TI-17-1-TI-17-4,2007.
user system is capable of producing 4 constants of [8] Astrom. K, Hagglund. T, PID controllers: theory
controller and 4 types of controllers. The results of design and tuning (Research Triangle Park, NC:
testing for functional and timing simulation obtained of Instrument Society, 1995).
digital on-off controller, ie the results of functional [9] Terrasic, DE0-Nano user manual (Taiwan, Terrasic
simulation had been worked as expected in the design Technologies.inc, 2003).
while the results of timing obtained maximum [10] Ogata, Katsuhiko, Discrete time control signal
frequency of 723,07 MHz that can be used by on-off second edition (Englewood Cliffs, NJ: Prentice Hall,
digital controller so it has a minimum operating period 1995).
of 1,38ns. [11] Khan, Hammad, PID Controller: Comparative
10. REFERENCES Analysis and Design of Diverse Realizations
[1] Ogata, Katsuhiko, Teknik kontrol automatic jilid I (Saarbrucken, Germany: LAP LAMBERT Academic,
edisi kedua(Jakarta: Erlangga, 1996). 2012).
[2] Basri, Muh, Pengendali Digital Universal, Teknik [12] Brown. Stephen, Vranesic. Zvonko, Fundamentals
Elektro Universitas Hasanuddin, Makassar, 2011. of Digital Logic with Verilog Design (Avenue of
[3] Triyanto, Dedy. Perancangan Pengendali PID Americas, NY: McGraw-Hills, 2003).
Digital dan Implementasinya Menggunakan FPGA, [13] Chu. Pong P, FPGA Prototyping by Verilog
Sekolah Teknik Elektro dan Informatika ITB, Bandung, Examples (Hoboken, NJ: John Wiley and Sons, 2008).
2008.
[4] Abdelati, Mohamed, FPGA-Based PID Controller
Implementation, The Islamic University of Gaza, Gaza.