Compression and Data Hiding System Based On SMVQ
Compression and Data Hiding System Based On SMVQ
PROF MANTRI D. B.
Department of Electronics and Telecommunication,V.V.P Institute of Engg & Technology, Solapur
University, Solapur, Ms, India. [email protected]
20 | P a g e
NOVATEUR PUBLICATIONS
International Journal of Research Publications in Engineering and Technology [IJRPET]
ISSN: 2454-7875
VOLUME 3, ISSUE 4, April-2017
Algorithm of compression and secret data embedding 4. After decomposing the image to hide the data into
Step1: Read input image image by entering the password
Step2: Take luminance component of the image
Step3: Split the image into 4x4 blocks
Step4: Top most row and left most column compressed
by VQ and embedding 0
Step5: For all residual blocks calculate E r (Mean Square
Error) and set threshold
Step6: If Er > T then block is compressed by VQ
Step7: If Er ≤ T embedded secret bit is 0 then block is
compressed by SMVQ and if embedded secret bit is 1
block is compressed by image inpainting
Step8: Stego image
III.EXPERIMENTAL RESULT:
1. First read the input image IV.CONCLUSION:
A joint data-hiding and compression (JDHC) concept can
integrate the two functions of data hiding and image
compression into a single module, which can avoid the
risk of attack from interceptors and increase the
implementation efficiency, recovery quality.
REFERENCES:
1) Xinmiao Zhang, Student Member, IEEE, and Keshab
K. Parhi, Fellow, IEEE “High-Speed VLSI Architectures
for the AES Algorithm” IEEE TRANSACTIONS, VOL.
12, NO. 9, SEPTEMBER 2004.
2. Split image into 4x4 block 2) Tim Good, Student Member, IEEE, and Mohammed
Benaissa, “Very Small FPGA Application-Specific
Instruction Processor for AES” IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS, VOL. 53, NO. 7, JULY
2006.
3) Ashwini M. Deshpande, Mangesh S. Deshpande and
Devendra N. Kayatanavar,“FPGA Implementation of
AES Encryption and Decryption” International
Conference on Control, Automation, Communication
and Energy Conservation-2009, 4th-6th June 2009.
4) Chen-Hsing Wang, Chieh-Lin Chuang, and Cheng-
Wen Wu “An Efficient Multimode Multiplier
3. Perform SMVQ and decompose the image Supporting AES and Fundamental Operations of
Public-Key Cryptosystems” IEEE TRANSACTIONS,
VOL. 18 NO. 4, April 2010.
5) Issam Hammad, Student Member, IEEE, Kamal
Sankary, Member “High-Speed AES Encryptor with
Efficient Merging Techniques” IEEE EMBEDDED
SYSTEMS LETTERS VOL. 2, NO. 3, SEPTEMBER 2010.
21 | P a g e