19-0584; Rev 2; 3/10

Low-Voltage DDR Linear Regulator

General Description Features

MAX8794
The MAX8794 DDR linear regulator sources and sinks up o Internal Power MOSFETs with Current Limit (3A typ)
to 3A peak (typ) using internal n-channel MOSFETs. This
linear regulator delivers an accurate 0.5V to 1.5V output o Fast Load-Transient Response
from a low-voltage power input (VIN = 1.1V to 3.6V). The o External Reference Input with Reference
MAX8794 uses a separate 3.3V bias supply to power the Output Buffer
control circuitry and drive the internal n-channel MOSFETs. o 1.1V to 3.6V Power Input
The MAX8794 provides current and thermal limits to pre- o ±15mV (max) Load-Regulation Error
vent damage to the linear regulator. Additionally, the
MAX8794 generates a power-good (PGOOD) signal to o Thermal-Fault Protection
indicate that the output is in regulation. During startup, o Shutdown Input
PGOOD remains low until the output is in regulation for 2ms o Power-Good Window Comparator with 2ms (typ)
(typ). The internal soft-start limits the input surge current. Delay
The MAX8794 powers the active-DDR termination bus o Small, Low-Profile, 10-Pin, 3mm x 3mm TDFN
that requires a tracking input reference. The MAX8794 Package
can also be used in low-power chipsets and graphics
processor cores that require dynamically adjustable o Ceramic or Polymer Output Capacitors
output voltages. The MAX8794 is available in a 10-pin,
3mm x 3mm, TDFN package. Ordering Information
PIN- TOP
Applications PART TEMP RANGE
PACKAGE MARK
Notebook/Desktop Computers 10 TDFN-EP*
MAX8794ETB+ -40°C to +85°C ASW
DDR Memory Termination (3mm x 3mm)
Active Termination Buses 10 TDFN-EP*
MAX8794ETB/V+ -40°C to +85°C ASW
Graphics Processor Core Supplies (3mm x 3mm)

Chipset/RAM Supplies as Low as 0.5V +Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.
*EP = Exposed pad.

Pin Configuration Typical Operating Circuit

VIN
(1.1V TO 3.6V) VOUT = VTT
IN OUT
TOP VIEW
OUTS
+
REFOUT 1 10 IN
VBIAS MAX8794
VCC 2 9 OUT (2.7V TO 3.6V)
3 8 PGND VCC PGND
AGND
MAX8794
REFIN 4 7 SHDN SHDN AGND

PGOOD 5 EP* 6 OUTS

PGOOD
VDDQ
TDFN (2.5V OR 1.8V) VREFOUT = VTTR
3mm x 3mm REFIN REFOUT

*EXPOSED PAD.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 Low-Voltage DDR Linear Regulator

ABSOLUTE MAXIMUM RATINGS

MAX8794

IN to PGND............................................................-0.3V to +4.3V Continuous Power Dissipation (TA = +70°C)

OUT to PGND ..............................................-0.3V to (VIN + 0.3V) 10-Pin 3mm x 3mm TDFN
OUTS to AGND ............................................-0.3V to (VIN + 0.3V) (derated 24.4mW/°C above +70°C)...........................1951mW
VCC to AGND.........................................................-0.3V to +4.3V Operating Temperature Range
REFIN, REFOUT, SHDN, PGOOD to AGND...-0.3V to (VCC + 0.3V) MAX8794ETB...................................................-40°C to +85°C
PGND to AGND .....................................................-0.3V to +0.3V Junction Temperature ......................................................+150°C
REFOUT Short Circuit to AGND .................................Continuous Storage Temperature Range .............................-65°C to +150°C
OUT Continuous RMS Current Lead Temperature (soldering, 10s) .................................+300°C
100s ................................................................................±1.6A Soldering Temperature (reflow) .......................................+260°C
1s ....................................................................................±2.5A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIN Power input 1.1 3.6
Input Voltage Range V
VCC Bias supply 2.7 3.6
Quiescent Supply Current (VCC) ICC Load = 0, VREFIN > 0.45V 0.7 1.3 mA
SHDN = AGND, VREFIN > 0.45V 350 600
Shutdown Supply Current (VCC) ICC(SHDN) µA
SHDN = AGND, REFIN = AGND 50 100
Quiescent Supply Current (VIN) IIN Load = 0 0.4 10 mA
Shutdown Supply Current (VIN) IIN(SHDN) SHDN = AGND 0.1 10 µA
REFIN to OUTS, TA = +25°C -4 0 +4
Feedback-Voltage Error VOUTS mV
IOUT = ±200mA TA = -40°C to +85°C -6 +6
Load-Regulation Error -1A ≤ IOUT ≤ +1A -15 +15 mV
Line-Regulation Error 1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA 1 mV
OUTS Input Bias Current IOUTS -1 +1 µA
OUTPUT
Output Adjust Range 0.5 1.5 V
High-side MOSFET (source) (IOUT = 0.1A) 0.10 0.169
OUT On-Resistance Ω
Low-side MOSFET (sink) (IOUT = -0.1A) 0.10 0.20
Output Current Slew Rate COUT = 100µF, IOUT = 0.1A to 2A 3 A/µs
OUT Power-Supply Rejection 10Hz < f < 10kHz, IOUT = 200mA,
PSRR 80 dB
Ratio COUT = 100µF
OUT to OUTS Resistance ROUTS 12 kΩ
Discharge MOSFET On-
RDISCHARGE SHDN = AGND 8 Ω
Resistance

2 _______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

ELECTRICAL CHARACTERISTICS (continued)

MAX8794
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE
REFIN Voltage Range VREFIN 0.5 1.5 V
REFIN Input Bias Current IREFIN -1 +1 µA
REFIN Undervoltage-Lockout
Rising edge, hysteresis = 75mV 0.35 0.45 V
Voltage
VREFIN VREFIN
REFOUT Voltage VREFOUT VCC = 3.3V, IREFOUT = 0 VREFIN V
- 0.01 + 0.01
REFOUT Load Regulation ΔVREFOUT IREFOUT = ±5mA -20 +20 mV
FAULT DETECTION
Thermal-Shutdown Threshold TSHDN Rising edge, hysteresis = 15°C +165 °C
VCC Undervoltage-Lockout
VUVLO Rising edge, hysteresis = 100mV 2.45 2.55 2.65 V
Threshold
IN Undervoltage-Lockout
Rising edge, hysteresis = 55mV 0.9 1.1 V
Threshold
Current-Limit Threshold ILIMIT 1.8 3 4.2 A
Soft-Start Current-Limit Time tSS 200 µs
INPUTS AND OUTPUTS
With respect to feedback threshold,
PGOOD Lower Trip Threshold -200 -150 -100 mV
hysteresis = 12mV
With respect to feedback threshold,
PGOOD Upper Trip Threshold 100 150 200 mV
hysteresis = 12mV
OUTS forced 25mV beyond PGOOD trip
PGOOD Propagation Delay tPGOOD 5 10 35 µs
threshold
Startup rising edge, OUTS within ±100mV of
PGOOD Startup Delay 2 3.5 ms
the feedback threshold
PGOOD Output Low Voltage ISINK = 4mA 0.3 V
OUTS = REFIN (PGOOD high impedance),
PGOOD Leakage Current IPGOOD 1 µA
PGOOD = VCC + 0.3V
Logic high 2.0
SHDN Logic Input Threshold V
Logic low 0.8
SHDN Logic Input Current SHDN = VCC or AGND -1 +1 µA
Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical-quality-control (SQC) methods.

_______________________________________________________________________________________ 3
 Low-Voltage DDR Linear Regulator

Typical Operating Characteristics

MAX8794

(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)

MAXIMUM OUTPUT CURRENT

OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION vs. INPUT VOLTAGE
0.96 1.30 3.0

MAX8794 toc02
MAX8794 toc01

MAX8794 toc03
VREFIN = 0.9V VREFIN = 1.25V
VOUT = 0.9V
VOUT = 1.25V
0.94 2.5

MAXIMUM OUTPUT CURRENT (A)

1.28

0.92 VIN = 1.5V 2.0

VIN = 1.25V 1.26
VOUT (V)
VOUT (V)

0.90 1.5
1.24 THERMALLY LIMITED
0.88 1.0
VIN = 1.8V
VIN = 1.5V 1.22 DROPOUT VOLTAGE LIMITED
0.86 0.5

0.84 1.20 0
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3 1.0 1.5 2.0 2.5 3.0
IOUT (A) IOUT (A) INPUT VOLTAGE (V)

INPUT CURRENT (IIN) BIAS CURRENT (ICC) BIAS CURRENT (ICC)

vs. INPUT VOLTAGE (VIN) vs. INPUT VOLTAGE (VIN) vs. LOAD CURRENT (IOUT)
250 1.0 MAX8794 toc05 1.4

MAX8794 toc06
MAX8794 toc04

VIN = 1.5V
0.9
VOUT = 1.25V 1.2
200 0.8 VOUT = 1.25V
0.7 1.0
VOUT = 0.90V VOUT = 1.25V
150 0.6
ICC (mA)

ICC (mA)

0.8
IIN (µA)

0.5 VOUT = 0.90V

0.4 0.6
100 ENTERING
0.3 0.4 DROPOUT
DROPOUT
50 0.2
0.2
0.1
INPUT UVLO
0 0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -2 -1 0 1 2
VIN (V) VIN (V) IOUT (A)

POWER GROUND CURRENT (IPGND) INPUT CURRENT (IIN) DROPOUT VOLTAGE

vs. SOURCE LOAD CURRENT (IOUT) vs. SINK LOAD CURRENT (IOUT) vs. OUTPUT CURRENT
0.25 7 0.30
MAX8794 toc09
MAX8794 toc08
MAX8794 toc07

VIN = 1.5V VIN = 1.5V

6 0.25
0.20
VOUT = 1.25V
5
DROPOUT VOLTAGE (V)

0.20
IPGND (mA)

0.15
IIN (mA)

4
ENTERING VOUT = 0.90V 0.15
DROPOUT
VOUT = 1.25V 3
0.10
VOUT = 1.25V 0.10 VOUT = 0.9V
2
0.05 VOUT = 0.90V 0.05
1

0 0 0
0 0.5 1.0 1.5 2.0 -2.0 -1.5 -1.0 -0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0
IOUT (A) IOUT (A) OUTPUT CURRENT (A)

4 _______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

Typical Operating Characteristics (continued)

MAX8794
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)

REFOUT VOLTAGE ERROR

vs. REFOUT LOAD CURRENT STARTUP WAVEFORM
MAX8794 toc11
20 5V

MAX8794 toc10
SHDN
15 0V
REFOUT VOLTAGE ERROR (mV)

10
1.25V
5
VOUT
0 0V

-5 4V

-10
PGOOD
-15 0V

-20
-10 -5 0 5 10 500µs/div
REFOUT LOAD CURRENT (mA)

SHUTDOWN WAVEFORM SOURCE LOAD TRANSIENT

MAX8794 toc12 MAX8794 toc13
5V
RLOAD = 100Ω SHDN
0V

2V
VOUT
1V AC-COUPLED
VOUT
1mV/div
0V

4V

1A
PGOOD
0V IOUT

0A
100µs/div 20.0µs/div

SOURCE/SINK LOAD TRANSIENT LINE TRANSIENT

MAX8794 toc14 MAX8794 toc15

3.3V
VOUT VIN (1V/div)
AC-COUPLED
5mV/div 1.5V

VOUT (10mV/div)
+1.5A AC-COUPLED
IOUT 0.9V
-1.5A
IOUT = 100mA

4.00µs/div 40µs/div

_______________________________________________________________________________________ 5
 Low-Voltage DDR Linear Regulator
MAX8794

Typical Operating Characteristics (continued)

(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)

DYNAMIC OUTPUT-VOLTAGE TRANSIENT DYNAMIC OUTPUT-VOLTAGE TRANSIENT

MAX8794 toc16 MAX8794 toc17

VIN = 1.5V 2.5V VIN = 1.8V 2.5V

VDDQ VDDQ
1.8V 1.8V

1.2V 1.2V
VREFOUT VREFOUT

0.9V 0.9V
1.2V 1.2V
VOUT VOUT
0.9V 0.9V

20.0µs/div 20.0µs/div

SINK CURRENT-LIMIT SOURCE CURRENT-LIMIT

DISTRIBUTION DISTRIBUTION
50 50
MAX8794 toc18

MAX8794 toc19
SAMPLE SIZE = 200 +25°C SAMPLE SIZE = 200 +25°C
+85°C +85°C
40 40
SAMPLE PERCENTAGE (%)

SAMPLE PERCENTAGE (%)

30 30

20 20

10 10

0 0
-4.0 -3.5 -3.0 -2.5 -2.0 2.0 2.5 3.0 3.5 4.0
SINK CURRENT LIMIT (A) SOURCE CURRENT LIMIT (A)

6 _______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

Pin Description

MAX8794
PIN NAME FUNCTION
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
1 REFOUT
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or
2 VCC
greater ceramic capacitor.
3 AGND Analog Ground. Connect the backside pad to AGND.
4 REFIN External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN).
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
5 PGOOD or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.

Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
6 OUTS remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.

Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the
7 SHDN
linear regulator. The reference buffer remains active in shutdown.
8 PGND Power Ground. Internally connected to the output sink MOSFET.
9 OUT Output of the Linear Regulator
10 IN Power Input. Internally connected to the output source MOSFET.
Exposed Pad. Connected to a large AGND ground plane with multiple vias to maximize thermal
— EP
performance.

_______________________________________________________________________________________ 7
 Low-Voltage DDR Linear Regulator

Detailed Description
MAX8794

The MAX8794 is a low-voltage, low-dropout DDR termi- VIN = VOUT = VTT = VDDQ / 2
1.1V TO 3.6V IN OUT
nation linear regulator with an external bias supply
input and a buffered reference output (see Figures 1 CIN2 COUT1
10µF 100µF
and 2). VCC is powered by a 2.7V to 3.6V supply that is
MAX8794
commonly available in laptop and desktop computers.
3.3V BIAS
The 3.3V bias supply drives the gate of the internal SUPPLY VCC PGND
pass transistor, while a lower voltage input at the drain R3
C1
of the transistor (IN) is regulated to provide VOUT. By 1.0µF AGND
100kΩ
using separate bias and power inputs, the MAX8794 POWER-GOOD
can drive an n-channel high-side MOSFET and use a PGOOD OUTS
lower input voltage to provide better efficiency. ON
OFF SHDN
The MAX8794 regulates its output voltage to the volt-
R1
age at REFIN. When used in DDR applications as a ter- 10kΩ VREFOUT = VTTR
mination supply, the MAX8794 delivers 1.25V or 0.9V at VDDQ REFIN REFOUT
3A peak (typ) from an input voltage of 1.1V to 3.6V. The R2
CREFIN CREFOUT
MAX8794 sinks up to 3A peak (typ) as required in a ter- 1000pF 0.33µF
10kΩ
mination supply. The MAX8794 provides shoot-through
protection, ensuring that the source and sink MOSFETs
do not conduct at the same time, yet produces a fast
source-to-sink load transient. Figure 1. Standard Application Circuit

3.3V BIAS VCC

SUPPLY INPUT
SOFT-
IN 1.1V TO 3.6V
EN START
UVLO

OFF ON SHDN
THERMAL
SHDN
REFIN
VDDQ
OUT
VTT

Gm
PGND

12kΩ
REFOUT
VTTR
OUTS

AGND REFIN
+150mV
EN 8Ω

REFIN
-150mV

POWER- PGOOD
GOOD
DELAY
LOGIC MAX8794

Figure 2. Functional Diagram

8 _______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

The MAX8794 features an open-drain PGOOD output connected to ceramic bypass capacitors (0.33µF to

MAX8794
that transitions high 2ms after the output initially reach- 1.0µF). REFOUT is active when VREFIN > 0.45V and
es regulation. PGOOD goes low within 10µs of when VCC is above VUVLO. REFOUT is independent of SHDN.
the output goes out of regulation by ±150mV. The
MAX8794 features current- and thermal-limiting circuitry Shutdown
to prevent damage during fault conditions. Drive SHDN low to disable the error amplifier, gate-
drive circuitry, and pass transistor (Figure 2). In shut-
3.3V Bias Supply (VCC) down, OUT is terminated to AGND with an 8Ω MOSFET.
The VCC input powers the control circuitry and provides REFOUT is independent of SHDN. Connect SHDN to
the gate drive to the pass transistor. This improves effi- VCC for normal operation.
ciency by allowing VIN to be powered from a lower sup-
ply voltage. Power V CC from a well-regulated 3.3V Current Limit
supply. Current drawn from the VCC supply remains rel- The MAX8794 features source and sink current limits to
atively constant with variations in VIN and load current. protect the internal n-channel MOSFETs. The source-
Bypass VCC with a 1µF or greater ceramic capacitor as and-sink MOSFETs have a typical 3A current limit (1.8A
close to the device as possible. min). This current limit prevents damage to the internal
power transistors, but the device can enter thermal
VCC Undervoltage Lockout (UVLO) shutdown if the power dissipation increases the die
The VCC input UVLO circuitry ensures that the regulator temperature above +165°C (see the Thermal-Overload
starts up with adequate voltage for the gate-drive cir- Protection section).
cuitry to bias the internal pass transistor. The UVLO
threshold is 2.55V (typ). VCC must remain above this Soft-Start Current Limit
level for proper operation. Soft-start gradually increases the internal source current
limit to reduce input surge currents at startup. Full-
Power-Supply Input (IN) source current limit is available after the 200µs soft-start
IN provides the source current for the linear regulator’s timer has expired. The soft-start current limit is given by:
output, OUT. IN connects to the drain of the internal
I × t
n-channel power MOSFET. IN can be as low as 1.1V, ILIMIT(SS) = LIMIT
minimizing power dissipation. The input UVLO prohibits t SS
operation below 0.9V (typ). Bypass IN with a 10µF or
where ILIMIT and tSS are from the Electrical Charac-
greater capacitor as close to the device as possible.
teristics. Figure 3 shows the MAX8794 PGOOD and
Reference Input (REFIN) soft-start waveform.
The MAX8794 regulates OUTS to the voltage set at
Thermal-Overload Protection
REFIN, making the MAX8794 ideal for memory applica-
Thermal-overload protection prevents the linear regulator
tions where the termination supply must track the sup-
from overheating. When the junction temperature
ply voltage. Typically, REFIN is set by an external
exceeds +165°C, the linear regulator and reference
resistive voltage-divider connected to the memory sup-
buffer are disabled, allowing the device to cool. Normal
ply (VDDQ) as shown in Figure 1.
operation resumes once the junction temperature cools
The maximum output voltage of 1.5V is limited by the by 15°C. Continuous short-circuit conditions result in a
gate-drive voltage of the internal n-channel power pulsed output until the overload is removed. A continuous
transistor. thermal-overload condition results in a pulsed output. For
continuous operation, do not exceed the absolute maxi-
Buffered Reference Output (REFOUT) mum junction-temperature rating of +150°C.
REFOUT is a unity-gain transconductance amplifier that
generates the DDR reference supply. It sources and
sinks greater than 5mA. The reference buffer is typically

_______________________________________________________________________________________ 9
 Low-Voltage DDR Linear Regulator
MAX8794

SHDN 200μs

CURRENT LIMIT OUTPUT OVERLOAD

CONDITION

POWER-GOOD
WINDOW

OUT
2ms STARTUP
DELAY

PGOOD
10μs 10μs
PROPAGATION PROPAGATION
DELAY DELAY

Figure 3. MAX8794 PGOOD and Soft-Start Waveforms

Power-Good (PGOOD)
The MAX8794 provides an open-drain PGOOD output REFERENCE
that goes high 2ms (typ) after the output initially reach- VOLTAGE
(VREF)
es regulation during startup. PGOOD transitions to low
after a 10µs delay when either the output goes out of
regulation by ±150mV, or when the device enters shut-
down. Connect a pullup resistor from PGOOD to VCC
for a logic-level output. Use a 100kΩ resistor to mini- R1
MAX8794
mize current consumption. CREFIN

Applications Information REFIN

Dynamic Output-Voltage Transitions R2

By changing the voltage at REFIN, the MAX8794 can
be used in applications that require dynamic output-
voltage changes between two set points (graphics
processors). Figure 4 shows a dynamically adjustable VOUT(LOW)
resistive voltage-divider network at REFIN. Using an VOUT(HIGH)
R3
external signal MOSFET, a resistor can be switched in
and out of the REFIN resistor-divider, changing the volt-
age at REFIN. The two output voltages are determined
by the following equations:
VOUT(LOW) = VREF
( )R2
R1 + R2

⎛ R2 ⎞ (R2 + R3)
VOUT(LOW) = VREF ⎜ ⎟ VOUT(HIGH) = VREF
⎝ R1 + R2 ⎠ R1 + (R2 + R3)

⎡ (R2 + R3) ⎤
VOUT(HIGH) = VREF ⎢ ⎥
⎢⎣ R1 + (R2 + R3) ⎥⎦
Figure 4. Dynamic Output-Voltage Change

10 ______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

For a step-voltage change at REFIN, the rate of change

MAX8794
of the output voltage is limited by the total output SAFE OPERATING REGION
capacitance, the current limit, and the load during the 3.5
DROPOUT VOLTAGE
transition. Adding a capacitor across REFIN and AGND LIMITED
3.0 MAXIMUM CURRENT LIMIT
filters noise and controls the rate of change of the

MAXIMUM OUTPUT CURRENT (A)

REFIN voltage during dynamic transitions. With the 2.5
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given 2.0
TA = 0°C TO +70°C
by REQ x CREFIN, where REQ is the equivalent parallel 1.5
resistance seen by the slew capacitor. VIN(MAX) - VOUT(MIN)
1.0
Operating Region and Power Dissipation
The maximum power dissipation of the MAX8794 0.5
depends on the thermal resistance of the 10-pin TDFN TA = +100°C
0
package and the circuit board, the temperature differ- 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ence between the die and ambient air, and the rate of INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
airflow. The power dissipated in the device is:
PSRC = ISRC x (VIN – VOUT) Figure 5. Power Operating Region—Maximum Output Current
PSINK = ISINK x VOUT vs. Input-Output Differential Voltage
The resulting maximum power dissipation is:
VDROPOUT = RDS(ON) x IOUT
TJ(MAX) - TA For low output-voltage applications, the sink current is
PDIS(MAX) =
θJC + θCA limited by the output voltage and the RDS(ON) of the
MOSFET.
where TJ(MAX) is the maximum junction temperature
(+150°C), TA is the ambient temperature, θJC is the Input Capacitor Selection
thermal resistance from the die junction to the package Bypass IN to PGND with a 10µF or greater ceramic
case, and θCA is the thermal resistance from the case capacitor. Bypass VCC to AGND with a 1µF ceramic
through the PCB, copper traces, and other materials to capacitor for normal operation in most applications.
the surrounding air. For optimum power dissipation, use Typically, the LDO is powered from the output of a
a large ground plane with good thermal contact to the step-down controller (memory supply) that has addi-
backside pad, and use wide input and output traces. tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
When 1in2 of copper is connected to the device, the
maximum allowable power dissipation of a 10-pin TDFN Output Capacitor Selection
package is 1951mW. The maximum power dissipation is The MAX8794 output stability is independent of the out-
derated by 24.4mW/°C above TA = +70°C. Extra copper put capacitance for C OUT from 10µF to 220µF.
on the PCB increases thermal mass and reduces ther- Capacitor ESR between 2mΩ and 50mΩ is needed to
mal resistance of the board. Refer to the MAX8794 eval- maintain stability. Within the recommended capaci-
uation kit for a layout example. tance and ESR limits, the output capacitor should be
The MAX8794 delivers up to 3A and operates with input chosen to provide good transient response:
voltages up to 3.6V, but not simultaneously. High output ∆IOUT(P-P) x ESR = ∆VOUT(P-P)
currents can only be achieved when the input-output where ∆IOUT(P-P) is the maximum peak-to-peak load-
differential voltages are low (Figure 5). current step (typically equal to the maximum source
Dropout Operation load plus the maximum sink load), and ∆VOUT(P-P) is
A regulator’s minimum input-to-output voltage differen- the allowable peak-to-peak voltage tolerance.
tial (dropout voltage) determines the lowest usable sup- Using larger output capacitance can improve efficiency
ply voltage. Because the MAX8794 uses an n-channel in applications where the source and sink currents
pass transistor, the dropout voltage is a function of the change rapidly. The capacitor acts as a reservoir for
drain-to-source on-resistance (RDS(ON) = 0.25Ω max) the rapid source and sink currents, so no extra current
multiplied by the load current (see the Typical is supplied by the MAX8794 or discharged to ground,
Operating Characteristics): improving efficiency.

______________________________________________________________________________________ 11
 Low-Voltage DDR Linear Regulator

Noise, PSRR, and Transient Response PCB Layout Guidelines

MAX8794

The MAX8794 operates with low-dropout voltage and The MAX8794 requires proper layout to achieve the
low quiescent current in notebook computers while intended output power level and low noise. Proper lay-
maintaining good noise, transient response, and AC- out involves the use of a ground plane, appropriate
rejection specifications. Improved supply-noise rejec- component placement, and correct routing of traces
tion and transient response can be achieved by using appropriate trace widths. Refer to the MAX8794
increasing the values of the input and output capaci- evaluation kit for a layout example:
tors. Use passive filtering techniques when operating 1) Minimize high-current ground loops. Connect the
from noisy sources. ground of the device, the input capacitor, and the
The MAX8794 load-transient response graphs (see the output capacitor together at one point.
Typical Operating Characteristics) show two compo- 2) To optimize performance, a ground plane is essen-
nents of the output response: a DC shift from the output tial. Use all available copper layers in applications
impedance due to the load-current change and the where the device is located on a multilayer board.
transient response. A typical transient response for a
step change in the load current from -1.5A to +1.5A is 3) Connect the input filter capacitor less than 10mm
10mV. Increasing the output capacitor’s value and from IN. The connecting copper trace carries large
decreasing the ESR attenuate the overshoot. currents and must be at least 2mm wide, preferably
5mm wide.
4) Connect the backside pad to a large ground plane.
Use as much copper as necessary to decrease the
thermal resistance of the device. In general, more
copper provides better heatsinking capabilities.

Chip Information Package Information

TRANSISTOR COUNT: 3496 For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
PROCESS: BiCMOS the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

10 TDFN-EP T1033+1 21-0137

12 ______________________________________________________________________________________
 Low-Voltage DDR Linear Regulator

Revision History

MAX8794
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 8/06 Initial release —
1 10/07 Revised Ordering Information. 1
Added the automotive version to Ordering Information and revised the
2 3/10 1, 2, 7
Absolute Maximum Ratings and Pin Description.

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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