Motivation for CDR: Deserializer (1)

1:2
Input data DMUX

1:2
DMUX

channel 1:2
DMUX

Input clock

÷2 ÷2

If input data were accompanied by a well-synchronized clock, deserialization

could be done€directly. €

EECS 270C Prof. M. Green / Univ. of California, Irvine 1

 Motivation for CDR (2)
•  Providing two high-speed channels (for data & clock) is expensive.

•  Alignment between data & clock signals can vary due to different channel
characteristics for the different frequency components. Hence retiming
would still be necessary.

Clock

Data

retimed data
input data Clock
Recovery
circuit
recovered clock

PLLs naturally provide synchronization between external and internal timing sources.
A CDR is often implemented as a PLL loop with a special type of PD...

EECS 270C Prof. M. Green / Univ. of California, Irvine 2

 Return-to-Zero vs. Non-Return-to-Zero Formats

()
Sx f

NRZ €

()
Sx f 1 2 3 f
Tb
Tb Tb Tb

RZ
€
€ € €
2 f
1 0 1 1 0 1 0 Tb

RZ spectrum has energy at 1/Tb ⇒ conventional phase detector can be used.

NRZ spectrum has null at 1/Tb ⇒ ??

EECS 270C
€ Prof. M. Green / Univ. of California, Irvine 3

€
 Phase Detection of RZ Signals

Vdata Vd
VRCK

Vdata
VRCK

Vd

•  Phase detection operates same as for clock signals for logic 1.

•  Vd exhibits 50% duty cycle for logic 0.
•  Kpd will be data dependent.

EECS 270C Prof. M. Green / Univ. of California, Irvine 4

 Phase Detection of NRZ Signals

Vdata Vd
VRCK

Vdata
VRCK

Vd

Since data rate is half the clock rate, multiplying phase detection is ineffective.

•  RZ signals can use same phase detector as clock signals

•  RZ data path circuitry requires bandwidth that is double that of NRZ.
•  Different type of phase detection required for NRZ signals.

EECS 270C Prof. M. Green / Univ. of California, Irvine 5

Idea: Mix NRZ data with delayed version of itself
instead of with the clock.

Example: 1010 data pattern (differential signaling)

• • •
Tb 1 3 5
2Tb 2Tb 2Tb
€€€

*
€ € €
X • • •
1 3 5
2Tb 2Tb 2Tb
€€€

€ € €

= =
• • •
1 2
Tb Tb
€€€
fundamental generated
EECS 270C Prof. M. Green / Univ. of California, €
Irvine € 6
 Operation of D Flip-Flips (DFFs)
DFF:
CMOS transmission gate:
CK CK
D QI Q

CK CK CK CK
latch:

CK CK CK
Master Slave
D QI
Ideal waveforms:
CK CK Symbol:
D D0 D1 D2

D Q
CK CK

Q D0 D1 D2

No bubble ⇒ Q changes following rising edge of CK

EECS 270C Prof. M. Green / Univ. of California, Irvine 7
 DFF Setup & Hold Time

At CK rising edge, the master latches and the slave drives.

D
tsetup thold

CK

When a data transition occurs within the setup & hold region, metastability occurs.

EECS 270C Prof. M. Green / Univ. of California, Irvine 8

 DFF Clock-to-Q Delay

CK CK
D QI Q

CK CK CK CK

CK Slave CK
Master

D D0 D1 D2

tck-q is determined by delays of

CK transmission gate and inverter.

Q D0 D1 D2
tck-q
EECS 270C Prof. M. Green / Univ. of California, Irvine 9
 P
Realization of Data/Data Mixing : Din
Q
RCK Same as Din,
synchronized with RCK

RCK early: RCK synchronized:

Din D0 D1 D2 D3 D0 D1 D2 D3

RCK

Q D0 D1 D2 D3 D0 D1 D2 D3

P
D0 D1 D2 D3 D0 D1 D2 D3
⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕
D1 D2 D3 D4 D1 D2 D3 D4
Delay€ between
€ Din to Q€is related
€ to phase between
€ Din & €
RCK € €
EECS 270C Prof. M. Green / Univ. of California, Irvine 10
Define zero phase difference as a data transition coinciding with RCK falling edge;
i.e., RCK rising edge is in center of data eye.

RCK early (Δφ < 0): RCK synchronized (Δφ = 0):

Din

RCK

Δt Δt
Tb Tb

Δφ Δt 1 % Δφ 1(
= − Δt = Tb ' + *
2π Tb 2 & 2 π 2)
EECS 270C Prof. M. Green / Univ. of California, Irvine 11

€ €
 P
Phase detector characteristic Din
also depends on transition Q
RCK
density:

0101… pattern: 0011… pattern:

Din

RCK

P Vswing
% Δt 1 ( % Δt 1 (
VP = Vswing ⋅ ' − * VP = Vswing ⋅ ' − *
& Tb 2 ) & 2Tb 2 )

In
€ general, €
& Δt 1 )
VP = Vswing ⋅ (α − + where α ≡ average transition density
' Tb 2 *
EECS 270C Prof. M. Green / Univ. of California, Irvine 12

€
 Constructing CDR PD Characteristic

Δt Δφ 1
= +
Tb 2 π 2 VP α (α −1)
= Δφ +
VP Δt 1 Vswing 2π 2 VP
=α − Vswing
Vswing Tc 2 1
α=1
€ +
2

€ -π € +π
€ α € Δφ
slope: K pd =
2π 1
−
intercept: VP α −1 2 α = 0.5
Δφ = 0 ⇒ = α = 0.25
Vswing 2
€ €

€ Both slope and offset of phase-voltage characteristic

vary with transition density!

EECS 270C Prof. M. Green / Univ. of California, Irvine 13

 To cancel phase offset:
P Q D0 D1 D2 D3
Din
Q RCK
RCK

QR D0 D1 D2 D3
R
R
QR
Always 50% duty cycle;
average value is (α −1) ⋅Vswing 2

VP −VR
Vswing
+1/2 α = 1€ Kpd still varies with α,
α = 0.5 but offset variation cancelled.
-π €
Δφ
+π
C. R. Hogge, “A self-correcting clock recovery circuit,”
IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec.
-1/2 1985.
€
EECS 270C Prof. M. Green / Univ. of California, Irvine 14
 Transconductance Block

Iout+ Iout-
P+ P- R- R+

ISS ISS

EECS 270C Prof. M. Green / Univ. of California, Irvine 15

 Non-Idealities in Hogge Phase Detector:
A. Clock-to-Q Delay (1)

Din

P RCK
Din
Q €
RCK Q
tck-Q €
R QR
€
QR
P = Din ⊕ Q
tck-Q €
R = Q ⊕ QR
€
EECS 270C Prof. M. Green / Univ. of California, Irvine 16

€
 Non-Idealities in Hogge Phase Detector:
A. Clock-to-Q Delay (2)
Result is an input-referred phase offset:

Din
VP − VR
RCK Vswing
+α/2
tck-Q Δφ
Q € φos
-α/2
tck-Q
QR €

P tck −Q
φos = 2π
Tb
R

EECS 270C Prof. M. Green / Univ. of California, Irvine 17

€
 Non-Idealities in Hogge Phase Detector:
A. Clock-to-Q Delay (3)

tck-Q
Din

RCK

Dout Phase offset moves RCK away from

Din center of data, making retiming less
CDR robust.
RCK

EECS 270C Prof. M. Green / Univ. of California, Irvine 18

 Non-Idealities in Hogge Phase Detector:
A. Clock-to-Q Delay (4)
Use a compensating delay:
Din
Set Δt ≈ tCK−Q

Δt DΔt DΔt
€ P
RCK
Din
Q
RCK Q

tck-Q
R QR

QR P

tck-Q R

EECS 270C Prof. M. Green / Univ. of California, Irvine 19

 Non-Idealities in Hogge Phase Detector:
B. Delay Between P & R (1)

Din

RCK
P
Din
Q Q
RCK

QR
R
P
QR

P and R are offset by 1/2 clock period

EECS 270C Prof. M. Green / Univ. of California, Irvine 20

 Non-Idealities in Hogge Phase Detector:
B. Delay Between P & R (2)

P Average value of Vcontrol is

well-controlled, but resulting ripple
causes high-frequency jitter.
R

P
Din Vcontrol
Q
RCK
to VCO

QR

EECS 270C Prof. M. Green / Univ. of California, Irvine 21

 Non-Idealities in Hogge Phase Detector:
B. Delay Between P & R (3)
Idea: Based on R output,
create compensating pulses:
Standard Hogge/charge pump P
operation for single input pulse: Din
RCK DFF
Din
€ R
RCK

Q latch

€ P"
QR

P (up) latch

R (dn)
€ R"

Vcontrol latch

EECS 270C Prof. M. Green / Univ. of California, Irvine € 22

 Non-Idealities in Hogge Phase Detector:
B. Delay Between P & R (4)
Din
P
Din RCK
RCK Q1 Q1
DFF

€ R Q2
Q3
Q2
latch
Q4
€ P"
P (up)
Q3 R (dn)
latch
€ R" P’(dn)

R’(up)
Q4
latch
Vcontrol
€
Cancels out effect of next pulse
EECS 270C Prof. M. Green / Univ. of California, Irvine 23
 Other Nonidealities of Hogge PD (1)

60
PD Differential Output (mV)

40 response from
ideal linear PD
20

-20

-40 simulated result

of one linear PD
-60

-50p -40p -30p -20p -10p 0 10p 20p 30p 40p 50p
Data Delay in regard to Clock (s)

EECS 270C Prof. M. Green / Univ. of California, Irvine 24

 Other Nonidealities of Hogge PD (2)

Effect of Transition Density:

EECS 270C Prof. M. Green / Univ. of California, Irvine 25

 Other Nonidealities of Hogge PD (3)
Effect of DFF bandwidth limitation:

EECS 270C Prof. M. Green / Univ. of California, Irvine 26

 Other Nonidealities of Hogge PD (4)
Effect of XOR bandwidth limitation:

Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect.

EECS 270C Prof. M. Green / Univ. of California, Irvine 27

 Other Nonidealities of Hogge PD (5)

Effect of XOR Asymmetry:

EECS 270C Prof. M. Green / Univ. of California, Irvine 28

 Binary Phase Detectors
Idea: Directly observe phase alignment between clock & data

Clock falling edge early: Clock falling edge centered: Clock falling edge late:
Decrease Vcontrol No change to Vcontrol Increase Vcontrol

VP
Ideal binary Vswing
phase-voltage characteristic: +1/2 Also known as
“bang-bang” phase detector
€
Δφ
-1/2

EECS 270C Prof. M. Green / Univ. of California, Irvine 29

 D Flip-Flop as Phase Detector

Din
Early clock:
Data transitions align
with clock low RCK

Late clock: Din

Data transitions align
with clock high
RCK

Top (bottom) DFF detects on Din rising (falling)

edge; DFF selected by opposite Din edge to
Realization using double-clocked DFF; note avoid false transitions due to clock-q delay.
that RCK/Din connections are reversed:
Din
RCK VP
= RCK VP
Din
€
Din
EECS 270C Prof. M. Green / Univ. of California, Irvine Din 30
€

€
 What happens if Δφ=0?

tsetup

thold

•  If transition at D input occurs within

setup/hold time, metastable operation
D
results.
•  Q output can “hang’’ for an arbitrarily
long time if zero crossings of D & CK CK
occur sufficiently close together.
•  Metastable operation is normally
avoided in digital circuit operation(!) Q

EECS 270C Prof. M. Green / Univ. of California, Irvine 31

 Dog Dish Analogy

???

A dog placed equidistant between two dog dishes will starve (in theory).

EECS 270C Prof. M. Green / Univ. of California, Irvine 32

 Non-Idealities in Binary DFF Phase Detector

1.  Metastable operation difficult to characterize & simulate, varies widely

over processing/temperature variations. Kpd (and therefore jitter transfer
function parameters) are difficult to analyze. Exact value of Kpd depends
on metastable behavior and varies with input jitter.
2.  Large-amplitude pattern-dependent variation is present in phase detector
output while locked.
3.  During long runs phase detector output remains latched, resulting in VCO
frequency changing continuously:

Din

RCK

€ VP

fvco

EECS 270C Prof. M. Green / Univ. of California, Irvine 33

€
 Idea: Change VCO frequency for only one clock period

Din

RCK
€
VP

RCK early RCK late

Circuit realization should sample data with clock (instead of clock with data)
while maintaining bang-bang operation.

EECS 270C Prof. M. Green / Univ. of California, Irvine 34

 Alexander Phase Detector
DN

UP
Q1 Q2

Din
Q3 Q4
RCK
€
Din
RCK
Q1
€ Q2

Q3
Q4
DN
UP

RCK early RCK late

Q1 leads Q3; Q2/Q4 in phase Q3 leads Q1; Q1/Q4 in phase

EECS 270C Prof. M. Green / Univ. of California, Irvine 35

 Simulation Results: Alexander PD

DFF outputs

VCO control
voltage

EECS 270C Prof. M. Green / Univ. of California, Irvine 36

 Simulation Comparison:
Linear vs. Binary
Vcontrol Vcontrol

Linear PD Binary PD

•  very small freq. acquisition range •  high freq. acquisition range

•  low steady-state jitter •  high steady-state jitter

EECS 270C Prof. M. Green / Univ. of California, Irvine 37

 Half-Rate CDRs

To relax speed requirements for a given fabrication technology, a half-

rate clock signal can be recovered:

Din input data

RCK full-rate recovered clock

RCK2 half-rate recovered clock

•  Can be used in in applications (e.g., deserializer) where full-rate clock is

not required.

•  Duty-cycle distortion will degrade bit-error ratio & jitter tolerance

compared to full-rate versions.

EECS 270C Prof. M. Green / Univ. of California, Irvine 38

Idea 1: Input data can be immediately
demultiplexed with half-rate clock
Din DA

RCK2

DB

RCK2

Din D0 D1 D2 D3 D4

DA D0 D2 D4
synchronized with
DB D3
clock transitions
D1

EECS 270C Prof. M. Green / Univ. of California, Irvine 39

 Din XA DA
Splitting D flip-flops
into individual latches: RCK2
latch latch

XB DB

latch latch

RCK2

Din

XA synchronized with
both RCK2 & Din
XB

DA synchronized with
These pulse widths DB RCK2
contain phase information.
EECS 270C Prof. M. Green / Univ. of California, Irvine 40
 Complete Linear Half-Rate PD

XA DA RCK2
Din
RCK2 1 Din
×
2
P R
XA
XB € DB

XB

P = X A ⊕ XB

DA
J. Savoj & B. Razavi, “A 10Gb/s CMOS €
clock and data recovery circuit with a
half-rate linear phase detector,” DB
JSSC, vol. 36, pp. 761-768, May 2001.
R = DA ⊕ DB

EECS 270C Prof. M. Green / Univ. of California, Irvine 41

€
 Idea 2: Observe timing between Din, RCK and quadrature RCKQ

Din Din

RCK RCK

RCKQ RCKQ

S0 S1 S2 S0 S1 S2

Clock early Clock late

Phase logic:
S0, S2 sampled with RCK transitions
S1 sampled with RCKQ transitions
(S ⊕ S = 0) and (S ⊕ S = 1) ⇒
0 1 1 2 clock late
(S ⊕ S = 1) and (S ⊕ S = 0) ⇒
0 1 1 2 clock early
(S ⊕ S = 0) and (S ⊕ S = 0) ⇒
0 1 1 2 no transition
€
EECS 270C Prof. M. Green / Univ. of California, Irvine 42
€
€
 Din DI

RCK VPD

DQ
J. Savoj & B. Razavi, “A 10-Gb/s
RCKQ CMOS clock and data recovery
circuit with a half-rate binary
phase detector,” JSSC, vol. 38,
pp. 13-21, Jan. 2003.
Din Din

RCK RCK

RCKQ RCKQ

DI DI

DQ DQ

VPD VPD

Clock early Clock late

EECS 270C Prof. M. Green / Univ. of California, Irvine 43
 DLL-Based CDRs

fref fck phase generator

CMU •  CMU JBW can be optimized
to minimize fck jitter.
phase CDR loop
MUX
•  No VCO inside CDR loop;
less jitter generation.
•  Can be arranged to have
VC faster lock time.
Din PD •  Due to discrete phases of
recovered clock available,
C the clock and data will never
be exactly aligned.
Dout
retimer

EECS 270C Prof. M. Green / Univ. of California, Irvine 44

 Fast-Lock CDR for Burst-Mode Operation

Gated ring oscillator:

EN
EN high: 7-stage ring oscillator
EN low: no oscillation

CDR based on 2 gated ring oscillators:

Each ring oscillation

Din waveform is forced to
RCK sync with one of the Din
phases.

EECS 270C Prof. M. Green / Univ. of California, Irvine 45