Chapter 1 Question
Chapter 1 Question
8. Which type of PLD used multiple circuit blocks to program the logic functions?
a) PLA
b) PAL
c) CPLD
d) SLD
11. A CPLD is a
a) controlled program logic device
b) complex programmable logic driver
c) complex programmable logic device
d) central processing logic device
13. Many companies are transitioning to using FPGAs for their processor designs
instead of ASICs. Why?
a) FPGAs always outperform an ASIC
b) The development cycle for an FPGA is much shorter
c) FPGAs are both smaller and faster
d) FPGAs are more space-efficient
14. __________ are the EDA tools for front-end design process.
a) Design entry
b) Simulation tools
c) Synthesis tools
d) All of these
15. HDL is a
a) logic device
b) PLD programming language
c) computer language
d) very high density logic
16. HDL can be used to
a) Represent Boolean expressions and complex abstraction of the behaviour
of a digital system
b) Represent logic diagram and truth tables only
c) Represent logic diagram, truth table, Boolean expressions and complex
abstraction of the behaviour of a digital design
d) None of the above
17. Which the following statements is not relevant regarding the goal of the HDL?
a) Most reliable design process
b) With maximum cost and time
c) With minimum cost and time
d) Free of design errors
20. Which of the following features of the HDL structural modeling is NOT true?
a) It cannot model the gate’s delay
b) It is suitable for the large logic system
c) The order of the gate instantiations does not matter
d) It requires users to pre-minimize the logic function.