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Vlsi Programs (Ag, CNTRS)

The document describes a module that implements all basic logic gates. It defines inputs a and b and outputs the logic functions of a and b on wires y[0] through y[6], including NOT, AND, NAND, OR, NOR, XOR, and XNOR. It also includes a test module that applies different input patterns to the gates and holds them for a specified time.

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madhusudhan
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17 views

Vlsi Programs (Ag, CNTRS)

The document describes a module that implements all basic logic gates. It defines inputs a and b and outputs the logic functions of a and b on wires y[0] through y[6], including NOT, AND, NAND, OR, NOR, XOR, and XNOR. It also includes a test module that applies different input patterns to the gates and holds them for a specified time.

Uploaded by

madhusudhan
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ALL GATES

module allgates(a,b,y);

input a,b;

output [0:6] y;

assign y[0]=~a;

assign y[1]=a&b;

assign y[2]=~(a&b);

assign y[3]=a|b;

assign y[4]=~(a|b);

assign y[5]=a^b;

assign y[6]=~(a^b);

endmodule

Test

module allgates_test;

reg a,b;

wire [0:6] y;

allgates uut(.a(a),.b(b),.y(y));

initial

begin

a=1'b0;b=1'b0;#100;

a=1'b0;b=1'b1;#200;

a=1'b1;b=1'b0;#300;

a=1'b1;b=1'b1;#400;

end

endmodule
Up down counters

module aupdown(rst,clk,en,up_down,q);

input rst,clk,en,up_down;

output [3:0] q;

reg[3:0]q;

always @ (posedge clk)

begin

if (rst==1)

q<= 4'b0000;

else if (en== 1)

begin

if (up_down==1)

q<=q+1;

else

begin

q<=q-1;

end

end

else

q <= 4'b0000;

end

endmodule
Test bench

module test;

reg rst,clk,en,up_down;

wire [3:0] q;

aupdown counter1(rst,clk, en,up_down,q);

initial

begin

clk= 1'b0;

forever #100 clk = ~ clk;

end

initial

begin

rst = 1'b1;#300;

rst = 1'b0;

en = 1'b1;

up_down = 1'b1;#3300;

up_down = 1'b0;#6600;

end

initial #6500 $finish;

endmodule

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