Performance Improvement of QCA Design XOR Logic Gate Using Bistable Simulation Engine Vector
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Editor IJTSRDPerformance Improvement of QCA Design XOR Logic Gate Using Bistable Simulation Engine Vector
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Editor IJTSRDInternational Journal of Trend in Scientific Research and Development (IJTSRD)
International Open Access Journal | www.ijtsrd.com
ISSN No: 2456 - 6470 | Volume - 2 | Issue – 6 | Sep – Oct 2018
Performance Improvement of QCA Design XOR Logic Gate using
Bistable Simulation Engine Vector
Haritika Satle
Satle, Aastha Hajari
Embedded System and VLSI Design
Design, Department of Electronics and Communication Engineering,
Engineering
Shiv Kumar Singh Institute of Technology & Science (SKSITS), Indore
Indore, Madhya Pradesh,
Pradesh India
ABSTRACT
Among the emerging technologies recently proposed contains two electrons and four quantum dots and due
as alternatives to the CMOS technology, the quantum
quantum- to Coulomb interaction between these identical
dot cellular automata is one of the promising solutions charges, they occupy dots diagonally. As a result, the
to design very high speed and ultralow power digital two stable polarization states for a QCA cell are
circuits. In this paper we used QCA Designer achieved, as shown in Figure 1. 1 The instantaneous
simulator
imulator tool for simulation of the proposed XOR polarization of a cell is denoted as either -1 or +1 [2],
design. The QCA Designer tools used to simulate the which are encoded to represent a binary “1” value and
circuits and calculate the area as well as number of “0” value, respectively. In order to create any digital
cells. logic, basic elements including wire, NOT gate, AND
gate, OR gate and majority gate g are required to
Keyword: QCA, XOR, Majority Gate, QCA Cells, implement that logic [1, 3]. Since no electrons tunnel
Bistable Simulation Engine. between cells, QCA provides a mechanism for
transferring information without current flow [6].
I. INTRODUCTION
QCA is a computational nanotechnology that can be
used to construct nano-scale
scale circuits. Nowadays, this
technology is a popular alternative for CMOS
technology due to features such as speed, low
occupied area and low power consumption [1]. The
many technologies have been investigated such as
Carbon Nano Tube field effect transistors
(CNTFETs), Single electron transistors (SETs), Fig.1: Basic QCA cell with two binary state [7]
Quantum-dotdot cellular automata (QCA) and others.
QCA is a promising technology supporting a The Majority voter (M),, five QCA cells that realize
transistor-less paradigm. This QCA technology has the function of in equation 1, and its QCA design is
quantum cells. The quantum cells has 2 electrons shown in figure 2.
present at a time, has 4 quantum wells and 2 electrons
are occupies in adjacent position to each other. The , ,
1
rest of paper is organised in section A.1 is QCA
building blocks, II-Sectiontion QCA clock diagram
dissection, Section-III
III Simulation design and results
and last section IV is conclusion and references at the
last of paper.
A. QCA building blocks
The building blocks are determined by the
fundamental logic gate structure. Each QCA cell Fig. 2: MV QCA Design
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International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
2456
For example, a two-input
input AND gate is realized by
fixing one of the majority gate inputs to “0,” that is in
equation 2,
, , , 0 .
2
Fig. 3:: AND Logic Gate using QCA Cells Fig. 5: QCA Clock [7]
Similarly, an OR gate is realized by fixing one input III. SIMULATION RESULTS
to “1,” that is in equation 3, We are proposed two different QCA “XOR logic
design” in figure 4.5 XOR--1 with using Quantum
, , , 1
3 cells 27 used design area in 0.04 µm2 with utilized
single layer design and clock cycle delay count one.
This design is efficient in team of design cell area as
well as used cell count.
Fig. 4: QCA OR Logic Gate
II. QCA CLOCK
In QCA technology, storage cells do not require an
external power source to maintain their current stable
polarization. Actually, the clock controls the flow of
charge in the circuit. The QCA clock consists of four
clock phases, i.e.
.e. Switch, Hold, Release, and Relax,
which span a 90 degree out-of of phase progression [4,
5]. It is shown in figure 5 for QCA clock diagram.
This diagram x-axis
axis represents the time and YY-axis
represents the inter-dot-barrier. Fig. 6: Proposed QCA-XOR
XOR Logic Gate Design
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International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
2456
Fig. 77: Simulation of XOR Logic Gate
Table 1: Comparison of Proposed Design and Previous design of QCA XOR
Design Cell Area Delay
Proposed Design XOR 27 0.04 1
Mrinal Goswami (2014) et al. [9] 40 0.04 3
Young-Won
Won You (2016) et al. [10] 44 0.05 4
IV. CONCLUSIN 3. Shanthala.G.M, Riazini and Karthik.P “Design
CMOS technology is approaching its scaling limit and Implementation of Scan Flip-flop
Flip for
very fast. Quantum-dot
dot Cellular Automata (QCA) is Processor Using QCA Technology” International
an emerging nanotechnology, with extremely small Journal of Control and Automation Vol.10, No.8
feature size and ultra low power consumption (2017), pp.41-52.
compared to transistor-basedbased technology. The 4. S. Sheikhfaal, S. Angizi, S. Sarmadi, M. H.
proposed design resultss analysis is shown in table 1 in
Moaiyeri, and S. Sayedsalehi, "Designing efficient
this table we compared the both design XOR logic
QCA logical circuits with power dissipation
gate on the bases of quantum cells, design area and analysis," Microelectronics Journal, vol. 46, pp.
delay. The proposed design used the bistable
462-471, 2015.
simulation engine.
5. S. Srivastava, S. Sarkar, and S. Bhanja,
REFRENCES "Estimation of upper bound of power dissipation
1. Javad Chaharlang, Mohammad Mosleh ““An in QCA circuits," Nanotechnology, IEEE
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view on RAM memories in QCA technology
technology” transactions
tions on, vol. 8, pp. 116-127,
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Majlesi Journal of Electrical Engineering, Vol. 6. Fenghui Yao, Mohamed Saleh Zein-Sabatto,
11(2), 2017. Guifeng Shao, Mohammad Bodruzzaman, and
2. G. Cocorullo, P. Corsonello, F. Frustaci and S. Mohan Malkani “Nanosensor
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Perri “Design of Efficient BCD Adders in Quantum-Dot Cellular Automata”
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Quantum-Dot ot Cellular Automata” IEEE Nanotechnology Vol. 2014, Article ID 259869, 14
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International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
2456
7. Patidar M., Gupta N. (2019) Efficient Design and 9. Goswami,
swami, M., Kumar, B., Tibrewal, H., &
Simulation of Novel Exclusive-OROR Gate Based on Mazumdar, S. (2014). Efficient realization of
Nanoelectronics Using Quantum--Dot Cellular digital logic circuit using QCA multiplexer. 2014
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10. Young-Won
Won You and Jan-Chelo
Jan Jeon (2016),
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Oct 2018 Page: 1194
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