EL2095 Digital System

Sequential Logic (CH8 – FSM Design)

Sekolah Teknik Elektro dan Informatika
Institut Teknologi Bandung
State Machine Design
 Opposite of analysis
 Given
 a specification of the behavior of the state machine
including
 inputs
 desired outputs
 timing diagram
 Find
 state diagram
 circuit diagram
Steps in State Machine Design
1. Create a state diagram
2. Create a state/output table
3. (Optional) Minimize the number of states
4. Choose state variables and assign combinations to the states
5. Choose flip-flop type (D is easiest)
6. Construct an excitation table showing the excitation values
needed to obtain the next state
7. Derive logic equations for the excitations and outputs
8. Draw logic diagram showing flip-flops and the excitation and
output equations
Example (Sequence Detector)
 Circuit has one input w, one output z w z
 All changes occur on the positive FSM
clock edge clk
 The output z=1 if w=1 during two
immediately preceding clock cycles; reset
otherwise z=0
Example Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
input w: 0 1 0 1 1 0 1 1 1 0 1
sequence z: 0 0 0 0 0 1 0 0 1 1 0
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0

1
Timing w
diagram 0
1
z
0
Understanding the problem (Step 0)
 The output z=1 if w=1 during two immediately preceding
clock cycles; otherwise z=0
Next State
Present State Output
w=0 w=1
Initial State (no 1’s) Initial State Got 1 1’s 0
Got 1 1’s Initial State Got 2 1’s 0
Got 2 1’s Initial State Got 2 1’s 1
Understanding the problem (Step 0)
 The output z=1 if w=1 during two immediately preceding
clock cycles; otherwise z=0
Next State
Present State Output
w=0 w=1
Initial State (no 1’s) Initial State Got 1 1’s 0
Got 1 1’s Initial State Got 2 1’s 0
Got 2 1’s Initial State Got 2 1’s 1

Present Next State

Output
State w=0 w=1
A A B 0
B A C 0
C A C 1
State Diagram (Step 1)
Reset

w = 1
w = 0 Az= 0 Bz= 0

w = 0

w = 0 w = 1
Present Next State
Output
State w=0 w=1
A A B 0 Cz = 1

B A C 0
C A C 1
w = 1
State Assignment (Step 2 and 4, we skip step 3)
 We need at least two FF’s
State transition/output table
for three states
Next State
 Let’s pick two FF’s, call Present
Output
State w=0 w=1
them y1 and y2
y2 y1 Y2 Y1 Y2 Y1 z
 Assign states to 0 0 0 0 0 1 0
combinations of (y1,y2): 0 1 0 0 1 0 0
 A: (0,0) 1 0 0 0 1 0 1
 B: (0,1) 1 1 d d d d d

 C: (1,0)
y2,y1 = present state
 (note - we will never need
the combination 1,1) Y2,Y1 = next state
Excitation Table (Step 5 and 6)
 Using D flip-flops: Excitation/output table
 Characteristic Equation Q*=D Next State
Present
 If we want next state to be Y State
Output
then w=0 w=1
 Y must be the input to the FF’s y2 y1 D2 D1 D2 D1 z
 Now derive logic functions 0 0 0 0 0 1 0
for 0 1 0 0 1 0 0
 Y1(y2,y1,w) 1 0 0 0 1 0 1
 Y2(y2,y1,w)
1 1 d d d d d
 z(y2,y1)
for D flip-flops, excitation table is the
same as state transition table
Q* = D so Y = D
Excitation/Output Equations (Step 7)
y 2 y1
w 00 01 11 10 Present Next State
Output
0 0 0 d 0 State w=0 w=1
1 1 0 d 0 y2 y1 D2 D1 D2 D1 z
0 0 0 0 0 1 0
D1  wy1 y2
0 1 0 0 1 0 0
y2y1 1 0 0 0 1 0 1
w 00 01 11 10
1 1 d d d d d
0 0 0 d 0
1 0 1 d 1
y1
D2  wy1  wy2 y2 0 1
0 0 0
1 1 d
z  y2
 Implementation (Step 8)

D2  wy1  wy2 Y2
D Q
y2
z z  y2
D2  w( y1  y2 )
Q

D1  wy1 y2
Y1 y1
w D Q

Clock
Resetn
 Present Next State
Output
State w=0 w=1
Timing Diagram y2 y1 Y2 Y1 Y2 Y1 z
A 0 0 0 0 0 1 0
B 0 1 0 0 1 0 0
C 1 0 0 0 1 0 1
D 1 1 d d d d d

CLK

y1

y2
z
A A A B A B C A
Same Problem different implementation
 This time use JK FF Present Next State
Output
State w=0 w=1
 From Step 5
y2 y1 Y2 Y1 Y2 Y1 z
 Select JK FF 0 0 0 0 0 1 0
 Q* = JQ’ + K’Q 0 1 0 0 1 0 0
 So 1 0 0 0 1 0 1

 Y2 = J2y’2 + K’2y2 1 1 d d d d d

 Y1 = J1y’1 + K’1y1
 What JK input we
must apply to
produce transition
from Q → Q*?
 State table
Excitation Table (Step 6)
Present Next State
Output
 JK transitions (y → Y) State w=0 w=1

 0 → 0 : JK = 0d y2 y1 Y2 Y1 Y2 Y1 z
0 0 0 0 0 1 0
 0 → 1 : JK = 1d
0 1 0 0 1 0 0
 1 → 0 : JK = d1
1 0 0 0 1 0 1
 1 → 1 : JK = d0
1 1 d d d d d
Excitation table

Present Next State

Output
State w=0 w=1
y2 y1 J2 K2 J1 K1 J2 K2 J1 K1 z
0 0 0 d 0 d 0 d 1 d 0
0 1 0 d d 1 1 d d 1 0
1 0 d 1 0 d d 0 0 d 1
1 1 d d d d d d d d d
Derive Logic Excitation table

Function (Step 7) Present

State
Next State
Output
w=0 w=1
 J1(y2,y1,w) y2 y1 J2 K2 J1 K1 J2 K2 J1 K1 z
 K1(y2,y1,w) 0 0 0 d 0 d 0 d 1 d 0
 J2(y2,y1,w) 0 1 0 d d 1 1 d d 1 0
 K2(y2,y1,w) 1 0 d 1 0 d d 0 0 d 1
 z(y2,y1) 1 1 d d d d d d d d d

y2 y 1 y2 y1
w 00 01 11 10 w 00 01 11 10
0 0 d d 0 0 0 0 d d
y1
1 1 d d 0 1 0 1 d d y2 0 1
0 0 0
J1  wy2 J 2  wy1
y2y1 y2y1 1 1 d
w 00 01 11 10 w 00 01 11 10
0 d 1 d d 0 d d d 1 z  y2
1 d 1 d d 1 d d d 0

K1  1 K2  w
Dram Circuit (Step 8)
J1  wy2
w Y1 y1
K1  1 J
SET
Q
J 2  wy1
vcc
K2  w
K CLR Q
z  y2

Y2 SET
y2 z
J Q

K CLR Q
 Example of Sequence Generator
Secure Car Key
 Many new car keys
include tiny computer
chip
 When car starts, car’s Present Next State Output
computer (under engine State a=0 a=1 r
hood) requests identifier Wait Wait First 0
from key by sending a First Second Second 1
signal to the key (Input a) Second Third Third 1
 Key transmits identifier Third Fourth Fourth 0
 Identifier a sequence of 4 Fourth Wait Wait 1
bits 1101 (Output r)
 If not, computer shuts off
car
 Example of Sequence Generator
Secure Car Key
 FSM
 Wait until computer Present Next State Output
requests ID (a=1) State a=0 a=1 r

 Transmit ID (in this Wait Wait First 0

case, 1101) First Second Second 1
Second Third Third 1
Third Fourth Fourth 0
Fourth Wait Wait 1

Inputs: a; Outputs: r
Wait/0

1 0
First/1 Second/1 Third/0 Fourth/1
 Example of Sequence Generator
Secure Car Key
Present Next State Output
 FSM State a=0 a=1 r
 5 states : 3 FF’s Wait Wait First 0
 Assign States First Second Second 1

 Implement using DFF Second Third Third 1

Third Fourth Fourth 0
Fourth Wait Wait 1

Present Next State Output

State a = 0 a = 1 r
Inputs: a; Outputs: r
Wait/0 000 000 001 0
1 0 001 010 010 1
010 011 011 1
First/1 Second/1 Third/0 Fourth/1
011 100 100 0
100 000 000 1
 Example of Sequence Generator
Secure Car Key Next State Present
 FSM State a=0 a=1
Output

 Present State y3y2y1 y 3 y2 y1 D3D2D1 D3D2D1 z

 DFF : Q*=D 000 000 001 0
ay3\y2y1 00 01 11 10 001 010 010 1
00 0 0 1 0 010 011 011 1
01 0 d d d
011 100 100 0
11 0 0 1 0
10 0 d d d
100 000 000 1

D3  y2 y1 Unused state : don’t care

ay3\y2y1 00 01 11 10 ay3\y2y1 00 01 11 10 y3\y2y1 00 01 11 10

00 0 1 0 1 00 0 0 0 1 0 0 1 0 1
01 0 d d d 01 0 d d d 1 1 d d d
11 0 1 0 1 11 1 0 0 1
z  y3  y2 y1  y2 y1
10 0 d d d 10 0 d d d

D2  y2 y1  y2 y1 D1  ay3 y2 y1  y2 y1
 Example: Button Press Synchronizer

Button press
bi synchronizer
bo
controller

 Want simple sequential circuit that converts button press to

single cycle duration, regardless of length of time that
button actually pressed
 This is very important!
 All inputs are asynchronous thus must be synchronized for the FSM to
work properly
 Example: Button Press Synchronizer

Button press
bi synchronizer
bo
controller

 State Table & Diagram

Present Next State Output 0
1
0 0
State bi = 0 bi = 1 bo A/0 B/1 1 C/0
1
Wait Wait Got 1 0
A : Wait
Got 1 Wait Still 1 1
B : Got 1
Still 1 Wait Still 1 0 C : Still 1
Example: Button Press Synchronizer
 Assign State and Implement using DFF
Present Next State Output 0
1
0 0
State bi = 0 bi = 1 bo A/0 B/1 1 C/0
1
00 00 01 0
A : 00 (y2y1)
01 00 10 1
B : 01
10 00 10 0 C : 10
11 00 00 0 Unused : 11
y2 y 1 y2 y1 y1
bi 00 01 11 10 bi 00 01 11 10 y2 0 1
0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 1 0 1 1 1 0 0 0 1 0 0

D2  biy2 y1  biy 2 y1 D1  biy2 y1 bo  y2 y1

 Mealy FSMs May Have Fewer States
Inputs: enough (bit) Inputs: enough (bit)
Outputs: d, clear (bit) Outputs: d, clear (bit)
/d=0, clear=1

Moore Init Wait

enough’
Init Wait Mealy
d=0 enough’
enough
clear=1
Disp enough/d=1
d=1

clk clk

Inputs: enough Inputs: enough

State: I W W D I State: I W W I

Outputs: clear Outputs: clear

d d
(a) (b)
 Soda dispenser example: Initialize, wait until enough, dispense
 Moore: 3 states; Mealy: 2 states
 Mealy vs. Moore Tradeoff
 Mealy outputs change mid-cycle if input changes
 Note earlier soda dispenser example
 Mealy had fewer states, but output d not 1 for full cycle
 Represents a type of tradeoff
Inputs: enough (bit) Inputs: enough (bit)
Outputs: d, clear (bit) Outputs: d, clear (bit)
/d=0, clear=1

Moore Init Wait

enough’
Init Wait Mealy
d=0 enough’
enough
clear=1
Disp enough/d=1
d=1

clk clk

Inputs: enough Inputs: enough

State: I W W D I State: I W W I

Outputs: clear Outputs: clear

d d
(a) (b)