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SS07A4041 Digital IC Applications

This document contains questions that appear to be from a supplementary exam on digital integrated circuits applications. The exam contains 8 questions, and students are instructed to answer any 5 questions. The questions cover topics such as how CMOS devices are destroyed, ECL noise margins, TTL output currents, designing logic circuits for prime number detection and comparison, uses of XOR gates for parity checking, differences between latches and flip-flops, switch debouncing using IC, ROM timing parameters, and an application of ROM as a digital attenuator.

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Mahaboob Subahan
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22 views

SS07A4041 Digital IC Applications

This document contains questions that appear to be from a supplementary exam on digital integrated circuits applications. The exam contains 8 questions, and students are instructed to answer any 5 questions. The questions cover topics such as how CMOS devices are destroyed, ECL noise margins, TTL output currents, designing logic circuits for prime number detection and comparison, uses of XOR gates for parity checking, differences between latches and flip-flops, switch debouncing using IC, ROM timing parameters, and an application of ROM as a digital attenuator.

Uploaded by

Mahaboob Subahan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Code: 07A4041

SS
B.Tech III Year I Semester (R07) Supplementary Examinations June 2015
DIGITAL IC APPLICATIONS
(Electronics & Instrumentation Engineering)

Time: 3 hours Max. Marks: 80


Answer any FIVE questions
All questions carry equal marks
*****
1 (a) Explain how a CMOS device is destroyed.
(b) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic diagram
and function table.

2 (a) Mention the DC noise margin levels of ECL 10K family.


(b) Explain sinking current and sourcing current of TTL output. Which of the above parameters decide
the fan-out and how?

3 (a) Design a logic circuit to detect prime number of a 5-bit input?


(b) Write the structural VHDL program for the above design.

4 (a) Realize the following expression using 74x151 IC.

(b) Design a 16-bit comparator using 74×85 Ics.

5 Explain how XOR gates used as parity circuits. Draw the logic diagram, logic symbol of 74X280
(9 input parity checker).

6 Explain how EXOR and EXNOR gates will be used for comparing the data and explain 4 bit
magnitude comparator.

7 (a) Write the differences between a latch and a flip flop.


(b) Design a switch debouncer using 74X109 IC. Explain the operation using timing diagram.

8 (a) Give a brief description of ROM timing parameter.


(b) Explain the application of 8K X 8 ROM as a digital attenuator with the required diagrams.
*****

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