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Synthesis Assignment - 1

The document contains 7 synthesis assignment questions: 1) Realize logic for an RTL module and check timing requirements 2) Identify which statement about controlling input values of logic gates is true 3) Calculate rising and falling propagation delays of a 2-input NAND driving identical gates 4) Calculate minimum clock period for a logic diagram 5) Realize hardware for an RTL module and check for bugs 6) Realize hardware for another RTL module and check for bugs 7) Determine transistor sizes to match propagation delays of an inverter

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Sumanth Varma
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73 views

Synthesis Assignment - 1

The document contains 7 synthesis assignment questions: 1) Realize logic for an RTL module and check timing requirements 2) Identify which statement about controlling input values of logic gates is true 3) Calculate rising and falling propagation delays of a 2-input NAND driving identical gates 4) Calculate minimum clock period for a logic diagram 5) Realize hardware for an RTL module and check for bugs 6) Realize hardware for another RTL module and check for bugs 7) Determine transistor sizes to match propagation delays of an inverter

Uploaded by

Sumanth Varma
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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​Synthesis Assignment -1

1 . Realize the hardware for below rtl and also justify whether the realized logic is correct
in-terms of timing requirement

module block1 ( 
output reg q , 
Input a, b, c, 
Input clk,rst_n) ; 
always @(posedge clk or negedge rst_n) 
if (!rst_n) q <= 0 ; 
else begin: logic 
reg d ; 
d = a & b ; 
q <= d ; 
end 
assign y = q & c ; 
Endmodule 

2 . Which of the following are true?


a) The controlling input value of an AND gate is 0
b) The controlling input value of an AND gate is 1
c) The controlling input value of an OR gate is 0
d) The controlling input value of an OR gate is 1

3. Estimate rising and falling prorogation delays of a 2-input NAND driving “h” identical
gates using Elmore Delay

4. For the figure shown below, calculate the minimum clock period:
5. Realize hardware for below rtl and analyse the realized hardware against the rtl code and
also list out the bugs if any in the rtl

module block_hard (inputA, inputB, inputC, inputD, outputA); 


input inputA, inputB, inputC, inputD;  
output outputA; 
reg outputA; 
always @ (inputA or inputB or inputC or inputD)  
begin 
if (inputA & inputB) 
begin 
if (inputC | ~inputD)  
outputA = 1'b1; 
else 
outputA = 1'bZ; 
end 
end  
endmodule  
  
6. Realize hardware for below rtl and analyse the realized hardware against the rtl code and
also list out the bugs if any in the rtl
 
module block_case (inputA, inputB, select, outputA); 
input inputA, inputB ;  
input [1:0] select;  
output outputA; 
reg outputA; 
always @ (inputA or inputB or select) 
begin 
case (select) 
2'b00: outputA = inputA;  
2'b01: outputA = inputB; 
endcase  
end 
endmodule 
 
7 . ​Determine the transistor sizes of the individual transistors as shown in below figure such
that it has approximately the same tplh and tphl as a inverter with the following sizes: NMOS:
0.5μm/0.25μm and PMOS: 1.5μm/0.25μm
tplh …> Propagation Delay of a gate when signal swings from Low to High
tphl …> Propagation Delay of a gate when signal swings from High to Low
 

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