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Endterm Review HK1 2018-2019 PDF

The end-term review covers design of custom digital logic circuits using finite state machine models and optimization techniques. It also covers instruction set design for processors. Specifically: 1) Students will be tested on designing custom circuits using asynchronous state machines, finite state machines with outputs, and optimizing data paths using register and functional unit sharing. 2) Designing instruction sets including instruction types, formats, addressing modes, and differences between CISC and RISC. 3) Exercises will include all homework problems. The exam allows only 6 pages of notes.

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30 views2 pages

Endterm Review HK1 2018-2019 PDF

The end-term review covers design of custom digital logic circuits using finite state machine models and optimization techniques. It also covers instruction set design for processors. Specifically: 1) Students will be tested on designing custom circuits using asynchronous state machines, finite state machines with outputs, and optimizing data paths using register and functional unit sharing. 2) Designing instruction sets including instruction types, formats, addressing modes, and differences between CISC and RISC. 3) Exercises will include all homework problems. The exam allows only 6 pages of notes.

Uploaded by

Trần Thảo Nguyên
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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END-TERM REVIEW

DIGITAL LOGIC DESIGN (CE118)

The review content is in Chapter 3 (part 1 & 2) and chapter 4. Main content as follow:

Chapter 3 slide (<-> Chapter 8 textbook)


Part 1: Design a Custom-design (ASIC) by ASM and FSMD model
• ASM chart: State-based (Moore) chart, Input-based (Mealy) chart
• FSMD or State-action table for the design
• Decide necessary components in Data path
• Derive necessary equations (Flip-lop inputs equations, outputs equations) of Control Unit
• Draw logic schematic (including Data path and Control Unit)
* Students know how to design the Data path and Control Unit for a problem/specific purpose.
Part 2: Design optimization (Data path optimization)
• Register sharing (Variable merging)
- Left-edge algorithm
- Graph-partitioning algorithm
• Functional-unit sharing (Operator merging):
- Know how to design a circuit for an operator (simple functional units/library
components)
- Know how to design a shared circuit to combine many operators (complex
functional units/library components)

Chapter 4 slide (<-> Chapter 9 textbook)


• Design the instruction set for a given specific processor. Understand the instruction set
in terms of:
- Instruction type
- Instruction format
+ Three-address instructions
+ Two-address instructions
+ One-address instructions and ACC
- Addressing mode
+ Immediate, Direct/ Indirect, Relative, Indexed

• Difference between the Instruction set of CISC and RISC


• Understand ASM and Data path of the CISC and RISC processor

---------------------------

Exercises: all the exercises and problems you have done in the homeworks.

In the exam: Students are only allowed to use 3 papers A4 (correspondingly 6 pages A4).

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