EE M216A .:.

Fall 2010
Lecture 13

Logic Synthesis

Prof. Dejan Marković

[email protected]

Design Challenges: An Industrial View

TIMING AREA POWER

RUNTIME DESIGNER MEMORY

TIME TO
MARKET

Š Correct functionality requirements

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1
Logic Synthesis
Š Constraining your design for logic synthesis

Š Design constraints
– Environmental
E i t l constraints
t i t
● Driver
● Load (max fanout)
– Define clocks
● Cycle time
● Uncertainty
– Optimization constraints
● In and out delay / max transition
● Max area etc.
– (Timing exceptions)

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Logic Synthesis is Timing‐Driven

Š This is a generic design used during synthesis
– Internal data‐path delay (cycle (and hold) time analysis)
– Relationship to in and out paths
– Timing
Ti i exceptions
ti

TOP

A D Q D Q Z
FF2 FF3
QB QB
Clk

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2
Timing Constraints
Š Clock period: set by define_clock
Š Input delay: arrival of an external path with respect to a Clk edge
Š Output delay: timing path from an output port to a register input
of an external block

Š Input and output delays budget timing for surrounding logic in

general case when the in/out ports are not registered
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Understanding Timing Constraints

Š Three important constraints (clock, input, output)
– Blue box = current_design (to be retimed)

(input) (internal) (output)

logic logic logic logic logic

Clk

“set_input_delay” “set_output_delay”
(affects input logic) (affects output logic)
“create_clock”
(affects internal logic)
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3
Environment: Drivers, Load…
Š To simulate realistic inputs, we can set the driving cell using the
external_driver command, to be any cell in the library
– This ensures that the input has a finite slew rate

Š The load capacitance can be set on the output ports using the
external_pin_cap command

Š By default the Encounter RTL Compiler only tries to meet the

timing constraints without optimizing power

Š If the
h max_dynamic_power
d i attribute
ib is
i set to some value,
l the
h
tool tries to meet the timing specs while also optimizing for
power in the process

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Example: Automated Adder Synthesis

Š Copy the following files to your work directory
/usr/public.2/ee216a/cadence/SOC62/SynLib.v
/usr/public.2/ee216a/cadence/SOC62/adder.v
/ / bli 2/ 216 / d
/usr/public.2/ee216a/cadence/SOC62/adder.tcl
/SOC62/ dd t l
Š The top level synthesis script adder.tcl reads in the HDL file, sets
timing, load and power constraints, and runs synthesis
Š To run RTL synthesis type the following command
> rc –files adder.tcl –gui
Š The GUI window will show detailed architecture (gate level). Use
report power, report area, report timing commands in the rc
command window to get Power, Area and Delay numbers

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Setup Example: Adder.tcl (1/2)
set_attribute library /w/apps/apps.16/cadence/gsclib090_v2.9/timing/typical.lib
set_attribute hdl_language v2001 Define lib
read_hdl adder.v
Read HDL
read_hdl SynLib.v
elaborate adder Elaborate
dc::current_design adder
dc::set_time_unit ‐picoseconds
dc::set_load_unit ‐femtofarads
define_clock ‐name clk ‐period 1000 ‐design /designs/adder
{/designs/adder/ports_in/clk}
dc::set_input_delay 20 ‐clock clk [all_inputs] Set timing
dc::set output delay 100 ‐clock
dc::set_output_delay clock clk [all_outputs]
[all outputs]
set_attribute external_driver [find [find / ‐libcell DFFX1] ‐libpin D]
{/designs/adder/ports_in/*} Set
set_attribute external_pin_cap 26.5488 {/designs/adder/ports_out/*} env.
set_attribute lp_power_unit mW /
set_attribute max_dynamic_power 0.5 /designs/adder Opt.

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Setup Example: Adder.tcl (2/2)

synthesize ‐to_mapped ‐effort high Synthesis
report area > adder_area.rpt
report power > adder_power.rpt
Reports
report timing > adder_timing.rpt
report clocks > adder
adder_clocks.rpt
clocks rpt
write_encounter design adder ‐basename adder ‐lef [format "%s %s %s"
/usr/public.2/ee216a/cadence/SOC62/gpdk090_9lm.lef
/w/apps/apps.16/cadence/gsclib090_v2.9/lef/gsclib090_tech.lef
/w/apps/apps.16/cadence/gsclib090_v2.9/lef/gsclib090_macro.lef]

Š How does synthesis work?

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5
Example Clock, In and Out Delay [Synopsys]
Š Define clock, input and output delay
create_clock –name “Clk” –period $Tclk
set_input_delay 0.5
set_output_delay [expr $Tclk – 0.5 + $wire_margin] ;# wire_margin = 0.2

Š Work with expressions and variables

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Adder.tcl
Š The adder.tcl file sets constraints & optimization parameters

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Pre‐ and Post‐Layout Clock

ideal clock

Courtesy:
Synopsys latency uncertainty transition
[ jitter 0.1 + skew 0.4 ]
pre‐layout
pre layout post‐layout
post layout
create_clock ‐p 30 ‐n MCLK Clk create_clock ‐p 30 ‐n MCLK Clk
set_clock_uncertainty 0.5 MCLK set_clock_uncertainty 0.1 MCLK
set_clock_transition 0.25 MCLK
set_clock_latency ‐source 4 MCLK set_clock_latency ‐source 4 MCLK
set_clock_latency 2 MCLK set_propagated_clock MCLK
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Synthesis Results: Fast Adder

Š Adder synthesized to meet
timing constraint of 550 ps
Š Input is registered from a FF
– Clk‐Q
Clk Q delay = 157 ps
– Setup time = 82 ps
Š Effective adder delay = 311 ps
Š Timing constraints are
stringent, tool synthesizes a
carry look ahead type of adder
Š S h i reports
Synthesis
– Area = 1035 µm2
– Energy (active) = 0.2145 fJ
– Power (leak) = 0.005 mW

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Synthesis Results: Slow Adder
Š Adder delay = 757 ps
Š Structure is somewhat like
carry ripple topology
Š Area = 548 µm2 (half of
previous)
Š Energy (active) = 0.13 fJ
– Nearly ½ of previous design
– Expected since VDD was the
same, Eactive depends only on
Csw, which
hi h was h
halved
l d with
ith
the area being halved…
Š Power (leak) = 0.002 mW
– Also reduced due to
reduced area
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Synthesis Results
Š Energy‐delay tradeoff plot obtained from synthesis
– Keep timing constraint, move down the energy axis (left plot)
– Resulting energy‐area should be below reference curve (right
plot)
26 26
per Opertaion (fJ)

per Opertaion (fJ)

(311,24) 24
24 (1035,24)

22 22

20 20

18 18
Energy p

Energy p

(361,16) (813,16)
16 (757,15) 16 (548,15)

14 14
200 400 600 800 400 600 800 1000 1200
Delay (ps) Area (µ m )
2

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High‐Level Design Issues
Š You may think design is a straightforward
logical process
– Start with the idea of what you need to build
– And then build it
Š Real design is not like that
– Think you have an idea of what to build
Specification
– Through the design process you figure out
what you really want to build
– Need to validate idea early in the process
Š What you build depends on the Implementation

i l
implementation i capabilities
bili i and
d constraints
i
– Implementation issues will change the
Verification
specification
Need a language that helps with the real
(interactive) design process
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Hardware Description Languages

Š Need a description level up from logic gates

Š Work at the level of functional blocks, not logic gates

– Complexity of the functional blocks is up to the designer
– A functional unit could be an ALU, or could be a microprocessor

Š The description consists of functional blocks and their

interconnections
– Describe functional block (not predefined)
– Support hierarchical description (function block nesting)

Š To make sure the specification is correct, make it “executable”

– Run the functional specification and check what it does

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Hardware Description Languages
Š A hardware description language (HDL) translates the
specification of a hardware device into a software medium; This
software medium can be
– Verified via simulation
– Translated into an optimized, technology‐specific, gate‐level
implementation

Š Register Transfer Level (RTL) synthesis explicitly defines register

boundaries and the combinational logic between them:
– Data
D t fl
flow, control
t l fl
flow, and
d machine
hi states
t t are explicitly
li itl
defined by the coding style that is used

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Hardware Description Languages (Examples)

Š There are many different systems for modeling and simulating
hardware
– Verilog IEEE Standard
– VHDL
– L‐language, M‐language (Mentor)
– DECSIM (DEC)
– Aida (IBM / HaL)
– and many others

Š The two most standard languages: Verilog & VHDL

– For this class we will be using Verilog

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Verilog from 20,000 Feet
Š Verilog descriptions look like programs:
C / Pascal Verilog
Procedures/Functions Modules
Procedure parameters Ports
Variables Wires / Regs
Courtesy:
Synopsys
Š Block structure is a key principle
– Use hierarchy/modularity to manage complexity
Š But they aren’t ‘normal’ programs
– Module evaluation is concurrent
– Model is really that of communicating blocks

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Verilog (or any HDL) View of the World

Š A design consists of a set of
communicating modules
Š There are graphic‐input tools
for Verilogg
– Come to EE216B b
Ctrl Memory
– Matlab/Simulink Æ RTL c
Š We will use the text method
– EEM216A bus d
a
Š Basic philosophy
– Label the wires, and pass
them
h b
between modules
d l as Datapath
you would parameters in
function calls
– Wires are I/O nets for
modules

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Example Verilog
ModuleName InstanceName (wires);
clkgen
module system;
wire [7:0] bus_v1, const_s1;
wire [2:0] regSpec_s1, regSpecA_s1, patternsource
Phi2 Phi1
regSpecB_s1;
S B 1
wire [1:0] opcode_s1;
wire Phi1, Phi2, writeReg_s1,
ReadReg_s1,nextVector_s1
clkgen clkgen(Phi1, Phi2);
datapath datapath(Phi1, Phi2, regSpec_s1,
bus_v1, writeReg_s1, readReg_s1); controller
controller controller1(Phi1, Phi2, regSpec_s1,

read

writ

regS
bus_v1, const_s1, writeReg_s1, readReg_s1,
opcode_s1, regSpecA_s1, regSpecB_s1,

bu

dReg

teReg

Spec
us
nextVector_s1);
patternsource patternsource(Phi1,
Phi2,nextVector_s1, opcode_s1,
regSpecA_s1, regSpecB_s1, const_s1);

In this example the instance name and the module datapath

name are the same, except for controller1.

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Ways to Describe A Function

Š Structural
– Consists only of module calls

Š Declarative
– Concurrently executed combinational logic

Š Procedural
– Sequentially executed program
● A state machine (with storage)
● Or combinational logic

Š Functional
– Function/task calls

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Structural Description
ModuleName InstanceName (wires);
Š Maps a physical structure
module system; into Verilog
wire [7:0] bus_v1, const_s1;
wire [2:0] regSpec_s1, regSpecA_s1, – Example is one shown
regSpecB_s1;
S B 1 earlier
li ((repeated
t dhhere))
wire [1:0] opcode_s1;
wire Phi1, Phi2, writeReg_s1, Š Possible hierarchically
ReadReg_s1,nextVector_s1
clkgen clkgen(Phi1, Phi2); – List of functions
datapath datapath(Phi1, Phi2, regSpec_s1, – List of sub‐functions
bus_v1, writeReg_s1, readReg_s1);
controller controller1(Phi1, Phi2, regSpec_s1, – List of gates
bus_v1, const_s1, writeReg_s1, readReg_s1,
opcode_s1, regSpecA_s1, regSpecB_s1, – List of transistors
nextVector_s1);
patternsource patternsource(Phi1,
Š Typically don’t need to go
Phi2,nextVector_s1, opcode_s1, below a gate level list
regSpecA_s1, regSpecB_s1, const_s1);
– Standard cells
Compose a module out of module cells. Specify
wiring.

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Declarative Statements
Provide the logical relations between inputs and outputs
Š Assign outputs to be some function of the inputs (continuously)
– Key word is assign
Š Models a piece of combinational logic C
Š Uses a C‐like expression syntax L
Š Denoted by keyword assign
Examples (all execute in parallel):
assign nor = ~(b | c);
assign a = x & y, o = x | y;
assign sum[4:0] = a[3:0] + b[3:0];
assign out = (Sel) ? in1: in2; //conditional
Outputs are wires, and can be a single bit or multiple bits.
Š It is good practice to declare all variables even though Verilog
allows undeclared single bit wires

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Declarative Order of Execution
Š Don’t assume any particular order.
– Each statement occurs concurrently.
assign x = aaa;
assign aaa = bbb;
– Unlike C, the order of the above statements does not matter

Š Internally, however, declarative statements are still executed in

a particular order
– Verilog has an internal event linked list
– But, there is no guarantee of that order
assign out = aaa;
assign out = bbb;
– This yields a warning and is not allowed

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Procedural Statements
Š Procedural statements = sequential order
Š Keyword always
– Provides functionality of a tiny program that executes
q y
sequentially
Š Inside an always block, standard control flow statements:
if (<conditional>) then <statements> else <statements>;
case (<var>) <value>: <statements>; … default: <statements>
Š Note: Case statements are actually prioritized
– The 2nd case entry can’t happen unless the 1st doesn’t match
– May not be what the actual hardware implies – especially when
cases are mutually exclusive
exclusive.
– Need additional directives (parallel‐case) to indicate this
Š Statements can be compound
– Use begin and end to form blocks

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Procedural Statements (Cont.)
Š Example
always @ (Activation List…stuff we still need to talk about)
begin
// more than 1 statement allowed inside here
if (x==y) then
out= in1
else
out = in2;
end

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always Block Issues

Two issues with always blocks…

Š Issue #1: Unset outputs

–AAre allll outputs
t t given
i a value
l with
ith an explicit
li it assignment
i t
statement at the end of the block?
– If not, then it is “unset”
– If the output is always set, then the always block is no different
from a combinational logic

Š Issue #2: Activation list

– Determines when to execute the always block

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Unset Outputs
Š Occur when an output is not set on all the paths in the code
Š Example: always @ (Activation List…stuff we need to talk about)
begin
// more than 1 statement allowed inside here
if (x==y) then
out= in1
// no else statement. So, if x!= y then out is unset.
end
– In Verilog, this creates storage
● The value of the output remains the previous value
● In synthesized result, it appears as an explicit FF or latch
Š Is this storage what we want?
– Careful to not build storage elements when you don’t
don t intend to
Š The outputs of always blocks might act as storage elements
– Left‐hand sides of expressions in always blocks must be
declared as registers (regs)
● That does not mean the synthesized result contains registers
● If output is set on all paths, there is no storage

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Unset Outputs

Did he want latch

always or combinational logic?
begin
g
Data_Out = In_B;
if (Enable)
begin
Data_Out = In_A; In_B 0
end
end Data_Out

In A
In_A 1

Courtesy:
Synopsys
Enable MUX

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 Unset Outputs

always @(Enable or In_A or In_B) Courtesy:

begin Synopsys

if (Enable)
(E bl )
begin In_A Out_1
Out_1 = In_A; LATCH
end Enable
else
begin
Out_2 = In_B;
end In_B Out_2
LATCH
end

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Intentionally Creating Storage in Verilog

Š To make a simple latch in Verilog is easy
– Just make the output of an always block not get set when you
want to hold its value
Š Example:
reg myout; //a latch
always @ (stuff we still need to talk about)
if (Enable) then
myout = in;
– When Enable is high, the output myout is updated
– When Enable is low low, myout will hold its last value
value.
– This is like the simple pass transistor latch
Š In this example, myout would need to be declared a register,
because it is the LHS of an expression in an always block

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Is This an Infinite Loop?
Š Example 1

assign nor = ~(b | c);

Š Example 2

always
nor = ~(b | c);

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Activation List
Š The last tricky part about the always block…

Š Activation List
– TTells
ll th
the simulator
i l t when
h tto run thi
this bl
blockk
– Allows the user to specify when to run the block and makes the
simulator more efficient
● If not sensitized to every input, you get a storage element
– But also enables subtle errors to enter into the design

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Two Forms of Activation List in Verilog
Š @(signalName1 or signalName2 or …)
– Evaluate this block when any of the named signals change
(either positive or negative change)

Š @(posedge signalName);or @(negedge signalName);

– Makes an edge triggered flop
– Evaluates only on one edge of a signal
– Can have @(posedge signal1, posedge signal2)
● Implied OR (not AND) because edges are singular events
● Not
N used d in
i this
hi class
l b because diffi
difficult
l to map to an actuall gate

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Activation Lists
Š Example:
always @ (Enable or In) // latch
if (Enable) then
out=In;
always @ (x or y or in1 or in2) //combinational logic
begin
if (x==y) then
out= in1
else
out = in2;
end //same as out = (x==y) ? in1 : in2;

Š To represent
p Combinational Logic
g
– The activation lists must contain everything on the RHS of the
expressions (and both side of conditionals). Why?
Š Beware, if an always block has no activation list (or # delay
statements), then the simulator goes into an infinite loop
Š always@* syntax

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Activation Errors: Examples
always @(phi) always @(phi) always @(phi or in)
outA =in; if(phi) outB = in; if(phi) outC = in;

phi

in

outA

outB

outC

Š What would synthesis results look like?

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Procedural Order of Execution

Š Be careful of the sequential nature! (C‐like behavior)
Š Case 1
always @(posedge clock) begin
q2=q1;
q1=q0;
1 0
end
Š Case 2
always @(posedge clock) begin
q1=q0;
q2=q1;
end
Š Case 3 – Which one is this case more similar to?
always @(posedge clock) begin
q1=q0;
end
always @(posedge clock) begin
q2=q1;
end

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Non‐Blocked Assignment
Š A feature of Verilog helps by eliminating the order of
evaluation
– Instead of “=“ ; known as a blocking assignment
● Blocks future action until RHS is updated
– Use “<=“; known as non‐blocking assignment
● All LHS are changed first before the RHS is updated
always @ (posedge clock)
begin
a[0] <= inp;
a[1] <= a[0];
a[2]
[2] <= a[1];
[1]
a[3] <= a[2];
end
Š The above is equivalent to a[3:0]={a[2:0],inp};
Š If we had used “=“ instead of “<=“, then a = 4{inp};
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Parallel Case Definition

Š A case statement is called parallel case if its case items do not
overlap:
– If synthesis determines that the case statement is parallel case
then a multiplexer or equivalent logic will be synthesized
● Otherwise priority‐checking logic will be synthesized

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Parallel Case Example
Š No priority logic needed

case (Sel)
2'b00 : D_Out = A;
2'b01 : D_Out = B;
2'b10 : D_Out = C;
2'b11 : D_Out = D;
endcase

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Initial Block
Š This is another type of procedural block
– Does not need an activation list
– It is run just once, when the simulation starts

Š Used to do extra stuff at the very start of simulation

– Initialize simulation environment
– Initialize design
● This is usually only used in the first pass of writing a design
● Beware, real hardware does not have initial blocks
– Allows
All ttesting
ti off a d
design
i ((outside
t id off th
the d
design
i module)
d l )

Š Best to use initial blocks only for non‐hardware statements

(like $display)

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Summary of Verilog Variables
Š There are two types of “physical” variables in Verilog:
– Wires (all outputs of assign statements must be wires)
– Regs (all outputs of always blocks must be regs)
Š Both
B th variables
i bl can be
b used
d as inputs
i t anywhere
h
– Can use regs or wires as inputs (RHS) to assign statements
assign bus = LatchOutput + ImmediateValue
● Bus must be a wire, but LatchOutput can be a reg

– Can use regs or wires as inputs (RHS) in always blocks

always @ (in or clk)
if (clk) out = in
● in can be a wire, out must be a reg

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Summary of Verilog Variables (Cont.)

Š Module outputs can be either regs or wires
module div_ctrl(ctl1, ctl2, dp1, clock, reset, start);
output ctl1, ctl2;
input dp1
dp1, clock
clock, reset
reset, start;

Š Integer and real do not map into hardware

– Useful for initial functional description but not for
implementation

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Delays in Verilog
Š Verilog simulated time is in “units” or “ticks”
– Simulated time unrelated to the wall‐clock to run the simulator
– Simulated time models the time in the modeled machine
● When
Wh ththe computer
t completes
l t with
ith allll the
th “events”
“ t ” that
th t occur att th
the
current simulated time
● The computer increases time until another signal is scheduled to
change values
Š User must specify delay values explicitly to Verilog
– # delayAmount
● When the simulator sees this symbol, it stops “evaluating”, and pause
delayAmount of simulated time (# of ticks).
● Delays are often used to model the delay in functional units
● Can be tricky to use properly
– We will design our logic to have zero (or unit) delay
● The standard cell library we use can annotate delay information

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Synthesis | 4747

RTL Subset
Š HDLs were designed for simulation
Š Subset of the language is supported for Synthesis
Š Unsupported Verilog language constructs:
– Delays
D l
– “initial” blocks
– $display
– Tool Specific
Š Organize synthesis and simulation specific code into separate
files
– RTL
– Test bench

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24
Verilog Summary
Š An HDL provides a means for the user to specify a design at a
higher level than just gates
– This lecture addresses mostly form and not content
● How to represent combinational logic and state machines
– We can now use this tool to specify any machine with state
Š A good question to ask is
– “What should my code look like?”
– “Are there certain styles of hardware that are easier to
understand / build / test?”
– Gets back to the question of abstractions, and is really asking
whether there are some hardware abstractions that work well
Š The answer is briefly introduced in the examples above
– Partitioning of the problem into
● Finite State Machines
● Data flows

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Synthesis | 4949

Now What?
Š Synthesis = Translation + Logic Optimization + Mapping
residue = 16’h0000;
if (high_bits == 2’b10)
residue = state_table[index]; Translate (read)
else
state_table[index] = 16’h0000;
HDL Source Optimize + Map
(compile)

Courtesy:
Synopsys Generic Boolean
(GTECH)

Target Technology
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25
Synthesis Design Flow
Spec
Select Code RTL
Architecture
Floorplan
RTL Code Check
T tb h
Testbench RTL CWLM Constraints

Synthesis Lib
Logic Synthesis
Test (Scan/JTAG) DW
Power Reduction
RTL Verification Formal Verification Datapath Synthesis

ATPG Gate‐level
netlist/db
Placement
Gate‐level Verification Static Timing Info
Analysis
Courtesy:
Synopsys GDSII Physical Design

EEM216A .:. Fall 2010 Lecture 13: D. Markovic

Logic / Slide
Synthesis | 5151

Simplified View: EEM216A Flow

Today

Next few
lectures

EEM216A .:. Fall 2010 Lecture 13: D. Markovic

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Synthesis | 5252

26
The Importance of HDL Coding Styles

Poor
Better
Start Courtesy:
Start
Point Synopsys
Point
B
Best
Start
Point
Goal

Š Different coding styles that are functionally equivalent may

synthesize into hardware that have different timing and area
Š Synthesis engineers cannot rely solely on the synthesis tool to
"fix" a poorly coded design
Š Alternative coding styles should be explored, so that the
synthesis algorithms will have the best possible starting point

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Synthesis | 5353

Synthesis Is Constraint‐Driven

Area

Large •

•
•
Small • • •

Short Long Delay

Courtesy: Synopsys
Š You set the goals (through constraints)
Š Synthesis tool optimizes the design to meet your goals

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27
Synthesis Summary
Š Synthesis tools are like compilers
– Allow the user to work at a higher level
– Show you what the details look like

Š Use tools to understand the parts that need extra work

– Optimize the parts that don’t meet the constraints
– Don’t improve what is not broken

Š Tools leverage your creativity

– Not a substitute for thinking
– Need
N d tot competet with
ith others
th using
i th
the same ttools!
l!

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Logic / Slide
Synthesis | 5555

Cadence Manuals / Tips Etc.

Š Online resources:
http://sourcelink.cadence.com

Š Sign up for an account

– Disclaimer (from Cadence)
● Reference key for UCLA is: 606‐ucla1108
● Only university staff, faculty and students may use this reference key
● You must sign up using a university domain email address

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