Subject:

Mark VI panel layout

Panel- Page
hardware 2.1
 Subject:
Mark VI panel layout
Panel- Page
hardware 2.2

Intentionally left blank

 Subject:
Mark VI panel layout Panel- Page
hardware 2.3

– Introduction 2.4
– Mark VI simplex 2.5
– Mark VI TMR 2.7
– Control Module 2.10
– Control and Interface module 2.11
– Protection Module 2.12
– The Main Controller 2.13
– IONet 2.14
– Voting 2.15
– I/O Hardware 2.18
– Digital I/O 2.20
– Analog I/O 2.21
– Thermocouples and RTD’s 2.22
– Servo’s 2.22
– Speedmeasurement and Trips 2.24
– Trip Solenoid en Light off protection 2.25
– Vibrations 2.26
– Generator 2.27
– Power Supply 2.28
 Subject:
Introduction Panel- Page
hardware 2.4

The Mark VI TMR and or simplex are typically part of a redundant network. Typical part are:
Network switches, servers and de MKVI itself. If the mkVI is simplex then there is usually also not a
redundant network.
An example of a full blown system is in Figure 2.1
All Control modules are directly connected to the UDH (Unit Data Highway).

Figuur 2.1 Mark VI systeem

The heart of the control system is the control module, which is available in either a 13 or 21 slot
standard VME board rack. Inputs are received by the control module through terminal boards with either
barrier or box type terminal blocks and passive signal conditioning.

In addition to the I/O boards, the control module contains an internal communication board, a
main processor board. Each board takes one slot.

I/O data is transmitted on the VME backplane between the I/O boards and the VCMI board
located in slot 1. The VCMI is used for internal communications between:

. I/O boards that are contained within its board rack

. I/O boards that may be contained in expansion I/O racks, called interface modules
. I/O in backup <P> protection modules
. I/O in other control modules used in triple redundant control configurations
. The main processor board

The main processor board executes the bulk of the application software at 10, 20, or 40ms
depending on the requirements of the application. Since most applications require that specific parts of
the control run at faster rates (servo loops, pyrometers) the distributed processor system between the
main processor and the dedicated I/O processors is very important for optimum system performance. A
QNX® operating system is used for real-time applications with multitasking, priority-driven pre-emptive
scheduling, and fast context switching.

.
 Subject:
Mark VI Simplex Panel- Page
hardware 2.5

The control module is used for control, protection, and monitoring functions, but some
applications require backup protection. For example, backup emergency overspeed protection is always
provided for turbines that do not have a mechanical overspeed bolt, and backup synch check protection
is commonly provided for generator drives. In these applications, the IONet is extended to a backup
protection module that is available in Simplex and triple redundant forms. The triple redundant version
contains three independent sections (power supply, processor, I/O) that can be replaced while the
turbine is running. IONet is used to access diagnostic data or for cross-tripping between the control
module and the protection module, but it is not required for tripping.

In Simplex applications, the Control Module contains the processor card (UCV_), the
communications card (VCMI), and the I/O cards. The I/O cards communicate with the VCMI card which
communicates with the UCV_ card. An Ethernet port is located on the VCMI which is used for an IONET
interface with an expansion I/O Module (if required) or a Protection Module which is used for emergency
overspeed (EOS) protection and/or synch check protection. Note that most retrofit applications do not
need the Protection Module for EOS because the turbine already has a mechanical overspeed bolt.

Figure 2.2 Mark VI Simplex

 Subject:
Mark VI Simplex Panel- Page
hardware 2.6

Communication of data between the control module and other modules within the Mark VI control
system is performed on the IONet. The VCMI board in the control module is the IONet busmaster
communicating on an Ethernet 10-Base-2 network to slave stations. A unique poling type protocol
Asynchronous Drives Language (ADL) is used to make the IONet more deterministic than traditional
Ethernet LANs.

Simplex System with

V U Local I/O
C C I/O
M V Boards
I X
UCVX is Controller
VCMI is Bus Master
I/O are VME Boards

R R1
V U V
Simplex System with
C C I/O C I/O
M V Boards M Local & Remote I/O
Boards
I X I

IONet

R R1
V U V
C C C I/O Simplex System with
M V M Boards Multiple IONets &
I X I Remote I/O

IONet
R2
V
C I/O
M Boards
I

IONet

Figure 2.3 Mark VI Simplex I/O

 Subject:
Mark VI TMR Panel- Page
hardware 2.7

A triple redundant Mark VI control has three (3) sets of separate and independent Control
Modules. Each module has its own processor, communication card, I/O cards and power supply. A
single point failure in any Control Module will not cause a misoperation. Data from each Control
Module’s I/O cards is read by its communication card (VCMI) and transmitted to the VCMI cards in the
other two (2) Control Modules. Inputs are voted in software in a scheme called Software Implemented
Fault Tolerance (SIFT).Each VCMI card then “votes” the data from three (3) sets of I/O by selecting the
logically voted 2/3 data for logic points and the median value for analog data. The voted data is then
transmitted from the VCMI card to the processor card to be used by the application software. The term
“frame rate” means the time it takes to read all inputs, exchange the data between the three (3) Control
Module, vote the data, execute the application software, and write outputs to the control valves. Frame
rates are application specific depending on the system dynamics of each turbine. Also, some parts of the
control may run faster such as the control valve regulators. A typical frame rate is 40ms, and the servos
are regulated at 5ms.
All hardware & software which is required for the critical control functions and trip functions is
triple redundant as well as I/O and sequencing to perform a normal shutdown sequence. Non-critical
functions are implemented with hardware in one (1) of the three (3) Control Modules. Sensors for critical
functions may be implemented as triple, dual, or single devices as required. Most sensors are
connecting to one (1) TB point on the Mark VI and then internally paralleled to the three (3) Control
Modules. Exceptions are speed, thermocouple and RTD inputs.
Other forms of output voting are available including a median select of 4-20 mA outputs for
process control and 0-200 mA outputs for positioners. Sensor interface for TMR controls can be either
single, dual, triple redundant, or combinations of redundancy levels. The TMR architecture supports
riding through a single point failure in the electronics and repair of the defective board or module while
the process is running. Adding sensor redundancy increases the fault tolerance of the overall system.
Another TMR feature is the ability to distinguish between field sensor faults and internal electronics
faults. Diagnostics continuously monitor the three sets of input electronics and alarm any discrepancies
between them as an internal fault versus a sensor fault. In addition, all three main processors continue to
execute the correct voted input data.

Figure 2.4 Mark VI TMR

 Subject:
Mark VI TMR Panel- Page
hardware 2.8

Remote I/O applications are implemented by separating the processors and I/O cards into
separate card racks and cabinets. The I/O cards are mounted in Interface Modules with VCMIH1 cards
for communication to the VCMIH2 communication cards which are mounted in Control Modules with the
UCV_ processor cards. The cabinet which contains the Control Modules is called the Control Cabinet
which is mounted in an air-conditioned environment, and the Interface Modules are mounted in the
Termination Cabinet which can be mounted at the turbine and generator. One (1) Control Cabinet can
support interface with two (2) Termination Cabinets.
Communication between the Control Module and the Interface Module is performed on an
Ethernet 10Base2 (ThinNet Ethernet - Coax) network called IONET. Maximum distance between the
Control Module and the Interface Module is 185m (607’). See figure 2.5.

Figure 2.5 Mark VI TMR with Interface module

 Subject:
Mark VI TMR Panel- Page
hardware 2.9

Typical examples on how I/O can be configured. See figure 2.6

R S T
TMR System with
V U V U V U Local I/O
C C I/O C C I/O C C I/O
M V Boards M V Boards M V Boards UCVX is Controller
I X I X I X
VCMI is Bus Master
I/O are VME Boards
IONet - R Termination Boards
IONet - S not shown
IONet - T

R S T TMR System with

V U V U V U Remote I/O,
C C C C C C Termination Boards
M V M V M V not shown
I X I X I X

IONet - R
IONet - S
IONet - T

R1 S1 T1
V V V
C I/O C I/O C I/O
IONet Supports
M Boards M Boards M Boards Multiple Remote
I I I I/O Racks

Figure 2.7 Mark VI TMR I/O

 Subject:
Control Module Panel- Page
hardware 2.10

The control module is available as an integrated control and I/O module, or as a stand-alone
control module only. The integrated control and I/O rack can be either a 21-slot or 13-slot VME size. The
13-slot rack can accommodate all the boards for control of a small turbine. The backplane has P1 and
P2 connectors for the VME boards. The P1 connectors communicate data across the backplane, and the
P2
connectors communicate data between the board and 37-pin J3 and J4 connectors located
directly beneath each board. Cables run from the J3 and J4 connectors to the terminal boards.

There can be one control module (simplex) or three triple modular redundant (TMR) control
modules. Each of these configurations supports remote I/O over IONet. The simplex control modules
can be configured to support up to three independent parallel IONet systems for higher I/O throughput.
Multiple communication boards may be used in a control module to increase the IONet throughput. The
following figure shows a 21-slot rack with a three-IONet VCMI communication board, and a UCVx
controller. The UCVx must go in slot 2. The remaining slots are filled with I/O boards.

Figure 2.8 Control Module & I/O

 Subject:
Control and Interface Module Panel- Page
hardware 2.11

Figure 2.9 Control Module

Figure 2.10 Interface Module

 Subject:
Protection Module Panel- Page
hardware 2.12

The Turbine Protection Module (VPRO) and associated terminal boards (TPRO and TREG)
provide an independent emergency overspeed protection for turbines that do not have a mechanical
overspeed bolt. The protection module is separate from the turbine control and consists of triple
redundant VPRO boards, each with their own on-board power supply, as shown in the following figure.
VPRO controls the trip solenoids through relay voting circuits on the TREG, TREL, and TRES boards.
The TPRO terminal board provides independent speed pickups to each VPRO, which processes
them at high speed. This high speed reduces the maximum time delay to calculate a trip and signal the
ETR relay driver to 20 ms. In addition to calculating speed, VPRO calculates acceleration which is
another input to the overspeed logic.

TPRO fans out generator and line voltage inputs to each VPRO where an independent generator
synchronization check is made. Until VPRO closes the K25Apermissive relay on TTUR, generator
synchronization cannot occur. For gas turbine applications, inputs from temperature sensors are brought
into the module for exhaust over temperature protection.

The VPRO boards do not communicate over the VME backplane. Failures on TREG are detected
by VPRO and fed back to the control system over the IONet. EachVPRO has an IONet communication
port equivalent to that of the VCMI.

VPRO Card X VPRO Card Y VPRO Card Z

x x x x x x x x x x x
x x

I RUN I RUN I RUN

IONet R FAIL FAIL O FAIL
O O
IONet S N STAT N STAT N STAT
E 8 X E 8 X E 8 X
IONet T T 4 Y T 4 Y T 4 Y
T 2 Z T 2 Z T 2 Z
R 1 R 1 R 1
C C C
S S S
E E E
Ground R J R J R J
6 J 6 6
J P5 P5 J P5
COM 5 COM COM
5 5
P28A P28A P28A
P28B P28B P28B
E E E
T T T
To TPRO H H H
R R R
x J J J J J J
To TPRO P P P x
3 4 A 3 4 A 3 4 A
P P P
R O R O R O
A W A W A W
F N L E F N L E F N L E
To TREG VPRO R VPRO R VPRO R
x x x x x x x x x x x

To TREG

Power In
125 Vdc

Figure 2.11 Protection Module

 Subject:
The Main Controller Panel- Page
hardware 2.13

The controller is a single-slot VME board, housing a high-speed processor, DRAM, flash memory,
cache, an Ethernet port, and two serial RS-232C ports. It must always be inserted in slot 2 of an I/O rack
designed to accommodate it. These racks can be identified by the fact that there are no J3 and J4
connectors under slot 2. The controller provides communication with the UDH through the Ethernet port,
and supports a low-level diagnostic monitor on the COM1 serial port. The base software includes
appropriate portions of the existing Turbine Block Library of control functions for the steam, gas, and
Land-Marine aero-derivative (LM) products. The controller can run its program at up to 100 Hz, (10 ms
frame rate), depending on the size of the system configuration.

External data is transferred to/from the controller over the VME bus by the VCMI communication
board. In a simplex system, the data consists of the process I/O from the I/O boards, and in a TMR
system, it consists of voted I/O.

Figure 2.12 UCVx Card

 Subject:
Internal Communication IONet Panel- Page
hardware 2.14

IONET is the internal network which communicates between the various Mark VI modules. It uses
Ethernet with a special poling type protocol ADL (Asynchronous Drives Language) to make the network
more deterministic.
The Bus Master Controller cards (VCMI) and the Turbine Protection cards (VPRO) are the only
cards involved in the IONET communications. The VPRO is a hybrid card which combines VCMI
functionality with dedicated protective I/O and software.

Figure 2.13 VCMI Card

 Subject:
Voting Panel- Page
hardware 2.15

Voting is the mechanism that takes care that finally all three UCVx cards get the same data.
It is not important in which rack the I/O card are. The VCMI cards are collecting the data, do the
voting and then send the voted values to the processors.

For TMR I/O:

Digital inputs - controllers vote 2 out of 3 inputs
Analog inputs - controllers select median value
Digital outputs - voted at terminal board
2 out of 3 relay drivers for redundant outputs
2 out of 3 relay contacts for critical outputs
Analog outputs - each controller has its own regulator

For Simplex I/O

All inputs are exchanged with all other processors, no voting occurs

I/O Rack Control Rack

Field Wiring Termin. Bd. I/O Board VCMI IONet VCMI Controller

Sensors Dedicated Signal Prevote Exchange Voter Control System

Input Condition Data Base
Alarm Limit

SC R Voted (A,B,C)
A
R Voter

B SC S Voted (A,B,C)
S Voter

SC T Voted (A,B,C)
C
T Voter

Figure 2.14 3 Sensors for one TMR value.

I/O Rack Control Rack

Field Wiring Termin. Bd. I/O Board VCMI IONet VCMI Controller

Sensors Fanned Signal Prevote Exchange Voter Control

Input Condition System Data
Base
SC R Voted (A)
A
R Voter

SC S Voted (A)
S Voter

SC T Voted (A)
T Voter
Figure 2.15 One sensor for one TMR value
 Subject:
Voting Panel- Page
hardware 2.16

I/O Rack Control Rack

Field Wiring Termin. Bd. I/O Board VCMI IONet VCMI Controller

Sensor Direct Signal Exchange No Control System

Input Condition Vote Data Base
Alarm Limit

A SC R

Figure 2.16 One sensor for one simplex value in a TMR panel

Termination Board, Relay Outputs

I/O Board
Channel R

I/O Board Voted

Channel S Relay Coil
Driver
Relay Output
I/O Board
Channel T

Termination Board, High Reliability Relay Outputs

I/O Board KR KS
Channel R Relay KR
Coil
Driver

KS KS KT Relay Output
I/O Board Relay
Coil
Channel S Driver
KT KT KR
Relay
I/O Board Coil
Driver
Channel T

Figure 2.17 TMR relays outputs

 Subject:
Voting Panel- Page
hardware 2.17

I/O Boards
Servo Driver Output
Termination Coils
Channel R
D/A Board on Servo
Valve

Servo Driver
Channel S
D/A

Servo Driver
Channel T
D/A
Hydraulic
Servo
Valve

Figure 2.18 TMR Servo output.

I/O Boards
4-20 mA Driver Output Current
Channel R Termination Feedback
D/A Board

Output
4-20 mA Driver
Load
Channel S
D/A

4-20 mA Driver
Channel T
D/A

Figure 2.19 TMR 4 – 20mA output

 Subject:
MK6 I/O hardware Panel- Page
hardware 2.18

The Mark VI I/O cards.

Card In Control Module Termination Board

Card Function Catalog Number I/O Capacity Catalog Number I/O Capacity "Per Board" Wide / Narrow
Turbine Card (Generic) IS200VTUR (12 TMR / 4 Simp) Speed Inputs IS200TTUR (12 TMR / 4 Simp) Speed Inputs Wide
Gen. & Bus 1 Phase PT Inputs Gen. & Bus 1 Phase PT Inputs
Auto / Manual Synch. Interface Auto / Manual Synch. Interface
Shaft Voltage & Current Monitor Shaft Voltage & Current Monitor
Primary Trip Relays IS200TRPG Primary Trip Relays Wide
(8) Flame Inputs (Honeywell) 1=TMR, 2=Simp (8) Flame Inputs (Honeywell)
Protection Card IS200VPRO (3) Speed Inputs IS200TPRO (9) Speed Inputs Wide
Gen. & Bus 1 Phase PT Inputs Gen. & Bus 1 Phase PT Inputs
(1) 4-20ma or +/-5,10vdc Inputs (1) 4-20ma or +/-5,10vdc Inputs
(2) 4-20ma Inputs (2) 4-20ma Inputs
(3) Thermocouple Inputs (9) Thermocouple Inputs
(3) Emergency Trip Relays IS200TREG (9) Emergency Trip Relays Wide

& Support Relays & Support Relays

Figure 2.20 Overviewt I/O cards MKVI

 Subject:
I/O cards Panel- Page
hardware 2.19

Figure 2.21 Mark VI I/O Card

Figure 2.22 Mark VI I/O Card

 Subject:
Digital I/O Panel- Page
hardware 2.20

<R> Control Module

Termination Board Input Card Processor
IS200TBCI IS200VCRC Card
IS200UCV_
JE1
(+) Floating
(-)

From Power Distr. Gate Inv. Mask

Module <PDM> Connectors
JE2
125vdc Source on card front
(+) Gate Inv. Mask
(-)
P5
JR1 J33/J44 Gate Inv. Mask

(+) Sup.
Gate Inv. Mask

(-) Ref.
Gate Inv. Mask
Field Contact
(+) Sup.
Gate Inv. Mask
(-) Optical Isolation
60 Vrms Noise Rejection at 125vdc
Excitation Gate Inv. Mask
Field Contact
Sup. 4 msec Hardware Filter
(+)
1 msec Resolution - SOE
(-)

Field Contact
(+) Sup.

(-)
Terminations Terminations
Field Contact
Circuit (+) (-) Conn. Current Circuit (+) (-) Conn. Current
(+) Sup.
Ckt. #1 01 02 J33 2.5ma Ckt. #13 25 26 J44 2.5ma
Ckt. #2 03 04 J33 2.5ma Ckt. #14 27 28 J44 2.5ma
(-) Ckt. #3 05 06 J33 2.5ma Ckt. #15 29 30 J44 2.5ma
Ckt. #4 07 08 J33 2.5ma Ckt. #16 31 32 J44 2.5ma
Field Contact
Ckt. #5 09 10 J33 2.5ma Ckt. #17 33 34 J44 2.5ma
(+) Sup.
Ckt. #6 11 12 J33 2.5ma Ckt. #18 35 36 J44 2.5ma
Ckt. #7 13 14 J33 2.5ma Ckt. #19 37 38 J44 2.5ma
(-) Ckt. #8 15 16 J33 2.5ma Ckt. #20 39 40 J44 2.5ma
Ckt. #9 17 18 J33 2.5ma Ckt. #21 41 42 J44 2.5ma
Field Contact Ckt. #10 19 20 J33 2.5ma Ckt. #22 43 44 J44 10ma
Ckt. #11 21 22 J33 2.5ma Ckt. #23 45 46 J44 10ma
Ckt. #12 23 24 J33 2.5ma Ckt. #24 47 48 J44 10ma

<R> Control Module Termination Board - IS200TRLY

Processor Card Relay Card

IS200UCV_ IS200VCRC "5" of these circuits
K# K#
NO
Relay Terminations
Ckt NC COM NO SOL
Com
1 01 02 03 04
JA1 2 05 06 07 08
P28V K# 3 09 10 11 12
J3/4 NC
4 13 14 15 16
Software Output Buffer 5 17 18 19 20
K1 6 21 22 23 24
7 25 26 27
Connectors at P24 8 29 30 31
bottom of 9 33 34 35
VME rack 10 37 38 39
11 41 42 43
12 45 46 47 48
Monitor

Monitor
"6" of these circuits
DRY
JP1-6 K# K#
NO
SOL JPX
TB3
01 Com
+
02 Field Solenoid
Power Source K#
03 NC
(20Amp) -
04
Sol
JF1 "1" circuit
3.2 Amp Contact Ratings
K# K#
slow-blow NO
Alternate Power 24vdc: 3.0A, resistive
Source 3.0A, L/R = 7ms no suppr.
JF2 Com 3.0A, L/R = 100ms with suppr.
(7Amp)
125vdc: 0.6A, resistive
K# 0.2A, L/R = 7 ms, no suppr.
NC 0.6A, L/R = 100ms, with suppr.
JG1 120/240vac: 3.0A, resistive
Available for GT 2.0A, pf = 0.4
Ignition Transformers Sol 7.0A, with suppr. (12th ckt.)
(7 Amp up to 240 vac)
 Subject:
Panel- Page
Analog I/O
hardware 2.21

Termination Board <R> Termination Board

IS200TBAI <S> IS200TBAI
<T>
Processor Two (2) Output Circuits
Card Application Software #1 Circuit is 4-20ma only
8 Circuits per Term. Board IS200UCV_ #2 Circuit is selectable
4-20 / 0-200ma
Noise
Suppr. Noise
Suppr.
+24vdc Current Limit Analog I/O Card 41
J#
+28v Current Limit
vdc IS200VAIC A/D D/A 24vdc, 0.2amp
+/-5,10vdc A 42
20 ma 43
4-20 ma Gain J3/4 JR1 Current Limit
250 ohms
44 24vdc, 0.2amp
Return
J#
B Accuracy = 0.1%
Open Return Resolution = 14 bit Accuracy = 0.5%
Sampling Type Resolution = 12 bit
JO 200
A/D (16 bit)
Connectors at
Noise
bottom of 20 Suppr.
2 Circuits per Term. Board Signal
VME racks
Median
Maximum Load
Noise 4-20 ma, 500 ohms
Suppr. Select 0-200 ma, 50 ohms
+24vdc Current Limit Excit. Return
J#
1 ma A JR1 J3/4
+/-1 ma Shown for <R>
20 ma J3/4 JS1
4-20 ma Output Terminations
250
5k ohms
ohm
Return Same for <S> Ckt Signal/Return Jumpers
J# 1 45 / 46 None 20 only
B 2 47 / 48 JO 20/200ma
Open Return
J3/4 JT1
JS1 J3/4
Same for <T>

Same for <S>

Input Terminations
Ckt P24V/20ma/VDC/RetJumpers
JT1 J3/4 1 01 / 02 / 03 / 04 J1A,J1B
2 05 / 06 / 07 / 08 J2A,J2B
3 09 / 10 / 11 / 12 J3A,J3B
Same for <T> 4 13 / 14 / 15 / 16 J4A,J4B

10 37 / 38 / 39 / 40 J10A,J10B

Termination Board - IS200TBAO

<R> Control Module

Processor Maximum Load

Second set of (8)
Card D/A J3 JR1 Noise 4-20 ma, 500 ohms
4-20ma outputs Suppr.
IS200UCV_ 01 Signal

TMR 50 ohms
4-20ma Circuit #1
Simp 02 Return
Output Card
IS200VAOC Voting Circuitry 03 Signal

04 Return
Circuit #2
05 Signal
Sensing
06 Return Circuit #3
07 Signal

08 Return Circuit #4
Group 1 09 Signal
10 Return Circuit #5
11 Signal
12 Return Circuit #6
13 Signal
14 Return Circuit #7
15 Signal
Second set of (8) 16 Circuit #8
D/A J4 JR2 Return
4-20ma outputs
17 Signal

TMR 50 ohms 18 Return Circuit #9

Simp 19 Signal

Voting Circuitry 20 Return Circuit #10

21 Signal
22 Return Circuit #11
Sensing
23 Signal
24 Return Circuit #12
Accuracy = 0.5% Group 2 25 Signal
Resolution = 12 bit Connectors at Circuit #13
26 Return
bottom of
VME rack 27 Signal
28 Return Circuit #14
29 Signal
30 Return Circuit #15
31 Signal
32 Return Circuit #16
 Subject:
Thermocouples and RTD’S Panel- Page
hardware 2.22

<R> or <S> or <T> Control Module

Termination Input Card Processor

Board Card
System (Software) Limit Checking - 2 Hi / Lo Limits IS200UCV_
J#1 J3/4
Process Input Process Input in Engineering Units
A/D f( )

Config_en_L(n)
Config_en_O(n)
Enable
Scaling
Noise
Sensor A=>B Latch
Suppression
or AND
Config_lmt(n)
A=<B
Hi / Lo Select
System Limit Check
System Alarm Disable OR
Noise
Sensor Config_latch(n)
Suppression
Latch Alarm AND

AND Reset Alarm Latch

Noise
Sensor Suppression
To Other System Alarms

Diagnostic (Hardware) Limit Checking - 2 Hi / Lo Limits

Noise
Sensor Suppression Filtered Signal
A=>B Latch
or Diagnostic Alarm Limit Check
Hi / Lo Limits OR
A=<B

Noise
Sensor Suppression
AND Reset Diagnostic Alarm Latch

To Other Diagnostic Alarms

Composite Diagnostic
Noise
Sensor Suppression
From Other Alarm For Input Card
Diagnostic Alarms OR

"System" Alarm Disable

<R> or <S> or <T> Control Module

Termination Input Card Processor

Board Card
System (Software) Limit Checking - 2 Hi / Lo Limits IS200UCV_
J#1 J3/4
Process Input Process Input in Engineering Units
A/D f( )

Config_en_L(n)
Config_en_O(n)
Enable
Scaling
Noise
Sensor A=>B Latch
Suppression
or AND
Config_lmt(n)
A=<B
Hi / Lo Select
System Limit Check
System Alarm Disable OR
Noise Config_latch(n)
Sensor Suppression
Latch Alarm AND

AND Reset Alarm Latch

Noise
Sensor Suppression
To Other System Alarms

Diagnostic (Hardware) Limit Checking - 2 Hi / Lo Limits

Noise
Sensor Suppression Filtered Signal
A=>B Latch
or Diagnostic Alarm Limit Check
Hi / Lo Limits OR
A=<B

Noise
Sensor Suppression
AND Reset Diagnostic Alarm Latch

To Other Diagnostic Alarms

Composite Diagnostic
Noise
Sensor Suppression
From Other Alarm For Input Card
Diagnostic Alarms OR

"System" Alarm Disable

 Subject:
Servo’s Panel- Page
hardware 2.23

Servo Output Terminations

<R> Termination Board
Ckt High 1k ohm Return Comment <S> IS200TSVO
1R 25 31 26 Servo 1, coil 1 <R> <T>
1S 27 ---- 28 Servo 1, Coil 2 <S> Processor Range
1T 29 ---- 30 Servo 1, Coil 3 <T> Card Application Software 10,20,40,80,120 ma
JD1
2R 33 32 34 Servo 2, Coil 1 <R> IS200UCV_
P28VR Trip input from <P>
2S 35 ---- 36 Servo 2, Coil 2 <S> JT1
Connectors at Module (J1)
2T 37 ---- 38 Servo 2, Coil 3 <T> JS1
bottom of
Termination VME racks Servo Card JD2
Board IS200VSVO D/A
IS200TSVO
P28V J3/4 JR1 JP1,4 Servo coil driven from <R>
LVDT JR1 J3/4
A/D S
3.2k Hz, 7 V rms U
6 Ckts. 22 ohms
Excitation Source Suicide
2 Ckts. P
Relay 1k ohm 89 ohms
JS1 J3/4 1k ohm
Configurable
Gain
or LVDR Same for <S>
3.2KHz
S 3.2KHz, 7V rms
Diode High JT1 J3/4 2 Ckts. U Excitation Source
Select R/S/T P
For LVDTs
Same for <T>
P28V J3/4 JS1 Servo coil driven from <S>
P24V 41 CL JP2,5

42 S 22 ohms
JR5 J5 U
89 ohms
43 2 Ckts. P
Pulse Rate Inputs 1k ohm
Pr/D Same for <S>
Active Probes 44
0 - 12 k Hz
P24V 45 CL
Only available on S 3.2KHz, 7V rms
1 of 2 TSVOs 46 U
1 Ckt. Excitation Source
P
JS5 J5 For LVDTs
47
Pulse Rate Inputs
Same for <S> J3/4 JT1 Servo coil driven from <T>
Active Probes 48 JP3,6
0 - 12 k Hz
Noise
LVDT/R Input Terminations S 22 ohms
SuppressionJT5 J5 U
P
89 ohms
Ckt High Low 2 Ckts.
Same for <T> 1k ohm
1 1 2 Same for <T>
2 3 4
3 5 6 LVDT/R Excitation Terminations
4 7 8 S 3.2KHz, 7V rms
Ckt High Low Source 1 Ckt. U Excitation Source
5 9 10 P
1 17 18 <R> For LVDTs
6 11 12
2 19 20 <R>
3 21 22 <S>
4 23 24 <T>

Flow Reference Linear Interpolator Servo Valve Output

Stroke Reference
V1_FLO_R Input
Out V1_STROKE Input Output V1_OUT
KV1_FLOW0 Args x
K33V1_TRIP
"10" Size
F(x)
KV1_STR0 Function JADJ Select
A
ID # ID Code A=B
B
JADJ - Valve calibration selection
Turbine is reset Enable
from maintenance display
GSADJ Calibrate reference
L14HR L3ADJ
Calibrate
Permissive Servo Reference
Turbine stopped L43ADJ
Forcing In
Progress Valve Regulator - Type 2
L43MAINT Gain - pilot feedback
ARAMP Bias - cylinder feedback
A>X
Up Alarm - Maintenance Gain - cylinder feedback
A<X forcing mode enabled +
Down Reference
GSADJ_REF Input Out + x + + x + D/A
Converter
KGSADJ_RR Rate LVDR #1 - - +
A/D + x Cylinder position V1_POS
Main cylinder p osition Converter F( )
Not used Reset Offset #1 -
fee dba ck in puts fro m
LVDRs. The second Gain #1 Cylinder LVDR #1 position V1_POS1
LVDR is optional for A/D LVDR #2 + Cylinder LVDR #2 position V1_POS2
x
redundancy. Converter
Offset #2 - Type Position Detection
Gain #2 2D First assigned LVDR
2E Max of (2) assigned LVDRs
A/D LVDR #1 + x Pilot position V1_PIL
Pilot valve position Converter F( )
Offset #1 -
fee dba ck in puts fro m
LVDRs. The second Gain #1 Pilot LVDR #1 position V1_PIL1
LVDR is optional for A/D LVDR #2 + Pilot LVDR #2 position V1_PIL2
x
redundancy. Converter
Offset #2 -
Copy Gain #2
L4 Turbine is reset
Enable High limit
L14HP At overspeed OR V1 In Calibrate Mode
Converg. gain
JADJ + Integrator
"0" A
L83JADJ_V1 Calibrate Mode Off Conv. ref. +- -
A=B x +- Output
L83JADJ_V2 L83JADJ_OFF Lag TC Lag
KJADJV1 B
AND 1/(1+Ts)
L83JADJ_V3 No valve in Low limit
calibration mode
SVR_CONVG_1 -TMR systems only SVR_INTGRT_1
Copy
 Subject:
Speedmeasument and trips Panel- Page
hardware 2.24

<PDM>
24 or 125vdc
<R> Control Module

Termination Board Turbine Card Termination Board J1

IS200TTUR IS200VTUR IS200TRPG2
Processor
JR5 Card
J5
41
Filter
IS200UCV_ J4 JR1
#1 Primary
Clamp Median Select
Magnetic Suppr.
AC
f( ) Pr/D
& OS Algorithm Buffer
Speed PU 42 Coupling

Connector at
bottom of
43
Filter
VME rack
#2 Primary
Clamp
Magnetic Suppr.
AC
Speed PU 44 Coupling

Power
45
#3 Primary Filter
Clamp J2
Magnetic Suppr.
AC
46 -
Speed PU Coupling
Hydraulic Trip Solenoids
+

0 to 14 k Hz -
Termination Board J2
IS200TPRO
<P> Protection Module (EOS) - Section X
JX5 J5 <R>
31 Commun.
Filter
JX1
#1 Emerg. J3
Clamp
Magnetic Suppr.
AC
f( ) Pr/D OS Algorithm Buffer
Speed PU 32 Coupling
J7 <PDM>
3 Circuits IS200VPRO 125vdc
JY5
37 <P> Protection Module (EOS) - Section Y Termination Board
Filter
JY1
#2 Emerg. IS200TREG
Clamp
Magnetic Suppr.
AC
Same for Section Y
Speed PU 38 Coupling
IS200VPRO J1
3 Circuits Trip signal to
JZ5 servo TB
43 TSVO (JD1)
<P> Protection Module (EOS) - Section Z JZ1
#3 Emerg. Filter
Clamp
Magnetic Suppr.
AC Same for Section Z
Speed PU 44 Coupling
IS200VPRO
3 Circuits

Trip signal to servo TB

TSVO (JD1)

Termination Board J1
IS200TREG
13 JX1 <P>
14 CL P28VV VPRO
15 Section X
J3
E-STOP 16 JY1 <P>
17 VPRO
K4X
18 Section Y
P125X
J3
K4Y 2 JZ1 <P>
KE1 RD
JH1 3 VPRO
-125vdc
<PDM> Section Z
Power Distribution K4Z Economizing Relays KE2 2 J3
+125vdc RD 3
Module For Solenoids

KE3 2
35 RD 3

36

37 KE1,2,3

38
K4CL 2
RD 3
39 Servo Clamp

40

41 28vdc
Trip Contacts 42
Diagnostics monitor the
43 relay contacts
44

45

46

47

48
 Subject:
Trip solenoid and Light off protection Panel- Page
hardware 2.25

<R> Control Module

Processor Card Relay Card

IS200UCV_ Select off-line IS200VCRC Termination Board - IS200TRLY
overspeed test Daughter Board
L20PTR J3/4 JR P24 +125vdc
L4T L43PTR1_OFO
Buffer
Turbine trip "1" to reset K1
L52GX Activate E-Stop PB - Local
Hydraulics P24
Breaker closed
E-Stop PB - Remote
Typical System Trips * Duplicate contacts to contact
L5E Manual emergency trip K1 K1
NO input module
L12H Primary overspeed latched trip
L14HR Zero speed
L26EXHT High exhaust temperature Com
L39AXT Axial position trip Connectors at 28 or
L39AXFT Axial probes failed PTR1
bottom of 125vdc K1 +
L39VT Vibration trip NC Interposing
VME rack
L63EVT Exhaust vacuum trip Relay - Type
L63HQLT Hydraulic oil pressure low - GE HGA
L63QT_L Lube oil pressure low Ret
To contact input
L63TRIP Emergency trip header tripped
module for
L71QT_L Lube oil level low
Termination Board - IS200TRLY diagnostics
L86G1 Generator protective trip
(Second TB is an option on Simplex)
J3/4 JR P24
L20PTR L20PTR1_FB L30PTR1 House Power
Alarm HGA
#1 failure
"1" to reset K2 Shown for PTR1
L20PTR2_FB L30PTR2 energize
Activate
Alarm HGA to trip Trip
Hydraulics P24
#2 failure Solenoid
L4TRESET
Single Shot Disable trip on reset PTR2
K2 K2
NO
L20PTR1_FB L20PTR2_FB L4PTR House Power
Turbine trip
Com
HGA relays are de-energized 28 or PTR2
125vdc +
K2 Interposing
NC
Relay - Type
- GE HGA
Ret To contact input
module for
-125vdc diagnostics

<R> Control Module

Termination Board Input Card Processor
IS200TRPG2 IS200VTUR Card
IS200UCV_
J3 Typical Logic For Turbines With (2) UV Scanners
335vdc
<R>
Power Supply
Flame detected on either
Monitor Run Turbine
UV scanner
J4
L28FD1
Not Used
Loss of flame detected on Trip Turbine
JR1 J4 both UV scanners & Alarm
J5 L28FD2

Not Used A/D

Scanner disagreement or
Diagnostic Alarm
low light intensity

UV Scanners (+) 33 Connector at

bottom of
(-) 34 VME rack

(+) 35 Typical Logic For Turbines With (4) UV Scanners

(-) 36
L28FD1
(+) 37 Flame detected on any 2
Run Turbine
UV scanners
(-) 38
L28FD2
(+) 39
Loss of flame detected on Trip Turbine
(-) 40 any 3 UV scanners & Alarm
L28FD3
(+) 41

42 L28FD4 Scanner disagreement or

(-) Diagnostic Alarm
low light intensity
(+) 43

(-) 44

(+) 45

(-) 46

(+) 47

(-) 48
 Subject:
Vibrations Panel- Page
hardware 2.26

<R>
<S>
<T>
Term ination Board Proxim itor Processor
IS200TVIB Card Card
IS200VVIB IS200UCV_ L39VF1X "X" Probe Fault Alarm

P = Proxim itor L39VF1Y "Y" Probe Fault Alarm

S = Seismic
Proxim itor V = Velom iter L39VA1X
CL L39VA1
-24vdc * Only 8 vibration Vibration
inputs / VVIB L39VA1Y OR
Probe Alarm
at > 3,600 rpm
"X"
S
V Connectors at
J1-8A
3ma
bottom of L39VT1X L39VT1
P/A VM E racks
L39VT1Y OR Vibration Trip
Noise
Suppression
Shown for <R>
Proxim itor JR1 J3/4 -28vdc
-24vdc CL
XVIBM 00 - Vibration Monitor
Probe A/D BB1X vibration
"Y"
S A Alarm L39VA1X
V K39VA1X alarm lim it A>=B T
J1-8A B
Sam pling Type
P/A A/D (16 bit) A Trip L39VT1X
JS1 J3/4 K39VA1X trip limit A>=B T
Noise B
Suppression L39VF1X probe fault
4.5 Vp-p Same for <S> Fault L39VFLT1X
O
(22.5 m ils at 0.2 V/m il) L39VH1X signal health R
Accuracy = 0.03 Vpp
(1% of 3.0 Vpp) JA1 K39SCA tim e delay
Resolution = 14 Bits P,V
(+1 to -20 vdc) JT1 J3/4

J1-4B S XVIBM 00 - Vibration Monitor

Buffered Ouputs Sam e for <T>
P1-4 BB1Y vibration
To Bently Nevada
3500 Monitor A Alarm L39VA1Y
JB1 K39VA1Y alarm lim it A>=B T
B
P,V
JA1: Circuits 1-4 A Trip L39VT1Y
K39VA1Y trip limit A>=B T
J5-8B JB1: Circuits 5-8 B
S
L39VF1Y probe fault
P5-8 O Fault L39VFLT1Y
Input Terminations L39VH1Y signal health R
Ckt -24V/High/Low Jumper K39SCA tim e delay
1 01 / 02 / 03 J1
2 04 / 05 / 06 J2
3 07 / 08 / 09 J3
4 10 / 11 / 12 J4
5 13 / 14 / 15 J5
6 16 / 17 / 18 J6
7 19 / 20 / 21 J7
8 22 / 23 / 24 J8

<R>
<S>
<T>
Termination Board Proximitor Processor
IS200TVIB Card Card
IS200VVIB IS200UCV_
JC1

L39AF1 Probe #1 Fault Alarm - 1 sec TD L39AXA1

Buffered Ouputs L39AXA
L39AF2 Probe #2 Fault Alarm - 1 sec TD L39AXA2 Any Probe At
To Bently Nevada JD1 OR T
L39AF3 Probe #3 Fault Alarm - 1 sec TD L39AXA3 Alarm Level
3500 Monitor 1 sec

L39AF1 L39AXT1
JC1: Circuits 9-12 Position Connectors at L39AXFT L39AXT
JD1: Circuits 13, 14 KP bottom of L39AF2 2/3 Probe L39AXT2 2/3 Probes At
2/3 T 2/3 T
VME racks L39AF3 Fault Trip L39AXT3 Trip Level
1 sec 1 sec
Probe Proximitor Shown for <R>
-24vdc CL
JR1 J3/4 -28vdc

XAXPO01 - Axial Position Monitor

Noise AXIAL1 input
Suppression
A/D Alarm L39AXA1
OR
K39AAA active alarm A Not Used
A>=B
B
Probe Proximitor Sampling Type
-24vdc CL A/D (16 bit)
JS1 J3/4 K39AIA inactive alarm A Not Used
A<=B
B

Noise Same for <S> A Not Used

K39AAT active trip A>=B
Suppression B
Not Used
K39AIT inactive trip A
Probe Proximitor A<=B
-24vdc CL B Trip L39AXT1
JT1 J3/4 OR
L39AF1 probe fault

Noise
Range = -0.5 to -20 vdc Suppression
Same for <T> AXIAL2 L39AXA2
Accuracy = 1% of full scale
Resolution = 14 Bits Same as above for thrust input #2
L39AF2 L39AXT2

AXIAL3 L39AXA3
Input Terminations Same as above for thrust input #3
L39AF3 L39AXT3
Ckt -24V/High/Low Function
9 25 / 26 / 27 Position
10 28 / 29 / 30 Position
11 31 / 32 / 33 Position
12 34 / 35 / 36 Position
13 37 / 38 / 39 Keyphas
 Subject:
Generator Panel- Page
hardware 2.27

Auto Synch Permissive

L52GX Gen. breaker closed Auto / Manual
Synch Permissive
L2GFF2 At field flashing speed
L52SX Auto synch perm.
L86S Auto synch not locked out AND
L83S_AUTO In auto synch mode AND L3DV Gen voltage ok to synch L25P
L4 Turbine is reset OR AND
L83S_MAN In man synch mode L43EX_ALM EX2000 in man regulator

Auto / Manual synch check permissive

Synch Check
Relay Perm. Auto Synch Enabled Speed Matching Permissive
L43EX_ALM EX2000 in man reg. L52G Gen breaker direct FB L25P L52SX Auto synch perm.
L83S_MAN In man synch mode AND L83S_AUTO L52Z Auto synch enabled
AND
OR AND
L25P Auto / Man sych perm. L3SVL System voltage ok (TD) L2S (25X) L27BN Bus undervoltage L69TNM
AND
L14HS Turbine at synch speed
L3SYNCH Sys & gen voltage ok
L25X_PERM & system & gen frequency ok
L3DEADBUS Deadbus closure perm. AND
Synch check
permissive

Auto / Manual synch check permissive

Auto Synch Permissive

L69TNM Speed matching perm. Breaker
close time SSDIFF Phase
L83S_AUTO In auto synch mode
L83AS
AND L25_BYPASS Synch bypass SFDIFF Slip
L3DV_ERR Gen diff. voltage error ok
SFL Frequency
L3SFDIFF System freq. diff. slip ok
AND L83ASX Auto synch selected Phase / SYNCH_BKR_DELAY1
L3GEN Gen voltage > 50% Slip
L43SAUT2 Second breaker Calculation SYNCH_BKR_DELAY2
L3BUS Bus voltage > 50%
Bus voltage / frequency input SSDIFF_1,2,3 Predicted phase
Gen voltage / frequency input L25 & L25DRV Close breaker

<R> Control Module

Termination Board Processor
IS200TGEN Card
IS200UCV_
4 Circuits per Term. Board
Accuracy = 0.1%
TB1 Noise
Suppr. Resolution = 14 Bits Proximitor Termination
+24vdc Current Limit Card Board
J# IS200VGEN IS200TRLY
vdc A
+/-5,10vdc
20 ma
4-20 ma
250 ohms
Return Buffer
J#
B
Open Return

JR1 J3 +28vdc J4 JR1

18 TB1

19 Noise A/D Optional Relay Module for

Suppr.
TP-GA Medium Steam Turbine
A 18 applications.
Generator TP-GB Connectors at Interface to (12) fast acting
3 Phase Volts B 19
bottom of solenoids
(115VAC) TP-GC VME rack
C 20
TP-BA
A 21
Bus TP-BB
3 Phase Volts B 22
(115VAC) TP-BC
C 23
TB2 TP-IA1
H1 01 1:2000
H2 02 100 ohms
Current - Phase A TP-IA2 0.01%
(115VAC) L1 03
L2 04
TB3 TP-IB1 Accuracy J1
H1 01 1:2000
= 0.5%
H2 02 100 ohms
Resolution
Current - Phase B TP-IB2 0.01%
(115VAC) L1 03 = 0.1%
L2 04 <PDM>
TB4 TP-IC1 Analog Input Terminations
H1 01 1:2000 Typically 120vac
H2 02 100 ohms Ckt P24V/20ma/VDC/Ret Jumpers
Current - Phase C TP-IC2 0.01% 1 01 / 02 / 03 / 04 J1A,J1B
(115VAC) L1 03
2 05 / 06 / 07 / 08 J2A,J2B
L2 04
3 09 / 10 / 11 / 12 J3A,J3B
4 13 / 14 / 15 / 16 J4A,J4B
5 amps yields 0.25 Vrms (l-n)
or 0.433 Vrms (l-l)
 Subject:
Power Supply Panel- Page
hardware 2.28

<R> Control Module <PS-R> Power Supply

N/C Pin 4 Blank

0V (28VA) Pin 6 Ret
+28VA Pin 8 28V
0V (28VB) Pin 10 Ret
+28VB Pin 12 28V
0V (28VC) Pin 14 Ret
+28VC Pin 16 28V
0V (28VD) Pin 18 Ret Connector PSA
+28VD Pin 20 28V On top of supply

0V (28VE) Pin 22 Ret

+28VE Pin 24 28V
0V (-28V) Pin 26 Ret Located on front
of power supply
-28V Pin 28 -28V
0V (-15V) Pin 30 Ret
-15V Pin 32 -15V Power
1
N/C Pin 4 Blank 0
Power Supply Test Points 0V (+15V) Pin 6 Ret
Located at bottom-left
+15V Pin 8 +15V
TP1 P15
0V (-12V) Pin 10 Ret
TP2 ACOM
-12V Pin 12 -12V
Normal
TP3 N15
0V (+12V) Pin 14 Ret
TP4A P28AA
+12V Pin 16 +12V
TP4B P28BB
0V (+5VA) Pin 18 Ret Connector PSB
TP4C P28CC On top of supply
+5VA Pin 20 5V
Fault
TP4D P28DD
0V (+5VB) Pin 22 Ret
TP4E P28EE
+5VB Pin 24 5V
TP5 PCOM
0V (+5VC) Pin 26 Ret
TP6 N28
+5VC Pin 28 5V
Connectors located on bottom of supply
TP7 DCOM
0V (+5VD) Pin 30 Ret
TP8 SCOM
+5VD Pin 32 5V PS28A PS28B PS28C PS335 PS125
Fan

From <PDM> J1R