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COA Assignment

The document contains the solution to a programming problem involving adding 4 numbers stored in memory locations and storing the result. It then provides explanations of: 1) The values in registers after each instruction is executed. 2) A comparison of pipeline and non-pipelined processor performance in terms of clocks, CPI, and SF for the same instruction count. 3) The contents of the instruction cache after 1, 2, and 3 iterations of the program using direct mapping with a block size of 4 and cache size of 16.

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rajat
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88 views

COA Assignment

The document contains the solution to a programming problem involving adding 4 numbers stored in memory locations and storing the result. It then provides explanations of: 1) The values in registers after each instruction is executed. 2) A comparison of pipeline and non-pipelined processor performance in terms of clocks, CPI, and SF for the same instruction count. 3) The contents of the instruction cache after 1, 2, and 3 iterations of the program using direct mapping with a block size of 4 and cache size of 16.

Uploaded by

rajat
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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Group 10

19 2017HW86577 391480 Rajat Kumar


28 2017HW86749 391509 Priya Jha
29 2017HW86502 391525 Umang Singhal
8 2017HW86522 391469 Saurabh Narayan Dhande

A ) Store the numbers 1 to 4 at data memory location starting from 06h. Add
these 4 numbers and store the result at location 20h.

Solution : 1,2,3,4 Added to memory location 0006,0007,0008,0009 respectively as shown in


screenshot below.
1+2+3+4 = 10
Output which is 10 (Represented by OA) stored at memory location 0020.
All instructions that are used to achieve desired output are in the screenshot below.

A) Explain resultant intermediate General Purpose register values in the


register window after running above program.
Solutions:
Will be explaining only register instructions here

1) LDB 0006,R00 # Load byte data from memory location 0006 to R00 R00 will have 1.

2) LDB 0007,R01 # Load byte data from memory location 0007 to R01 R01 will have 2.

3) LDB 0008,R02 # Load byte data from memory location 0007 to R02 R02 will have 3.

4) LDB 0009,R03 # Load byte data from memory location 0009 to R03 R03 will have 4.

5) ADD R00,R01 # Add data from register R00 and R01 to R01 R01 will have (1+2=) 3

6) ADD R02,R03 # Add data from register R02 and R03 to R03 R03 will have (3+4=) 7

7) ADD R01,R03 # Add data from register R01 and R03 to R03 R03 will have (3+7=)10

8) STB R03,0020 # Store the byte from R03 to 0020 memory location
B ) Show, explain and justify with pipelining and without pipelining stages w.r.t
the below table parameters

W/o pipelining With pipelining


Clocks 1044 478
CPI 5.04 1.89
SF .99 2.18
Instruction count 207 207
Validity of answer (Answer correct or not) - -

C) Execute Program 3 Times. Show the contents of instruction cache after end of
every iteration in the table below (total 3 iterations) Show and explain misses Vs
cache size chart (graph) for instruction cache for block size =4 and cache size = 16
using direct mapping technique. Also explain the below table for each instruction

Iteration – 01
Address Instruction Hits Block Misses
1000 STB #01, 0006 - 0 1
1007 STB #02, 0007 1 0 1
1014 STB #03, 0008 1 0 1
1021 STB #04, 0009 1 0 1
1028 LDB 0006,R00 - 1 0
1034 LDB 0007,R01 1 1 0
1040 LDB 0008,R02 1 1 0
1046 LDB 0009,R03 1 1 0
1052 ADD R00,R01 - 2 0
1057 ADD R02,R03 1 2 0
1062 ADD R01,R03 1 2 0
1067 STB R03, 0020 1 2 0
1073 HLT 3

Iteration – 02

Address Instruction Hits Block Misses


1000 STB #01, 0006 1 0 1
1007 STB #02, 0007 2 0 1
1014 STB #03, 0008 2 0 1
1021 STB #04, 0009 2 0 1
1028 LDB 0006,R00 1 1 0
1034 LDB 0007,R01 2 1 0
1040 LDB 0008,R02 2 1 0
1046 LDB 0009,R03 2 1 0
1052 ADD R00,R01 1 2 0
1057 ADD R02,R03 2 2 0
1062 ADD R01,R03 2 2 0
1067 STB R03, 0020 2 2 0
1073 HLT 1 3 0
Iteration – 03

Address Instruction Hits Block Misses


1000 STB #01, 0006 2 0 1
1007 STB #02, 0007 3 0 1
1014 STB #03, 0008 3 0 1
1021 STB #04, 0009 3 0 1
1028 LDB 0006,R00 2 1 0
1034 LDB 0007,R01 3 1 0
1040 LDB 0008,R02 3 1 0
1046 LDB 0009,R03 3 1 0
1052 ADD R00,R01 2 2 0
1057 ADD R02,R03 3 2 0
1062 ADD R01,R03 3 2 0
1067 STB R03, 0020 3 2 0
1073 HLT 2 3 0

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