Dataflow modeling

Introduction
For small circuits, the gate level modeling approach works very well because the
number of gates is limited and the designer can instantiate and connect every gate
individually. Also gate level modeling is very intuitive to a designer with a basic
knowledge of digital logic design. However, in complex designs the number of gates
id very large. Thus designers can design more effectively if they concentrate on
implementing the function at a level 0f abstraction higher than gate level. Data flow
modeling provides a powerful way to implement a design.
Verilog allows a circuit to be designed in-terms of the data flow between registers and
how a design processes data rather than instantiation of individual gates.

Continuous Assignments
A continuous assignment is the most basic statement in dataflow
modeling, used to drive a value onto a net. A continuous assignment
replaces gates in the description of the circuit and descrbes the circuit at a
higher leel of abstraction.
A continuous assignment statement starts with the keyword assign. The
syntax of an assign statement is as follows.
// syntax of assign statement in the simplest form
<continuous_assign>
::= assign <drive_strength>?<delay>? <list_of_assignments>;
Notice that drive strength is optional and can be specified in terms of
strength levels. Value set. We will not discuss drive strength specification
here, we will discuss later. The default value for drive strength is strong1
and strong0. The delay value is also optional and can be used to specify
delay on the assign statement.
Continuous assignments have the following characteristics.
1. The left hand side of an assignment must always be a scalar or
vector net or a concatenation of scalar and vector nets. It cannot be
a scalar or vector register.
2. Continuous assignments are always active the assignment
expression is evaluated as soon as one of the right hand side
operands changes and the value is assigned to the left hand side
net.
3. The operands on the right hand side can be register or nets or
function calls. Registers or nets can be scalars or vectors.
 4. Delay values can be specified for assignments I terms of time units.
Delay values are used to control the time when a net is assigned the
evaluated value. This feature is similar to specifying dealys for
gates. It is very useful in modeling timing behavior in real circuits.

Examples:

assign out[3:0] = in0[3:0] & in1[3:0];

assign {o3, o2, o1, o0} = in0[3:0] | {in1[2:0],in2}; // Use of concatenation.

Implicit Net Declaration:

wire in0, in1;

assign out = in0 ^ in1;

In the above example out is undeclared, but verilog makes an implicit net declaration
for out.

Implicit Continuous Assignment

Instead of declaring a net and then writing a continuous assignment on the net, verilog
provides a shortcut by which a continuous assignment can be placed on a net when it
is declared. There can be onlu oone implicit declaration assignment per net because a
net is declared only once.

wire out = in0 ^ in1;

The above line is the implicit continuous assignment. It is same as,

wire out;
assign out = in0 ^ in1;

Delays
Delay values control the time between the change in a right side operand and when
the new value is assigned to the left hand side. Three ways of specifying delays in
continuous statements are regular assignment delay, implicit continuous assignment
delay, and net declaration delay.

Normal/regular assignment delay:

assign #10 out = in0 | in1;

If there is any change in the operands in the RHS, then RHS expression will be
evaluated after 10 units of time. Lets say that at time t, if there is change in one of the
operands in the above example, then the expression is calculated at t+10 units of time.
The value of RHS operands present at time t+10 is used to evaluate the expression.

Implicit continuous assignment delay:

wire #10 out = in0 ^ in1;

is same as

wire out;
assign 10 out = in0 ^ in1;

Net declaration delay:

wire #10 out; // net delay
assign out = in;

is same as

wire out;
assign #10 out = in;

Examples

1. Implementation of a 2x4 decoder.

module decoder_2x4 (out, in0, in1);

output out[0:3];
input in0, in1;

// Data flow modeling uses logic operators.

assign out[0:3] = { ~in0 & ~in1, in0 & ~in1,
~in0 & in1, in0 & in1 };

endmodule

2. Implementation of a 4x1 multiplexer.

module mux_4x1 (out, in0, in1, in2, in3, s0, s1);

output out;
input in0, in1, in2, in3;
input s0, s1;

assign out = (~s0 & ~s1 & in0)|(s0 & ~s1 & in1)|
(~s0 & s1 & in2)|(s0 & s1 & in0);
endmodule

3. Implementation of a 8x1 multiplexer using 4x1 multiplexers.

module mux_8x1 (out, in, sel);

output out;
input [7:0] in;
input [2:0] sel;

wire m1, m2;

// Instances of 4x1 multiplexers.
mux_4x1 mux_1 (m1, in[0], in[1], in[2],
in[3], sel[0], sel[1]);
mux_4x1 mux_2 (m2, in[4], in[5], in[6],
in[7], sel[0], sel[1]);

assign out = (~sel[2] & m1)|(sel[2] & m2);

endmodule

4. Implementation of a Full adder.

module full_adder (sum, c_out, in0, in1, c_in);

output sum, c_out;

input in0, in1, c_in;

assign { c_out, sum } = in0 + in1 + c_in;

endmodule

These programs are using

Data Flow

Modeling//NOT gate
module notgate(a,y);
input a;
output y;
assign y= ~a;
endmodule

//OR gate
module orgate(a,b,y);
inpput a,b;
output y;
assign y=(a|b)
;endmodule

//AND gate
module andgate(a,b,y);
input a,b;

output y;
assign y=(a&b);
endmodule

//NOR gate
module norgate(a,b,y);
inpput a,b;
output y;
assign y=~(a|b);
endmodule

//NAND gate
module nandgate(a,b,y);
input a,b;
output y;
assign y=~(a&b);
endmodule
//XOR gate
module xorgate(a,b,y);
input a,b;
output y;
assign y=(a^b);
endmodule

Operands

Operands can be any one of the data types. Data types

Some constructs will take only certain types of operands. Operands can be
constants, integers, real numbers, nets, registers, times, biit-select.
 Verilog operators

Verilog Name Functional

Operator Group
[] bit-select or part-select
() Parenthesis
! logical negation logical
~ negation bit-wise
& reduction AND reduction
| reduction OR reduction
~& reduction NAND reduction
~| reduction NOR reduction
^ reduction XOR reduction
~^ or ^~ reduction XNOR reduction

+ unary (sign) plus arithmetic

- unary (sign) minus arithmetic
{} Concatenation Concatenation
{{ }} Replication Replication

* multiply arithmetic
/ divide arithmetic
% modulus arithmetic
+ binary plus arithmetic
- binary minus arithmetic
<< shift left shift
>> shift right shift
> greater than relational
>= greater than or equal relational
< to relational
<= less than relational
less than or equal to
== case equality equality
!= case inequality equality
 & bit-wise AND bit-wise
^ bit-wise XOR bit-wise
| bit-wise OR bit-wise
&& logical AND logical
|| logical OR logical
?: Conditional Conditional

1. Arithmetic

There are five arithmetic operators in Verilog.

module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);

input [2:0] A, B;
output [3:0] Y1;
output [4:0] Y3;
output [2:0] Y2, Y4, Y5;
reg [3:0] Y1;
reg [4:0] Y3;
reg [2:0] Y2, Y4, Y5;

always @(A or B)
begin
Y1=A+B;//addition
Y2=A-B;//subtraction
Y3=A*B;//multiplication
Y4=A/B;//division
Y5=A%B;//modulus of A divided by B
end
endmodule
2. Sign

These operators simply assign a positive "+" or negative "-" sign to a

singular operand. Usually no sign operators is defined, in which case the
default "+" is assumed.

module Sign (A, B, Y1, Y2, Y3);

input [2:0] A, B;
output [3:0] Y1, Y2, Y3;
reg [3:0] Y1, Y2, Y3;

always @(A or B)
begin
Y1=+A/-B;
Y2=-A+-B;
Y3=A*-B;
end
endmodule

3. Relational

Relational operators compare two operands and returns an indication of

whether the compared relationship is true or false. The result of a
comparison is either 0 or 1. It is 0 if the comparison is false and 1 is the
comparison is true.

module Relational (A, B, Y1, Y2, Y3, Y4);

input [2:0] A, B;
output Y1, Y2, Y3, Y4;
reg Y1, Y2, Y3, Y4;

always @(A or B)
begin
Y1=A<B;//less than
Y2=A<=B;//less than or equal to
Y3=A>B;//greater than
if (A>B)
Y4=1;
else
Y4=0;
end
endmodule
4. Equality and inequality
Equality and inequality operators are used in exactly the same way
as relational operators and return a true or false indication depending on
whether any two operands are equivalent or not.

module Equality (A, B, Y1, Y2, Y3);

input [2:0] A, B;
output Y1, Y2;
output [2:0] Y3;
reg Y1, Y2;
reg [2:0] Y3;
always @(A or B)
begin
Y1=A==B;//Y1=1 if A equivalent to B
Y2=A!=B;//Y2=1 if A not equivalent to B
if (A==B)//parenthesis needed
Y3=A;
else
Y3=B;
end
endmodule

5. Logical

Logical comparison operators are used in conjuction with relational and

equality operators as described in the relational operators section and
equality and inequality operators section. They provide a means to
perform multiple comparisons within a a single expression.
module Logical (A, B, C, D, E, F, Y);
input [2:0] A, B, C, D, E, F;
output Y;
reg Y;
always @(A or B or C or D or E or F)
begin
if ((A==B) && ((C>D) || !(E<F)))
Y=1;
else
Y=0;
end
endmodule
6. Bit-wise

Logical bit-wise operators take two single or multiple operands on either

side of the operator and return a single bit result. The only exception is
the NOT operator, which negates the single operand that follows. Verilog
does not have the equivalent of NAND or NOR operator, their funstion is
implemented by negating the AND and OR operators.

module Bitwise (A, B, Y);

input [6:0] A;
input [5:0] B;
output [6:0] Y;
reg [6:0] Y;

always @(A or B)
begin
Y(0)=A(0)&B(0); //binary AND
Y(1)=A(1)|B(1); //binary OR
Y(2)=!(A(2)&B(2)); //negated AND
Y(3)=!(A(3)|B(3)); //negated OR
Y(4)=A(4)^B(4); //binary XOR
Y(5)=A(5)~^B(5); //binary XNOR
Y(6)=!A(6); //unary negation
end
endmodule

7. Shift

Shift operators require two operands. The operand before the operator
contains data to be shifted and the operand after the operator contains the
number of single bit shift operations to be performed. 0 is being used to
fill the blank positions.
module Shift (A, Y1, Y2);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B=3; reg [7:0] Y1, Y2;
always @(A)
begin
Y1=A<<B; //logical shift left
Y2=A>>B; //logical shift right
end
endmodule
8. Concatenation and Replication

The concatenation operator "{ , }" combines (concatenates) the bits of

two or more data objects. The objects may be scalar (single bit) or
vectored (muliple bit). Mutiple concatenations may be performed with a
constant prefix and is known as replication.

module Concatenation (A, B, Y);

input [2:0] A, B;
output [14:0] Y;
parameter C=3'b011;
reg [14:0] Y;

always @(A or B)
begin
Y={A, B, (2{C}}, 3'b110};
end
endmodule

9. Reduction

Verilog has six reduction operators, these operators accept a single

vectored (multiple bit) operand, performs the appropriate bit-wise
reduction on all bits of the operand, and returns a single bit result. For
example, the four bits of A are ANDed together to produce Y1.

module Reduction (A, Y1, Y2, Y3, Y4, Y5, Y6);

input [3:0] A;
output Y1, Y2, Y3, Y4, Y5, Y6;
reg Y1, Y2, Y3, Y4, Y5, Y6;

always @(A)
begin
Y1=&A; //reduction AND
Y2=|A; //reduction OR
Y3=~&A; //reduction NAND
Y4=~|A; //reduction NOR
Y5=^A; //reduction XOR
Y6=~^A; //reduction XNOR
 end
endmodule

10. Conditional

An expression using conditional operator evaluates the logical expression

before the "?". If the expression is true then the expression before the
colon (:) is evaluated and assigned to the output. If the logical expression
is false then the expression after the colon is evaluated and assigned to
the output.

module Conditional (Time, Y);

input [2:0] Time;

output [2:0] Y;
reg [2:0] Y;
parameter Zero =3b'000;
parameter TimeOut = 3b'110;

always @(Time)
begin
Y=(Time!=TimeOut) ? Time +1 : Zero;
end
endmodule

Concatenation Operator
The concatenation operator ( {, } ) provides a mechanism to append multiple
operands. The operands must be sized. Unsized operands are not allowed because the
size of each operand must be known for computation of the size of the result.

Concatenations are expressed as operands within braces, with commas separating the
operands. Operands can be scalar nets or registers, vector nets or registers, bit-select,
part-select, or sized constants.

// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110

Y = {B , C} // Result Y is 4'b0010
Y = {A , B , C , D , 3'b001} // Result Y is 11'b10010110001

Y = {A , B[0], C[1]} // Result Y is 3'b101

Replication Operator
Repetitive concatenation of the same number can be expressed by using a replication
constant. A replication constant specifies how many times to replicate the number
inside the brackets ( { } ).

reg A;

reg [1:0] B, C;

reg [2:0] D;

A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;

Y = { 4{A} } // Result Y is 4'b1111

Y = { 4{A} , 2{B} } // Result Y is 8'b11110000

Y = { 4{A} , 2{B} , C } // Result Y is 8'b1111000010