MOTOROLA

MC6839
FLOATING POINT
ROM
 T"8LE IT COllTENTS

Section Title Page

SECTION 1. INTROOUCTION

I.I Early Approach to Mathematical Operation 1-1

1.2 Programs-i n-R{l'1 • • • • • • • 1-2
1.3 MC6839 Floating Point (FP) RO!-\ 1-2
I. 3.1 General ••• 1-2
I.3.2 Pin Assignment • • • • 1-3

SECTION 2. SIAllJARD FLOATINJ POINT FORHAIS

2.1 Introduction • • • • • • • • • • 2-1

2.2 t.brmalized l<Jmbers • • • • • • • 2-1
2.2.J Single Precision Format 2-1
2.2.2 Double Precision Format 2-2
2.2.3 Extended Format • • • • • • • • • • • • 2-2
2.3 Special Values (Single and Double Memory Format) 2-3
2.3.1 Zero • • • • • • • • • • • • - 2-3
2.3.2 Infinity • • • • • • • • • • 2-3
2.3.3 Small l<lmbers (Denormalized) 2-3
2.3.4 t.bt a ltJmber (N'-N) • • • 2-~
2. 4 Special Values (Extended Format) 2-5
2 . 4. I Zero • • • • 2-5
2.4.2 lnf inity . . 2-5
2.4 . 3 Denonnal ized Jt.imbe rs 2-5
2.4.4 ~Ns • • • • 2-5
2.4.5 Unnormalized l<Jmbers 2-6
2.5 BCD Strings •• 2-6
2.6 Binary Integers •• 2-7

SECTIQN , 3. SUPPORTED DPIRATIONS

3.1 Introduction . 3-1

3.2 Required Operations 3-1
3.3 Ext·ra Operations 3-2
3.4 Architecture . 3-2

SECTION 4. MODES IT OPERATIC~ _

4.1 Introduction . . . . . . . 4-1

4.2 Rounding Modes • • • • • • 4-1
4.2.I Rounding Precision • 4-1
4.2.2 t.b Double Round i ng • 4-2
 TABLE Of CONTE tlTS (Contlnu•d)

Section Title Page

4.3 Infinity Closure Modes

4. 3.1 Affl ne Closure
•-2
...2
4.4
4.3.2 Projective Closure
Exception Modes • • •
•-2
... 2

SECTION 5. FLOAT!~ POI NT CONTROL BLOCK

5.1 Jntroduction . . 5-1

5.2 Control Byte •• 5-1
5.3 Status Byte •• 5-2
5.4 Tra p Enable Byte 5-3
5.5 Trap Ve ctor . . 5-3
5.6 Secondary Stetus 5-3

SECTION 6 . USER INTERFACE

6.1 Introduction . . . . . . . . 6-1
6.2 Operation Opcodes and Entry Points 6-1
6 .3 Stack Requirements • . 6-2
6.4 Calling Sequence • • • 6-2
6 . 4. 1 Register Call 6-2
6 . 4.2 Stack Call •• 6-3

APPENDICES
A -- Operation Oescriptions

B -- Application Example of the Quadratic Equation

C -- Oetailed Oescription of Operations

D -- Rounding end Exception Checking Routines

E -- Program Oetails end Stack Frame Oescriptlon

F -- Internal Fonnats

G -- Basic levels of Precision

H -- Oefinitions ind Abbreviations

 SECTION 1
INTRODUCTION

1.1 EARLY APPROACH TO MATHEMATICAL OPERATION

Since the earliest days of computers, It has been obvious that no compu1er was capable
of doing all the desired mathematical operations In binary Integer arithmetic. Some early
Implementations per1orm Ooating point ope rations as a long string of BCD charact~rs .
Although the accuracy of this approach and the ease of Implementation make It a
popular alternative, the speed ls too slow for most applications. Even though the BCD ap·
proach \1 all\\ used today In most BASIC systems and In most systems doing dollars and
cents calculations, most scientific calculations use a binary floating point representa·
lion.
As binary floating point became widely used during the 1960s. each compu1er manufac·
ture r created his own float ing point representation. There was (and ls) a wide variation In
form ats and accuracy which almost guarantees that a program u :ecuted on one com·
puter wlll get different results If executed on another computer. The mini-computer
manufacturers Improved the representations somewhat; but each manufacturer still had
a different format and different ways to represent and handle exceptions and enors.

Meanwhile. research h.. been completed which formulates an optimal binary floating
point representation . Unfortunately, the existing manufacturers had far too much money
tnvested In ao1tware and hardware to Incur the costs of conversion to a new standard.
Powerful microprocessors, on the other hand, were In their Infancy and the floating point
"experts" recognized the opportunity to standardize a floating point format for
microprocessors. The IEEE appointed a committee to address the standard. This manual
describes an Implementation of e proposed IEEE standard, tor the MC6809
Microprocessor (11\PU), which Is In a ROM. The lnfoimation dlscugsed In this manual is
not a "restatement of the proposed IEEE Standard;.. Instead, It addresses those areas
that are required by the proposed IEEE standard and those optional areas that are Im·
p\emented for the MC6809. Specific details of the proposed IEEE atandard can be found
In IEEE Proposed Stlnc!arc! for Bin1ry Floating Point Arithmetic Dr11t B.O(referred to as
the proposed IEEE standard In this manual) which la available from the IEEE.•

Much of the Information, and many of the suggestions, for the proposed IEEE standard
originated In a aeries of papers, published by Jerome Coonen at the University of C&llfor·
nla at Berkeley, the most recent of which Is entitled "Specifications for a Proposed Stan-
dard tor Floating Point Arithmetic" and appeared In the January 11180 Issue of Computer
magulne.

,., - - - - - -
('
1.2 PROGRAMS~N·ROM

From tta Inception, the MC6809 MPU was designed to aupport a concept of "ROMable"
aol1ware by ualng an Improved lnllrucllon aet and addressing modes. One way, and to
aome extent the only way, to reduce the escalating cost of aoltwara was to supply "soft·
ware on alllcon." Since the original cost of developing the aol1ware can be amortized
over a very large number of parts, the actual cost of the ROM part la low.

Shortly alter completing the MC6809 MPU, Motorola eelected floating point to become
the first Motorola Standard Product ROM (SPA). Floating point was selected because It is
standard software that can be used In many diverse systems. Furthermore, lmplementa·
tlon of the proposed IEEE standard Is aufficlenlly complex that many potential
customers would not wish to develop the necessa.ry expertise to wrtte their own soft·
ware; however, they would enjoy the advantages of Its many beneftts.

Hardware Implementations of floating point are always much faster (and more expen·
alve) than software lmplementellons. However, the MC6839 Floating Point ROM
aubslltutes Increased functionality for speed. In addition, the MC6839 floating Point
ROM supports all precisions, modes, and operations required or suggested by the pro·
posed IEEE standard.

f' · 1.3 MC6839 FLOATING POINT (FP) ROM

1~.1 Genoral

The MC6839 FP ROM provides floating point capability for the MC6809 and MC6809E
MCUs. It Implements the entire proposed IEEE standard providing a rel1tively simple,
economical, and reliable solution to a wide variety of numerical appllc1tions. The
MC6839 FP ROM provides three different formats, namely:slngle precision, double preci·
alon, and extended. Both the single and double precision formats provide results which
are blt·for-bit reproducible across all proposed IEEE standard lmplementations:The ex-
tended format provides the extro precision needed for the lntermedi1te resutts of long
calculations, particularly the implementation of transcendental functions and Interest
calculations. All applications benefit from the extensive error checking and well-defined
responses to exceptions, which are strengths of the proposed IEEE standard.

The MC6839 FP ROM tekes full adventage of the advanced archttecturol features of the
MC6809/MC6809E MPU. It ls position Independent and re-entrant, facilitating tts use In
reel-time, multi-tasking systems.

1·2
A brief aummary of the MC6839 FP ROM Is ahown below:
• Totally Posit ion Independent
• Operates In any Contiguous BK Block of Memory
• Re·Entrant
•No Use of Absolu1e RAM
• All Memory References are made Relative to the Stack Pointer
• Flexible User Interface
• Operands are Passed to the FP Package by One of Two Methods
1) Machine Reglstef5 are Used as Polntef5 to the Operands
2) The Operands are Pushed onto the Hardware Stack
•The Latter Method Facilitates the Use of the MC6839 FP ROM In High·Level
Language Implementations
• Easy to Use TworThree Address Arch ite cture
•The User Specifies Addresses of Operands and Result and Nee d Not be Con·
cerned with any Internal Reg ister& or Intermediate Results
• A Complete Implementati on of the Proposed IEEE Standard
• Includes All Preci sions, Modes, and Operations ReQulred or Suggested by the
Standard
• Includes the Following Operations:
Add
Subtra ct
Mu lt iply
Divide
Rema inder
SQuare Root
Integer Part
Absolute Value
Negat e
Pred icate Compares
Condition Code Compares•
Convert Integer-Floating Point
Convert Binary Floating Point-Decimal Siring

1.3.2 Pin Assignment

The MC6839 FP ROM Is housed In one 2•·pln BK·by-8 mask programmable ROM : the
MCM68364. II uses a single 5 V power supply and Is available with access times of 250 or
350 ns . For electrical characteristics, refer to the Advance Information Sheet for the
MC68A39 (1.5 MHz) and MC68B39 (2.0 MHz).

Figure M ahows a pin assignment diagram of the MC6839 FP ROM and Figure 1·2 con·
talns a block diagram of the device.
 Fiil'" 1·1. Pin AHl;nmont Dlogrom

•""'
AO
,.,
Al
----,_~....-- --,._~ •
10 01
,, 02
00

....
A3
13 DJ

"'
AO
A? l
,.,..,. "'"'"'
""23 ~.._ _ __,-~,___ __.-~17 ID
A9 22
A1 0 18
A111S
A122'1 - ,

Figure 1·2. MC6839 FP ROM Block Dlogrom

 SECTION 2
STANDARD FLOATING POINT FORMATS

2 .1 INTRODUCTION

The MC6839 Floating Point ROM (also referred lo as the floating point package In this
manual) supports three precisions of floating point numbers: slngle, double, and extend·
ed . II supports normalized numbers plus four special tJPeS of numbers for each preci·
lion: zeros, Infinities , NANs, and denormalized numbers . The following paragraphs
describe how the numbers are represented In user memory tor each precision. Also
described are the formals used to represent binary Integers and BCD strings.

2.2 NORMALIZED NUMBERS

Normalized numbers are floating poln\ numbers Iha\ are no\ one of thespeclal types. The
bulk cf the numbers In any rea l program w ill be normalized numbers. Three different for-
mats are used with normalized numbers, namely: single precision format, double preci·
sion format , and extended format.

2.2.1 Single Precision Format

All single precision numbers are represented In a four byte string as shown below:

11 i..-- B,--i-,.__23 Bils----+l

I•l Exponent l Signlficand I
In slngle precfslon formals shown above, the exponent Is biased by + 127. Thal ts, an ex·
ponen\ of: 0 Is 127, 2 Is 129, and -2 Is 125.• A normalized floating point number always
has a 1 lo the left of the binary point; this bll Is not explicit tn the memory formats . This
aaves one bit In memory which allows more precision with the same number of bits. ln
this specification, the fraction Is referred to as 11lgnlfic1nd in order to Indicate that It
has an Implied 1.0 added to the fraction. Hence, algnlficands lie In the range

,::-.._ •A blaMCI hpOMflt 1n11ttet t'°911ng point complirt MSlet to~ U.C. the •JIOl*l1 and Mgntfk:and can be~
ak'erltCI H •tong IN909r. A.tao. •n unalgnltel tftt909 r compare c.n• UMdklciakl.llel•thecondltioncodas.ran.rthan a
-.11n; aublract . ·

2·1
1.0<algnlflcand<2.0. S la the 1lgn of the algnlflcand. The algnlficand la stored In sign
magnitude rather than twos complement form. The equation for the single precision for·
mat representation Is:
X c (-1>2x2(exponent -127lx(1.algnlflcand).
• • 1lgn bit"' bit at ring length of 1.
exponent "' b lued exponent - bit string length of 8.
algnlficand "' bit at ring length of 23 encod ing the significant btts of the number that·
low the b inary point, yield ing a 24 bit algnificand digit field for the
number that always begins "1 __• . ·
Examples :
+ 1.0 = 1.0 x :20 = S3F, BO, 00, 00
+ 3.0 = 1.5 x 21 = $40, 40, 00, 00
-1 .0= - 1.0 x20:SBF, BO, 00, 00
+ 7.0= 1.75x22"140, EO, 00, 00
+0.5= 1.0 x 2-t s$3F, 00, 00, 00

2.2.2 Double Prtclslon Format

All double precision numbers are represe nte d In an eight byte string as 1hown below:
I 1 loo-11 Bits...-j4.-52Bits---+1
Js I Exponent I Signlficand I
In the double precision format shown above , the exponent Is biased by + 1023. Inter·
pretat ion of the format Is similar to the single precision format except the bias is + 1023
Instead of + 127. The equation fo r the double precl1ion format representation is:
X= (- t)• x s(" xponent - 1023) I' (1 .1ignif lcand)
Examples:
=
7.0 = 1.75 x 22 $40, IC, 00, 00, 00, 00, 00, 00
16.0"' 1.0 x i4 "'$40, 30, 00, 00, 00, 00, 00, 00
30.0= 1.B75 xi4cS40, 3E, 00, 00, 00, 00, 00, 00
-30.0 = - 1.B75 x i4 = SCO, 3E, 00, 00, 00, 00, 00, 00
0.25= 1.0x2-2:$3F, DO, 00, 00, 00, 00, 00, 00

2.2.3 Exltndtd Formtl

Single and double precision formal • should be used to represent the majority of floating
point numbers in the user'• system je.g., storage of arrays). The extended format should
only be uaed for Intermediate calculations such as occur in the evaluation of a complex
expression. In fa ct , extended forrnat may never be required by most users; however,
•Ince lt Is required internally, It Is optionally p rovided . Extended numbers are represented
In a 10 byte string as shown below:
I1 l--15 Bits &I Bits------!
I • I Exponent I1. Signlficand

2-2
 A notable difference between this format and the single and double precision formats Is
that the 1 .O Is expllcllly present In the slgnlficand and the exponent contains no bias and
Is In twos complement form. The equation for double extended Is:
· x., (- 1)5 x 2(exponenl) x slgnlficand
Where the slgnlflcand 'ontalns the explicit 1.0.
Examples:
=
30.0 1 .875 x ~ =$00, 04, FO, 00, 00, 00, 00, ·oo, 00, 00
0.5= 1.0x2-1 "'S7F, FF, 80, 00, 00, 00, 00, 00, 00, 00
- 1.0 = - 1.0 x 20 = seo. oo. 80, oo. oo, oo, oo, oo, oo, oo
=
384.0" , .5" 28 soo 08, co, 00, 00, 00, 00, 00, 00, 00

2 .3 SPECIAL VALUES (SINGLE AND DOUBLE MEMORY FORMAT)

No derivable floatio~ point forma t can represent the Infinite number of possible real
numbers, so It Is very useful if some special numbers are recognized by a floating point
package . These numbers are: +O, -D, +Infinity, -Infinity, •ery amall (almost zero)
numbers, and in some cases unnormalized numbers. It Is also convenient to have a
special format to Indicate that the content s of memory do not contain a valid floating
point numbe r. This "not a number" might occur If a variable Is defined In 1 high level
language (HLL) and is used before It Is Init ialized with a value. The most positive and
negative exponents of each format are reserved to represent these special values . How
these spe cial fo rmat numbers enter Into calculations will be covered In the detailed
descript ion of each operation (Appendix C).

2.3.1 Zero

Zero Is represented by a number with both a zero exponent and a zero algnlficand . The
sign Is signif icant and differentiate·s between plus or minus zero.

0 0

2.3.2 Infinity

The Infinities are represented by a number with the maximum exponent and a zero
algnlficand. The sign differentiates plus or minus Infinity.

I s 11111 ..•• 11111 o

l.3.3 5matl Humbert (Denormalized)

!-'-- When a number Is so small that Its exponent Is the smallest allowable normal biased
value (1), and 11 ls Impossible to normalize the number without further decrementing the
exponent, then the number becomes denormalized. The formal for denormalized

2-3
 numbers has a zero exponent and a nonzero algnlflcand. Note that In this form the Im·
pllclt bit Is no longer one but Is zero. The Interpretation for denormalized numbers Is:
Single: X"' (-1)1x2-126 x (0. algnlllcand)
Double: X"' (-1)1 x2-126 x (0. algnlflcand)
Note that the exponent Is always Interpreted as 2-126 for alngle and 2-1022 for double
Instead of 2 - 127 and 2- 1023 as might be expected. This Is necessary alnce the only
way to Insure that the lmpllclt bit becomes zero 11 to right ahllt the 1lgnlficand (divide by
2) end Increment the exponent (mult iply by 2). Thus the exponent ends up with the Inter·
pretation of 2 - 126 or 2- 1022.

The format for denormalized numbers Is:

0 Non-Zero

Note that ze ro may be considered a apeclal case of denormalized numbers where the
numbe r Is so small that the 1lgnlficand has been reduced to zero. The concept of denor·
malized numbers has perhaps been the most controversial aspect of the proposed IEEE
standard. However, the concept of allowi ng a number to ..gently underflow .. to ier o
aeems intult ive and straightforward to most Inexperienced users who do not have a built·
In bias fo r some existing floating point representation.
Examples : .
Single : t .Ox2-t28=025 x2-126 = 00, 20, 00, 00
Double: 1.0x2-102s,. 0.12Sx 2-1022 = 00, 02, 00, 00, 00, 00, 00, 00

2.3.4 Not a Number (NAN)

The format for NANs has the larg·est allowable exponent, a nonzero algnlficand, and an
undefined algn. As an lmplementalion feature.(not IEEE required), the nonzero fraction
and undefined algn are further defined as ahown below:

ld I 1111 .....1111 I 1 I Operation Address I 00 .. . 000

d : 0 =This NAN has never entered Into an operation with another NAN.
1 =This NAN has entered Into an operation with other NANs.
t :D= This NAN wlll not necessarily cause an Invalid operation trap when operated upon .
1 "'This NAN wlll cause an Invalid operation trap when operated upon (trapping NAN).
Operation address:
The 16 bits Immediately to the right of the t bit contain the address of the lnstruc·
tlon Immediately following the call to the floating point package of the operation
that caused the NAN to be created. If d (double NAN) Is also aet, the address Is ar·
bltrarlly one of the addresses In the two or more participating NANs.
r-- ..
2.4 SPECIAL VALUES (EXTENDED FORMAn

The apeclal values discussed below are Implemented using the extended format which
was discussed earlier In this aecllon. As explained before, numbers are represented In
this format as a 10 byte airing.

2.4.1 Zero

Zero Is represented by a number with the smallest unbiased exponent and a zero aignlf i·
eand:
I 1 t--15 Bits--;•,..li...•--<64"' Bits---.!
I• j100 .. ... ooool o I
2.4.2 Infinity

Infinity has the maximum unbiased exponent and a zero 1Jgnificand:

I 1 t--15 Bits---+\4--64 Bits---+!

I • !011111 .••• 11! D I
2.4.3 Dtnorm1flzed Numl>t"

Denormalized numbers have the smallest unbiased exponent and a nonzero aignificand :
I 1 l--15 Bits •I• 64 Bits---+!
I • j 100 . .' ._ .• 000 I ·Nonzero I
The exponent of denormalized extended and Internal numbers Is - 16384, and has the
value:
(-1)S x 2-16383 xO.f
Example:
1.ox2- 16387 xD.125x2-16384 x40, DO, 08, oo, oo, oo, oo. oo, oo, 00

2.4.4 NAN1

These have the lar;est unbiased exponent and a nonzero 1ignlficand. The operation ad·
dresses, "!" and ~d", are Implementation features and were defined In an earlier
paragraph of this aection.
I 1 k-15 Bits~ 1 I 1 k - 1 6 Bits •I• 46Blts--+I
Id I 011 .. ••• 1111 I 0 I t I Operation Address I oooooooo I
The operation address always appears In the 16 bits Immediately to the right of the I bit.

2·S
C 1.4.5 UnnormallHd Numbers

Unnormalized numbers occur onl y In extended or Internal format. Unnormalized numbers

have an exponenl which Is greater than the minimum established for Ille extended for-
mat ~ .e ., they are not denormalized or normal zero); however, the explicit leading algnlfi·
cand bit Is a zero. II the algnlflcand Is zero, this Is an unnormalized zero. Even though un·
normalized and denormalized numbers are handled almllarly In most cases, they should
not be confused. Denormalized numbers are numbers that are very small (have minimum
exponent) and hence have lost some bits of the significance. Unnormalized numbers are
not necessarily small (the exponent may be large or small) but the algnlficand has lost
aome blls of significance . hence, the explicit bit and possibly some of the bits to the right
of the explicit bit are zero.

I s I> 100 • .. 000 I0 . Signlficend

Unnormalized numbers cannot be represented (thus, cannot represent a result) for single
precision and double precision formats . Unnormalized numbers can only be created
when denormalized numbers, In single precision or double precision formats , are con·
verted to extended (or Internal) format s.
Example :
D.0625 x 22 (unnormalized) = 00, 02, 08, 00, 00, 00, 00, 00, 00, 00

2.5 BCD STRINGS

A BCD string Is the Input to the BCD·lo·FP operation and the output of the FP·to-BCD
operation. All BCD strings are represented by a 26 byte string with the following format :
D 1 !> 6 24 25 (Byte .#)
se 4 Digit BCD Exponent sf 9 Digit BCD Fraction p

ae =sign of the exponent. 0015=plus, OFts= minus. (I .byte)

af =sign of the fraction . 0015 =plus, OF15" minus. (1 byte)
p =number of fraction digits to the right of the decimal point. (1 byte)

All BCD digits are unpacked and right justified In each byte:

7 D
DDOO

Ui
 The byte ordering of the traction and exponent Is consistent with all Motorola processors
In that the most algnlficanl BCD digit Is In the lowest memory address.
Examples:
2.o.,2.ox1oO (p"'Ol
00 (ae: +I
00, 00, 00, 00 (exponent: OJ
00 (sf"+)
00, 00, 00, 00, 00 (fraction"' 2J
00, 00, 00, 00, 00
00, 00, 00, 00, 00
00, 00, 00, 02
00 (p:OJ
or 2.0 .. 20,000 x io-• (p .. o)
OF (se:-)
00, 00, 00, 0-4 (exponent= •l
oo (sf" +I
00, 00, 00, 00, UO (fraction"' 200000)
00, 00, 00, 00, 00
00, 00, 00, 00, 02
00, 00, 00, 00
00 (p"OJ
{The above might be the output of an FP to BCD operat ion with k:5.)
(""
or 2.0 = 2 .0 x ioO (p = 10)
oo (se= +I
00, 00, 00, 00 (exponent= OJ
00 (sf=+)
00, 00, 00, 00, 00 (fraction= 20000000000J
00, 00, 00, 02, 00
00, 00, 00, 00, 00
00, 00, 00, 00
OA IP= 10J

2..6 BINARY INTEGERS

Two alzes of binary Integers are supported : ahort and double. Short Integers are 16 bits
long and double Integers are 32 bits long. The byte ordering Is consistent with all
Motorola processors In that the most significant bit• are In the lowest address.

2-712~
 SECTION 3
SUPPORTED OPERATIONS

1.1 INTRODUCTION
The 1upported operations are divlcled Into two groups: those required by the proposed
IEEE standard, and those Implemented to support real data types tor Motorola Pascal. A
larger number of operations are required by the proposed standard to Insure portability
of floating point algorithms .

U REQUIRED OPERATIONS

The opera ti ons required to support the proposed IEEE standard are shown In Table 3-1 .
The mnemonic column In Table 3·1 Illustrates the suggested mnemonics although, at
present, no Motorola assembler supports them. The opcodes are used when calling the
MCS839 to differentiate the various functions. The method for call ing Is described In Se c·
,.-.._ tlon 6.

All routines shown In Table 3-1, except FMOV and the compares (FCMP, nCMP, FPCMP,
and FTPCMP), accept arguments of the same precision and generate a result contain ing
the same precision .

-...
Table S.1 . Roqulrod Operalions to Support IEEE Standard

00

"'
MfW!'nOnit
FADD
FS UB
fl.'. L!'l
FOIV
••g1••r; 2- res..11t
• r;1 -•1g:2-m1,11t
• •Ql• •1 ~-Tftl.lh .
• 1g1i• •;2-h1Sur.
Optratio'I

DB ffUM ~•l'l dlt r (9 rg11 ••;21- ~

FCV.P •1condrton todts
""cc ncu P
ergl- • rg2 .
• •gl - • r;2. M 1 c:orlOitClfl c::odff. Tf•P on ~ rtd

.
IE
oc
12
...
FPCM P
FlPCt.l'.P
FMOV
FSOfll
fl Nl
• rg1 - •rg.2 , • thrm OI diwttttll'I 1 pr9d.cttt
• rg1-.,.;:i. ett11mord1Utt11m 1 pt'ldicete, acior- ""°'*'td
mo..I Ol'c::onYrnl-vL--.'-"I
IQU9"1 ~ •r;2-~
in1•• oen c l •1;2-~
••••
...
fflXS lolil ll'ICI • rg2-Shorl ..... _.,.,
FFIXD lolit !!"Q . ,~ -~ ....... Mui\
FFLlS 111"°'1ir'l19· • 1;2-tiolill>QNSul1
FFLlD ~ in191 atg1-b1"'Q ret. tJlt

.,
1C l 1ND£C
Df. C81N
~rr tto. 1~ -decimal
~· BCD
I CD siring
l"t•ing-brle•v teoe1ori;

S.1
t.S !EXTRA OPERATIONS

In order 10 aupport Motorola Pascal, two other operations are supplied. They Include:
Opcode Mn•monlc Operation
1E FAB Absolute Value of arg2 - Result
20 FNEG - arg2 - Result

U ARCHITECTURE

All float Ing point operations are of the ·~wo address" or ·~hree address" variety; ali the
user need suppl y are the addresses of both the operand(s) and the result. The package
looks for operands at the apeclfied locatlon(s) and delivers the result to the apeclfied
destination. For example,
arg1 Result
<Source> <Destination>

The only permanent state Information I• contained In floating point control block (FPCB)
wh ich defines the modes of the package. This control block Is much like the control
blocks lreQuently used to define 110 or operating aystem operations. The FPCB Is
d iscussed In detall In Section 5.
 SECTION 4
MODES OF OPERATION

4.1 INTRODUCTION

In add ition to suppor11ng a wide range of precisions and operations, the MC6839 Floating
Point ROM suppor1s all modes reQulred or suggested by the proposed IEEE standard.
These Include: rounding modes , tnfinlt)' closure modes, and exception handling modes .
The various modes are selected by bits In the floating point control block (FPCB) that
resides In user memory. Thus, a unique aet of modes ts available for user calculations.
The aelectlon b its In the FPCB are defined In Section 5 of this manual. Details of
algorithms used for rounding and exception checking are discussed In Appendix C.

For most users , the default modes specified In the proposed IEEE standard wlll be suffi·
cie nt. The strength of the proposed IEEE standard Is that II provides experienced
numerical analysts with the necessary tools (modes) to generate special complex pro·
grams wh ile, at the same time , making It easier for the average engineering user to get
r the best res ult s possible by selecting the defaults.

4.2 ROUNDING MODES

For the following examples , assume z Is the Infinitely precise result of an arithmetic
operation. Further, assume z1 and z2 are the nearest numbers that bracket z and can be
exactly represented In the selectea precision. That ls: z1 <Z<z2 (barely). Then the follow·
Ing criteria are used to select the delivered result.

Round to Noa rest (RN) - The nearer of z1 or z2 ls selected. In the case of a tie, either of
21 o r z2 with a zero, least significant bit Is chosen (round to even). This Is the delault
mode.

Round Toward Zaro (RZ)- The smaller In magnitude of z1 and z2 ls aelec1ed (truncation).

Round Toward Plus lnllnlty (RP) - z2 Is aelected.

Round Toward llinu1 lnllntty (RM) - 21 Is aelac1ed.

C.2.1 Rounding "'9clalon

Normally • result la rounded to the precision of ha destination. However, when the

destination la Extended Format, the user may apeclly that the resuh aignlficand be
rounded to the precision of the basic tonnat of his choice, although the exponent range

4·1
remains extended. This allows programs written for an lmplementetlon with only the
amaller basic formets to be moved to a full Implementation and atlll generate the same
results .

4.2.2 No Double Rounding

. The MC6839 Floating Point ROM ts Implemented such thlt no result wlll undergo more
than one rounding error.

U INFINITY CLOSURE MODES

The way In which Infinity Is handled In e floating point pacbge may llmlt the number ot
appl ications In which the package cen be used . Toaolvethis problem, the proposed IEEE
atandard requires two types ot Infinity closures. A bit In the control byte of the floating
point control block (FPCB) will select the type of closure that Is In effect II eny time.

4.3.1 Afllnt Closure

In efline closu re: minus ln1inlty<(every finite number)< plus Infinity. Thus Infinity take s
part In the real number system In the same manner as any other signed quantity. The sign
of zero als o takes on meaning In affine mode such that:
+ nl +O= plus Infinity>+ nl -0= minus Infinity where n=llolting point number.
In all othe r operelions, + 0 end -0 part icipate Identically.

4.3.2 Projeetlve Closure

In projective closure: lnfinity=minus Infinity= plus Infinity, and ell comparisons be·
tween Infinity and e real number Involving order relations other than equal (=)or not
equal (•) are Invalid operations. In proje ctive closure, the real number systerri ca n be
thought of as a circle with zero at the 1op and Infinity at the bottom. Thus, Infinity + Infini-
ty and Infinity - lntinlty are Invalid opere\l ons . Projective closure Is the default closure.

4 .4 EXCEPTION MODES

Existing floating point Implementations vary In the way they handle exceptions, ao the
proposed IEEE atendard carefully prescribes how exceptions must be hendled end what
constitutes an exception. Seven types of exceptions will be recognized by the MC6839
Floe\lng Point ROM ; however, only the lira\ five are required by the proposed IEEE aten-
dard. These Include:
1. lnvelld Operation 5. lnexaC1 Result
2. Undertlow I . Integer Overtiow on FINT
3. 0vertlow 7. Comparison of Unordered Values
4. Division by Zero

4-2
 For each exception the caller will have the option of apecllylng whether. (1) the roUllne
ahould trap toe user aupplled trap routine on exception or (2) deliver a default apecllied
by the proposed standard and proceed with execUllon. In either case , a status bit Is set In
the FPCB status by1e and remains aet unlll cleared by the caller's program. Tiie aelectlon
of whether to trap or continue Is made by eettlng bits In the enable by1e of the FPCB. For
more details on the FPCB, aee Section 5. For a detailed description of each exception ,
rater to Append ix 0.

II a trap Is taken, the floatlng point peckage supplies a pointer In the U teglster that
points to the current stack frame (refer to Appendix 0 ). This stack frame contains the
following diagnost ic lnlormetlon:
1. Which Event Caused the Trap (Overflow, etc.)
2. Its Locat ion In the Caller'• Program
3. The Opcode
4. The Input Operands
5. The Default Result In Internal Format
In the event more thi n one excepHon occurs, only one trap will be Invoked according to
the follow ing precedence:
1. Invalid Operat ion
2. Overfl ow
3. Underflow
(;---- 4. Oivl• ion by Zero
5. Unordered
6. Integer Overflow
7. Inexact Resul t

The user supplied trap routine (If any) will usually accomplish one.of the lour Items listed
below.
1. Change the result on the Internal stack to the desired result. Thi• result can then be
returned to the caller by the floating point package during Its stack cleanup.
2. Correct the result directly In the memory space of the caller. In thl• case the floating
point package does not overwrite the result during Its atack cleanup.
3. Do not hing to the result and allow the floating point package to deliver 1he default
value to the result .
4. Abort execution.

All user supplied trap routines must retum to the floating point package (using an RTS In-
struction) for cleanup unless they abort. II the C-blt In the condition code reg ister Is set
on return, then the result (possibly corrected by the trap) Is returned to the destination;
otherwise, no result I• returned to the destination (with the assumption that the user sup -
plied trap handler already returned a value to the destination).
 SECTION 5
FLOATING POINT CONTROL BLOCK

6.1 INTRODUCTION

The lloal\ng point control block (FPCB) Is a user defined block that contain& Information
needed to select the operating mode for a panicular call to the floating point (FP)
package. The FPCB must be defined In user RAM. The FPCB Is also used to pass status
back to the caller or to Invoke the trap routine . The caller of the floating point package
must pass the address of the FPCB on each call (see Section 6, User Interlace, for calling
sequence details). The general form of the FPCB Is:

Control Byte o
Enable Byte
Status Byte
Secondary Status Byte

Address of Trap Routine

The following paragrpahs discuss the use of the various bytes In the FPCB.

6.2 CONTROL BYTE

Tt>e control byte configures the lloal\ng point package for the caller's operation and Is
written by the user.
7 6 5 " 3 2 1 0
~recisi~n x INRM IRoun~ Model AJP
Bit 0 Closure Bit
0 =Projective Closure
1 ,. Affine Closure

Bits 1·2 Rounding Mode

00 =Round to Nearest (RN)
01 .. Round Toward Zero (RZ)
10" Round Toward Plus Infinity (RP)
11 .. Round Toward Minus Infinity (RM)
er Blt3 Normalize Bit
1 s Normalize denormalized numbers while In Internal format bef0<1 using.
Precludes the creation of unnor,....alize~ numbers.
0" Oo not normalize denormalized numbers (warning mode).

Bit 4 Undefined, Reserved

Bits ~7 Precision Mode

OOO"Single
001.,0ouble
010 =Extended With No Forced Rounding of Result
011 "Ex1ended - Force Round Result to Single
100 =Extended - Force Round Result to Double
101 =Undefined, Reserved
110 =Undefined, Reserved
111 =Undefined, Reserved

For move and compare operations , bits S-7 are ..don•t cares" since the aource and
destination prec isions are specified by an extra argument passed to the routine . See Sec·
tion 6, User Interface, for more details of the moves and compare.

Note that If the control byle Is set to ze ro by the user, all defaults In the proposed IEEE
standard w ill be selected.

U STATUS BYTE

The bits In the status byle are set by the MC6839 If any errors have occurred. Note that
each b it of the status byle ls a "sticky" bit and must be manually reset (written) by the
user. The floa ti ng point package writes b its Into the status byle but never clears existing
bits . This Is done so that a long calculation can be completed end the status need only be
checked once at the end.
7 6 5 4 32, 0
I x I 1Nx I tov luNoRl oz I UNF IovF I 10P l
Bil 0 Invalid Operation (also see Secondary Status)
Bit t Overflow
Bit 2 Underflow
B it 3 OMslon by Zero
Bit 4 Unordered
Bit 5 Integer Overflow
Bit 6 Inexact Result
Bit 7 Undefined, Reserved
1.4 TRAP ENABLE BYTE
If any bit of the trap enable byte la aet, It enables the floating point package to trap If that
error occurs . The bit position definitions are the same as for the status byte. Note that If
a trapping compare Is executed and the result ls unordered, then the unordered trap will
be taken regardless of the state of the UNOR bit In the trap enable byte.
7 6 54 3210
I .. I 1Nx I iov ~NoRl oz I UNF IovF 1ioP I
Bit 0 Invalid Operation
Bii 1 Overflow
Bit 2 Underflow
Bit 3 Division b y Zero
B it 4 Unordered
Bit 5 Integer Overflow
Bit 6 Inexact Result
Bit 7 Undefined , Reserved

5.5 TRAP VECTOR

If a trap occurs , the floating point package will Initiate a )ump Indirectly through the trap
address In the FPCB. An Index In the A accumulator then Indicates the trap .type. Trap
types are as follows:
0 =Invalid Ope ration
1 c: Overflow
2=Underflow
3 =Divide by Zero
C = Unnormallzed
5 =Integer Ollerflow
6 =Inexact Result

If more than one enabled trap occurs, the MC6839 Floating Point ROM returns the Index
of the highest priority enabled error. Index O, which Is an Invalid operation, ls the highest
priority, whereas, Index 6 (Inexact result) Is the lowest.

U SECONDARY STATUS

The floating point package writes a status Into this byte whenever a new IOP occurs. As
la the case with the status byte, It Is up to the caller to reset the "IOP type.. field.
76 5 4 3 210
.. I .. .. I 1pvalld ?peration Tn!e
Bits 0-<I represent the Invalid operation type field. These lour bits are encoded as shown
below.
D=No IOP error
1 .. SQuare Root of: a Negative Number, Infinity In Projective Mode, or a Not Normal·
lzed Number
2 = (+Infinity)+ (-Infinity) In Affine mode
3=Trled to Convert a NAN to Binary Integer
•=In Division: 0/0, Infinity/Infinity, or the Divisor Is not Normalized and the Dividend Is
Not Zero and Is Finite
5 =One of the Input Arguments was a Trapping NAN
Ei =Unordered Values Compared via Predicate Other Than = or •
7 = k Out of Range for BIN DEC or
p Out of Range or DECBIN
S= Projecllve Closure Use of +I-Infinity In Add or Subtract
8 = 0 x Infinity
10 =In Remainder arg2 Is Zero, or Not Norrnalized In arg1 Is Infinite
11 =Unused, Reserved
12 =Unused, Reserved
13 c Unused, Reserved
1~=Unused, Reserved
15=Tried to MOV a Single Denormalized Number to a Double Destination
16 =Tried to Return an Unnormalized Number to Single or Double (also called Invalid
Result In the Proposed IEEE Standard).
17-31 =Unused, Reserved
 SECTION I
USER INTERFACE

1.1 INTRODUCTION
There are two types of calls to the floal\ng point package: register calls and stack calls .
For register calls, the user loads the machine register with pointers (addresses) to the
operand(s) and to the result; the call to the floatl..i point package ls then performed . For
sta ck calls , the operand(s) Is pushed onto the oack and the call to the floating point
package Is performed. The result then replaces Ille operands on the stack after comple·
lion. The operand(s) must be pushed least significant bytes first; this ls consistent with
the other Motorola archite ctures In that the most significant byte resides In the lowest
address . The two types of calls took like:
General form of a register call: General form of a stack call:
load reg isters push arguments
LBSR FPREG registe r call lBSR FPSTAK stack call
FCB opcode FCB opcode
pull result
(,......
6 .2 OPERATION OPCOOES AND ENTRY POINTS
The sugl)esled mnemonics and the opcode values for the various operations available In
this floating point package are shown below (in opcode order).
Opcode Operation
Mnemonic Valuo Description
FADD 00 ' Add
FSUB 02 Subtiact
FMUL 04 Multiply
FOIV 06 Divide
FREM 08 Remainder
FSORT 12 Square Root
FINT 14 Integer Part
FFIXS 16 Float - Short Integer
FFIXD 18 Floot - Double Integer
BIN DEC 1C Binary Float - BCD String
FAB 1E Absolute Value
FNEG 20 Negate
DECBIN 22 BCD String - Binary Float
FFLTS 24 Short Integer - Float
FFLTD 26 Do- Integer - Float
FCMP IA Co,,..are
FPCMP IE Predicate Compare
FMOV IA Mow (or Convert) arg1 - Result
FTCMP cc Trapping Compare
FTPCMP 00 Trapping Predicate Compare

..,
rr~ The two entry points to the MC6839 are referred to as FPREG (register call) and FPSTAK
(stack call). Their addresses are:
FPREG" ROM starting address+ S3D
FPSTAK., ROM starting address+ S3F
The first S3C locations of the ROM contain a fixed size ROM header. The entry points for
the floating package are located In a branch table Immediately following this header.
Therefore, the addresses of the entry points will rema in constant for future versions of
the ROM .

1 .3 STACK REQUIREMENTS
When the MC6839 Floating Point ROM Is called by the user, local storage ls reserved on
the hardware stack by the floating point package. The Input arguments are then moved
from user memory to the local storage area, and are expanded into a convenient Internal
format . The operations use these " internal" numbers to arrive at an ..internal" result. The
"Internal" result Is then converted to the memory format of the result and returned (as
the result) to the user. For th is reason , the user must insure that adequate memory exists
on the hardware stack belore calling the MC6839 Floating Point ROM. The maximum
stack a izes that any particular operat ion will ever reQulre are:
reg ister calls 170bytes
stack calls 200
bytes

1 .4 CALLING SEQUENCE

1 .4.1 Revlster Cell

In this calling method the addresses of the arguments and the floating point control
block (FPCB) are passed In the register:
U :c address of argument 1
Y ~address or argument 2
X =address of result
O&address of FPCB

II an argument Is not used In a particular operation, It need not be Included. In monadic

operations, Y contains the address of the single argument. The resutt may be the same
address as either of the arguments . All registers will be restored on exit.

6-2
 Example of a position Independent call to the add routine:
LEAU arg1,PCR
LEAY arg2, PCR
LEAX FPCBPTR, PCR pointer to FPCB•
TFR X, 0
LEAX result, PCR
LBSR fpreg
FCB FADD
Example of a position Independent monadic call to the square root routine:
LEAY arg2, PCR
LEAX FPCBPTR,PCR
TFR X, D
LEAX result, PCR
LBSR FPREG
FCB FSORT

For some operations the arguments have slightly different meanings. See Appendix A for
details. All subroutines In the floating point package are re~ntrant and position tndepen·
dent. However, the caller must use caution to Insure that his call does not violate the
rules of r~ntrancy or position Independence. For example, each catling task should
have Its own FPCB to rema in re-entrant. Also, If In the previous examples load Im-
med iates had been used , rathe r than load effective address program counter relative, the
call ing program could not have been position independent.

1.4.l! Stack Call

In this mode the actual argument(s), not their addresses, and the address of the FPCB
are assumed to be on the top of the hardware stack and they will be removed and replac·
ed by the result on exit. II two arguments are on the stack, then argument 2 should be
above {lower address) argument 1. The address of the FPCB Is on the top of t~e stack
above the argument(s).

Example of a stack call to the add routine:

push argument 1
push argument 2
push FPCBPTR Pointer to FPCB
LBSR FPSTAK
FCB FADD
pull result

For monadic operations, arg2 contains the single Input argument and there Is no arg1 .
On return, the FPCB pointer and any other parameters are lost from the top of the stack.
The only object left on the stack alter an operation Is the result. For some operations, the
r arguments have slightly different meaning . See Appendix A for details.

~6ons-. 1'9Qutr.cl Mra H the cal*......_ NI call to Nm&ln poalOon ~Of*•• no LEAD in·
~On).
 APPENDIX A
OPERATION DESCRIPTIONS

A.1 INTRODUCTION

This appendix conta ins detailed Information cove ring specific operations and the ir re ·
Quire d calling seQuences . The operaHons are arranged In alphabetical order with 1 sum·
mary listing on the last page of this appendix . Detailed descriptions of the algorithms are
provided In Appendix B.

A.2 NOTATION

In describing each specific operation, symbols are used to Indicate the operation. Table
A-1 lists these symbols and their meaning . /l.bbreviations which are used tor the source
form, various reg isters , bits, b ytes, etc. are l isted In Table A·2.

Table A·1. Specific Operation Notation

A-1
..
t CS
IGE
"llNOEC
"OECB!N
'""""""'
l,.nctl II C.nv Set
Table A·2. Abbrowlatlon&

lr•""1'1 II Gru1e• ll'\lln or Eoual 10 Ze•o

l•l'lll'V fiol 11ng Pom1 10 ~, ~omg
o.cim.• $1nng 10 B •l'll ty f101 1m; Pomt
-
A.b5.olu1e V•h.ie ot an A rgvmen1
"fkOO
fCB
"fCMP
""'
fo•m Colis\1 1"11 Bvu tauemblet Di1eei1~ l
Co"'Pll•t Comp.1n two • •Qvme"lts , ,,o aeu COT'ld •t!O" COGe'l
"FOl\I °'"''°' n...on Ot1C • •goJ"T1C' "1 b y l 'lOlhe l
"FFlXO Fu. ~ CO'l...ertl 1 n 1 rg v me"1 from 1 floa tin g pem1 rwmtll'> wito 1 32·b<: bol'll•v 11'1\fier
" FF tX S f1• S"'Wlr COl'lveru S" l:Tpi..l"ne"11 hom I tio1 11"; 00<n1 r..rnbt · in10 a H>- bit bil'll•y 1me~·
'Ffl TD flol t Oo..rt>\f co" ..oert• 1 32--bt °"* v
1n1egt • 1n10 1 foal>l'>Q pcm: rr.r.un
"fh lS f.toa', ~c:cn....u1'6-blibina<yint~·l'TI0 1hor..r,,goom1 r~
"f lNT tntege• Pi n Fb111ng po1n1 1rg!Jf"oe"ll 11 con.,.ne:I 10 • tlolll"'Q pOll'l1 integt• g11
"fMO\I M~ MC>"ots 1 n 1 rw vmen1 10 the Te$"'!\ !w rtr> ' "'V ~ conwet"OfU'
•fM Ul M ut\opiy M ut1<:>1ies1'wo 11g'1f'rltn\1 1no1:ores1he1ewti
"fNEG ~If CNn;t tht 11;n o l 1n 1 rg um.e rit
f PCS fJOI : ""' Pom1 Conuo1 B•oct,
"fPCMP .... :1.=a1e Comot •t COTT1P11 •e l ,..,.c 1rgumel'lt5 1 nd 1 tt inns or o.utt1~ I ~·U.lf
FPREG R19islr C&!. f '1\I)· Po int
fPSTAt:. Sui :-l Ui·· f n1•v f' ool'I~
" FSOl\T SQ"""'' " 001 S 1o•u tt>e SQU1 1t 1001 01 1 •· e •g..r'>f' n1
" FS US s ...tm•=~
"FTClo' P Tr~~ Col'tlPll·t Cornoto•n rwo • •g.........en11 an cl ~ CO"tlfl>O"I coon 111:-s 01' uno•oe·e:
"FTPCMP lrape.~ P1eO•c.a1t C~·t CofTlpa·t ~ ,..,..0 • ·g~•"'d at!~ 0: c1oM!l1'1'T\i P'~1t ':ta..~ 0"· U"'OO·°"~
l£!S I:\ Birc" 10 S uti·oui ·~

A·2
 ABSOLUTE VALUE

Mnemonic: FAB

Operation: jarg2 1-result

D111crlpllon: Relurn absolute value of arg2 as the result.

Opcode: $1E

Precisions: All. The result will have the same precision as arg2. The precision is
specified In bits 5-7 of the FPCB control byte.

Register
Calling
Sequence : load X with address of result
load Y with address of arg2
load D with address of FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FAB

The result Is automatically returned to user memory. This calling seQuen ce

Is the same fo r all monadic calls.

Stack
Calling
Sequence: push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK= ROM start +S3F)
FCB FAB ' .
pull result

Only the result Is left on the stack alter return from the subroutine. This
calling sequence ls the same for all monadic calls.

A·3
 ADD

Mnemonic: FAOO

Operation: arg1 + arg2-result

Description: Add arg2 to arg1 and atore the result.

Opcode: soo
Praclalons: All. Both arg1 and arg2 must be of the ume precision. The result wlll also
be 1he same precision. The precision Is specified In bits f>-7 of the FPCB
control byte.

l\eglator
Ca\ilng
Sequence: toad X with the address of the result
load Y with the address of arg2
load U with the address of arg1
load 0 with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FAOD

The result Is automatically returned to user memory. This calling sequence

Is the aame for all dyadic calls .

Stack
Calling
Sequtnca : push arg1
push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK=ROM start+S3F)
FCB FAOO
pull result

Only the result Is left on the stack after the call . This calling sequence Is
the same for all dyadic calls.
 BINARY FLOATING TO
DECIMAL STRING

Mnemonic: BINDEC

Operotlon: arg2-BCD ltring with k significant digits

Deacrlplion: Convert a lloatlng point argument In arg2 to an unpacked BCD 1trlng in the
tesult. A parameter k is also passed to the routine to Indicate the number of
algnificant digits desired in the result (1 s ks9 for single; 1sks 17 for dou·
bie).

Opcode: S1C

Preclalona: Single and double results are delivered to the accuracy required by the pro·
posed IEEE standard. Extended resulto, however, are not necessarily more
accurate than double and may take considerably more time to compute .
The precision of arg2 is specified in bits S-7of the FPCB control byte. The
output BCD string Is a standard 26 byte BCD string of the form:
01 56 2425 '
se 4 Digit BCD Exponent sf 19 Digit BCD Fraction P

ae =sign of the exponent. 00= plus, $0F=mlnus.

sf= sign of the fraction. 00 =plus, $OF= minus.
p =number of fraction digits to the right ofthe decimal point (one byte).

All BCD digits are unp'acked and ilghl justffied In each byte:
7 0
DODO

Since some special ftoaling point values have no obvious BCD equivalent,
the sign of the exponent (se) ts used to Indicate these special cases:

ae = 00 =regular positive number.

z.OF:regular negative number.
•DC= NAN. The four digit BCD exponent contains the unpacked hex
address that was In the NAN.
c OB= minus Infinity. All remaining bytes of the BCD string are zero.
a DA= plus Infinity. All remaining bytes of the BCD airing are zero.

Even though these apeclal numbers can be created as output, they are not
legal Inputs to OECBIN.
 Reg later
Calllng
Sequence: load X with address of result
load Y with address of arg2
load U with k
load D with address of FPCB
LBSR FPREQ (FPREG "ROM llart+S3D)
FCB BINDEC

The resultant BCD string ls automatically returned ta the uaer.

Stack
C11llng
Sequence: push arg2
push k
push address of FPCB
LBSR FPSTAK (FPSTAK" ROM start+ $3F)
FCB BINDEC
pull BCD string

(,--...
 COMPARE

Mnemonic: FCMP, nCMP, FPCMP, nPCMP

Oporollon: arg1 - arg2 (rel urn condlllon code register or alflrm/dlsalflrm a predicate)

011crlpllon: Compare arg1 with arg2. Both arg1 and arg2 moy be of different precisions.
Two basic types of compares are provided. One returns condition codes In
the condlllon code regi ster to the user to Indicate the result of the com·
parlson. The other Is given a predicate (e.g., Is arg1 equal to arg2?) and
either affirms or dlsalfirms the predicate.

1) Condition code compares:

FCMP
Compare arg1 with arg2 and aet the condlllon codes. Do not trap on
unordered unless the trap on unordered bit (UNOR) Is HI In the trap enable
byte of the FPCB.
ncMP
Compare arg1 w ith arg2 and set the condition codes. Trap If the unordered
conditions occur regardless of the state of the UNOR bit In the trap enable
byte of the FPCB.
The Intermediate resu lt of any comparison can yield one of five possible
results: arg1 Is> arv2, arg1 ls<arg2, arg1 "arg2, arg1 •Hrg2, or arg1 can-
not be compared to arg2 (unordered). The unordered condition occurs when
a coi>lparlson Is made between a NAN and anything else or when Infinity Is
compared to anything except Itself In projective closure. Thi• Intermediate
result Is then used t~ aet the condition codes as follows:
ll11ult N Z •V C
> 0 0 0 0
< , 0 0 0
·o 1 o o
unordered O O O
The remaining condition code register bit• (E, F, H, and Qara unaffected by
compare.

This allows the following signed bronches to be taken Immediately follow·

Ing the return from FCMP or nCMP.
Condition Branch Taal for Branch
> (L)BGT (not (N • V)J and (not Z)" 1
lt (L)BGE not (N•V)"1
< (L)BLT not (N•V)"O
s (L)BLE not(NeV)and(notZ) .. o
(L)BEQ Zc1
"' (L)BNE ZaO
unordered ~CS Ca1

. A·7
It FCMP and the unordered trap Is disabled, a BCS should Immediately
follow the call and precede any of the other branches:
LBSR fpxxx
FCB FCMP
BCS unordered
BGE label
Note that this Implementation ot compare conditions (as defined by the
proposed IEEE standard) does not support the dichotomy principle normal-
ly associated with Integer compare. For example, BGE Is not necessarily
the Inverse of BLT (the result may be unordered too). Compiler wrtters must
take care not to switch the condition ot a branch during code generation.

2) Predicate Compares
FPCMP
Compare arg1 with arg2 . Either affirm or disaffirm an lnpu1 predicate. Do
not trap on unordered unless the UNOR bit Is set In the trap enable byte of
the FPCB. For register calls the Z-blt In the condition code register Is set to
1 tor affirm (true) and set to 0 tor disaftirm (false). For stack calls a byte of
2eros ls pushed on top ot the stack tor true and a byte ol ones (SFF) is push-
ed for false.

FTPCMP
Compare arg'1 with arg2 . Either affirm or disaffirm an Input predicate. Trap
If the unordered condition occurs regardless of the state of the UNOR bit In
the trap enable byte of the FPCB . Forregister calls the Z·bit In the condition
code register Is set to 1 tor affirm (true) and set to 0 tor disaffirm (false). For
atack calls a byte of uros Is pushed on top of the stack tor true and a byte
of ones (SFF) Is pus~ed for false.

Unordered conditions 'occur when a comparison Is made between a NA.N

and anything else or when Infinity Is compared to anything except Itself in
projective closure. -

The predicate to be affirmed or disaftirmed Is passed to the compare In the

parameter word:

Predicates 876 ~32 0

I 0 I arg1 I 0 I arg2 I
 The predicates are >, ><, <, and unordered, or a reasonable combination
of these (e.g., > "'). The Intermediate ,.suit of a predicate compare Is
either > , s , <,or unordered . The table below gives the predicate affirmed
or dlaalflrmed for each poaalble Intermediate r.sult.

lntormtdlatt Rnult Prtdlcttn Alllrmtd

less than < s.
equal .,5,.
greater than·
> "'.
unordered unordered

lntermtdlato Rnult Pradlcatu Dinltlrmtd

less tha n c it: > unordered
equal < > unordered •
g reater tha n c s < unordered
unordered <Seit:><>
The resull rel urned 101 affiimed Is a zero byte and for disaffirmed It Is a - 1 or SFF byte
for a stack ca ll. For a reg iste r call, Z= 1 II the predicate ls affirmed .

Opcodes: FCMP=SBA
FTCMP=SCC
FPCMP=SBE
FTPCM P =SDO

Precision': S ince the compares allow arg'1 and arg2 to be of different preeisions, a
pa ramete r word must be passed on each call to any compare. The format of
the pa ramete r word Js:
15 11 Predica tes 876 •32 0
I 0 I arg1 I 0 I arg2 I
Where arg1 or arg2 Is defined :
000 Single
001 Double
010 Extended
011 Unused (defaults to extended)
100 Unused (defaults to extended)
101.111 Undefined
Since the ptrameter word spe cifies both arguments of the compare, bits
5-7 of the control byte of the FPCB do not affect the compare Instructions.

A·9
ti.glater
Calling
Sequence: load X with the parameter word
load Y with address of arg2
load U with address of arg1
load D with address of FPCB
LBSR FPREG (FPREG "'ROM start+ S3D)
FCB <Opcode>
The res ult ls returned In the cond ition code register. It Is tither a aetting of
the cond ition code register (condition code call) or the Z bit ls set to 1 for af·
firm and Z=O for disaffirm (predicate cal ls).

Stock
Calling
Soqutnco: push arg1
push arg2
push parameter word
push address of the FPCB
LBSR FPREG (FPREG =ROM st art+ S3F)
FCB <Opcode>
pull result

If the compa re Is a condition code compare , no result 15 delivered on the

1tack - only the condition codes are returned In the condition code
reg ister. 1f the compa re Is a pred icate compare , a 1.tlyte result I& returned
on top of the st ack. The resu lt = Ofor affirmed and -1 (SFF)for disaffirmed.

A-10
 DECIMAL STRING TO BINARY FLOATING POINT

Source
Fonn: OECBIN

Oper1llon: BCD string-floating point result

o..crtptlon: Conven I atandard BCD airing Into I binary floating point result. The Yllue
"p" In the 1t1ndard decimal string Indicates the number of digits of the
fraction that ore lo the right of the decimal point.

Opcode : $22

Proclalons: The precision of the result ls defined by bits S-7 of the FPCB control by1e.
The Input BCD string Is 1 atandard 26 byte BCD •.Iring of the form:
0 , 5 6 24 25
se 4 Digit BCD Exponent sf 9Digit BCD Fraction p

se =sign of the exponent. 00 =plus, SOF =minus (one byle).

sf= sign ot the fraction . 00 =plus , $OF= minus (one byle).
p =number of fraction d igits to the right of the decimal point (one byle).

All BCD digits ore unpacked and right justified In each byle:
7 0
00 0,0

The byle ordering of the friction ind exponent Is consistent with 111
Motorola processors In that the most significant BCD digit ls In the lowest
memory address .

l\egtllor
Colling
Sequence: load X with the 1ddress of result
load U with the 1ddress of the BCD Input airing
lo1d 0 with the 1ddress of the FPCB
LBSR FPREG (FPREG.,ROM ltart+$3D)
FCB OECBIN
The result Is automatically returned to the user.

Stock
Colling
Sequence: push the BCD airing
push address of the FPCB
LBSR FPSTAK(FPSTAK.,ROM 1tart+S3F)
FCB DECBIN
pull f101tlng point result

....,,
 DIVIDE

Mnemonic: FDIV

Operttlon: arg1/arg2-result

Ot1crlptlon: Divide arg1 by arg2 and store the result .

Opcode: S06

Procl1lons: Both erg1 end arg2 must be of the same precision. lhe result will also be
the same precision. The precision Is specified In bits 5·7 of the FPCB con·
trol byte .

Register
Calling
Sequence: load X with the address of the result
load Y with the address of arg2
load U wl1h the address of arg1
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM st art + $30)
FCB FDIV

The resu lt Is automatically returned to user memory. The calling sequence

Is the same for all dyadic calls . ·

Stack
Calling
Sequence: push arg1
push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK =FIOM start+ S3F)
FCB FOIV
pull result

Only the result Is telt on the stack alter the call. This calling sequence Is
the same !or all dyadic calls .

(r--.,

A·12
 FIX

Mnemonic: FFIXS, FFIXD

Oporallon: arg2-blnary Integer result

Ducrlpllon: Converts arg2 from a floating point number Into a 16· or 32-bit binary In·
teger. If arg2 Is lnlinlty, then the integer returned Is the largest or smallest
twos complement Integer.

Opcode: FFIXS = $16 (16·blt Integer)

FFIXD = $18 (32·blt Integer)

Preclolons: Same as absolute value except that the result will be a 16- or 32·blt Integer
as specified by the opcode.

Rog loter
Colling
Sequence: load X with the address of the result
load Y with the address of arg2
load 0 with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FFIXS or FFIXD

The result Is automatically returned to user memory. The calling sequence

Is the same for all monadic calls.

Stock
Colling
Sequence: push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK =ROM start+ S3F)
FCB FFIXS or FFIXD
pull result

Only the result Is left on the stack after return from the subroutine. This
calling sequence Is the same for all monadic calls.

A·13
(
FLOAT

Mnemonic: FFLTS, FFLTD

Operollon: Binary lntegery arg2-floatlng point result

Ooscrlptlon: Converts a 16- or 32-blt Integer Into a floating point result.

Opcode: FFLTS = S24 (16-blt binary Integer)

FFLTD = S26 (32·blt binary Integer)

Pr1cl1lon1: All. The size of the binary Integer Is specified In the opcode. The precision
Is specified In bits 5-7 of the FPCB control byte.

Register
Calling
Sequence: foad X with the address of the result
load Y with the address of arg2
load D with the address of the FPCB
LBSR FPREG (FPRET = ROM start+ $30)
FCB FFLTS or FFLTD

The result is automatically returned to user memory. The calling sequence

Is the same for all monadic calls.

Stack
Calling
Soqu1nc1: push arg2
push address of FP9B
LBSR FPSTAK (FPSTAK =ROM s.tart + S3F)
FCB FFLTS or FFLTD
pull result

Only the result Is left on the stack after return from the subroutine. This
calling seQuence Is the same for all monadic calls .
 INTEGER PART

Mnemonic: FINT

Operellon: Integer part (arg2)-lloaling point result

Ducrlpllon: The floating point argument In arg2 ls converted to Its floating point Integer
part. This differs from FIX which returns a binary Integer. Integer part
returns a floating point number. For example, lhe Integer part of 3.14159 is
3.00000 If the rounding mode Is round lo nearest.

Opcode: $14

Precisions: All. The result wlll have the same precision as arg2. The precision ls
specified In bits S.7 of the FPCB control byte.

Register
Calling
Sequence: load X with the address of the result
load Y with the address of arg2
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FINT

The result Is automatically returned to user mernt'ry. The calling sequence

Is the same for all monadic calls.

Stack
Calllng
Sequence: push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK=ROM slart+S3F)
FCB FINT
pull result

Only the resull Is left on the stack alter return from the subroutine. This
calling sequence Is the same for all monadic calls.

A·15
 MOVE

Mnemonic: FMOV

Operation: arg2-result

Description: For register calls, the move instruction moves arg2 to the result. Since
moves allow mixed precisions, they can be used to convert a number from
one precision to another during the move. For stack calls, the move Is
essentially a "convert precision of stack top" operation.

Opcode: S9A

Precisions: The move allows arg2 and the result to be of different precisions. In order to
specl1y the two precisions, a parameter word must be passed on each call
to move. The form of the parameter word Is:
15 8 6 • 2 0
00000000 j0 j arg2 j0 j result I
Where arg2 (source) or result (destination) is defined:
000 Single
001 Double
010 Extended
011 Extended round to single
100 Extended round to double
101-111 Illegal

Since the parameter word specifies both arguments of the move, bits 5-7 of
the FPCB control byte do not affect the move operation.

Register
Colling
Sequence: load X with the address of the result
load Y with the address or arg2
load U with the address of precision parameter word
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FMOV

The result Is automatlcally returned to user memory In the precision

apeclfied In the parameter word.

A·16
Stick
Colling
S.qu1nco: push arg2
push precision parameter word
push address of FPCB
LBSR FPSTAK (FPSTAK=ROM atart+S3F)
FCBFMOV
pull result

Only the result Is left on the stack alter the operation. The result has the
precision (and size) specified In the precision parameter word.

A·17
 MULTIPLY

Mnemonic: FMUL

Operation: arg1 xarg2-result

Ducrlpllon: Multiply arg1 and arg2 and alore the result.

Opcode: SO.C

Precisions: arg1 and arg2 must be of the same precision. The result w111 also be the
same precision. The precision Is specified In bits 5-7 of the FPCB control
byte.

Register
Calling
S.qu1nc1: load X with the address of the result
load Y with the address of arg2
load U with the address or arg1
load 0 with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FMUL

The result ts automatically returned to user memory. The calling seQuence

Is the same for all dyadic calls.

Stack
Calling
Sequence: push arg1
push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK =ROM start+ S3F)
FCB FMUL
pull result

Only the result Is left on the stack after the call. This calling sequence Is
the same for all dyadic calls.

A·18
(r-- NEGATE

Mnemonic: FNEG

Oparallon: arg2-result

Descrlpllon: Negate arg2 by changing the sign and store as the result.

Opcode: $20

Precl1lons: All. The result will also be the same precision as arg2. The precision Is
specified In bits 5-7 of the FPCB control byte.

Register
Colling
Sequence: load X with the address of the result
load Y with the address of arg2
load 0 with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FNEG

The result Is automaticall y returned to user memory. The caning sequence

( r"' . Is the same for all monadic calls.
'-
Stock
Colling
S.quanco: push arg2
push address of FPCB
LBSR FPSTAK (FPSTAK =ROM start+ S3F)
FCB FNEG ', .
pull result

Only the result Is left on the stack after the call. This calling seqoence Is
the same for all monadic calls.

A·19
 REMAINDER

Mnemonic: FREM

Oper1tlon: arg1 -(arg2 x n)-result [where .n =Integer part of (arg1/arg2) In round

nearest]

Description: Finds the remainder of arg1/arg2 and stores It as the result . Note, as defin·
ed by the proposed IEEE standard, th is Is not the same as " modulo." For
example, the remainder of 813 Is -1 not 2. This can be seen by substituting
8 and 3 In the equation In the operation description:
n - Integer part of 813 = 3 (round nearest)
remainder= 8-(3 x 3) = -1
This form of remainder was chosen for a number of reasons. First, it Is the
remainder most useful for scaling the Inputs to trigonometric subroutines.
Secondly, alt other remainder type functions may be easily derived from
this one. For example, the "modulo" function Is found by taking:
Z= remainder (arg2/arg1);
II 2<0thenZ=Z+arg1 .

Opcode: SOB
(
Precisions: erg1 and arg2 must be of the same precision. The result will also be the
same precision. The precision Is specified In bits 5-7 of the FPCB control
byie.

Reg later
C111ing
S.quenc1: load X with the address 'of the resuit
load Y with the address of arg2
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FREM .

The result Is automatically returned to user memory. The calling sequence

Is the same for all dyadic calls.

Stick
C1lllng
Sequence push arg2
push address of FPCB
LBSR FPST .t.K (FPST .t.K =ROM start+ S3F)
FCB FREM
pull result

Only the result Is left on the stack alter the call. This calling sequence is
the same for all dyadic calls.
 SUBTRACT

Mnemonic: FSUB

Operation: arg1 - arg2- result

Dtscrlptlon: Subtract arg2 from arg1 and store the result.

Opcode: SOF

Precisions: All. Both arg1 and arg2 must be of the same precision. The result will also
be the same precision. The precision Is specified In bits S-7 of the FPCB
control byte.

Register
Colling
Sequence: load X with the address of the result
load Y with the address of arg2
load U with the address of arg1
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ S3D)
FCB FSUB

The result Is automatically returned to user memory. The calling sequence

Is the same for all dyadic calls.

Sto~k
Colling
Sequence : push arg1
push arg2
push address of FPCB
LBSR FPST AK (FPSTAK: ROM start+ S3F)
FCB FSUB
pull result

Only the result Is left on the stack after the call. This calling sequence is
the same for all dyadic calls.

A·21
 SQUARE ROOT

Mnemonic: FSORT

Operation: Square root of arg2-result

Description: Returns the square root of arg2 as the result .

Opcode: $12

Precisions: All. The result will also be the same precision as arg2. The precision Is
specified In bits 5·7 of the FPCB control by1e.

Register
Calllng
Sequence: load X with the address of the result
load Y with the address of arg2
load D with the address of the FPCB
LBSR FPREG (FPREG =ROM start+ $30)
FCB FSORT

Jhe result Is automatically returned to user memory. The calling sequence

Is 1he same for all monadic calls.

Stack
Calllng
Sequence: push arg1
push address of FPCB
LBSR FPSTAK (FPSTAK =ROM start+.$3F)
FCB FSQRT
pull result

Only the result Is left on the stack after return from the subroutine. This
calling sequence Is the same tor all monadic calls. ·

A·22
 -
Table A·3. M C6839 Celling Sequence and Opcode Summary Table

Fii.DD"""'"" ""' U- A ddr , ol A r g~I ll P11Sl"IAIQ\l!'r>tn1 f1

FSUB
'°' v -Addr o1 A•QLITTle'nl 12 PU5nArgvmen1 12
fM UL
fO IV ""
S06
a- Add• o1 fPCB
ll. - Add• o lRHult
LBSR FPREO
Pus.,~·
LBSSI fPSlAI(
'-CB < OPCOOt>
ol fPCB

FCB <oPCOCk> Pull AH..>:

FRf.M
FSORl
fl,,..,
.,,""' Y-AdO • o l A1g<11T>ent
o- A.od· ot f PCB
P.,s.,A•g-"1
Pl.IS" Ao o• ot FPCB

FFIXS
HI XO
"'
"'
X - AOO • 0 1 Res.uti
LBSR FPREG
FCB <OPCooe>
LBSfl FPS1AK
fCE < ~oat:>
P.,ll RHut:
•••
FNEG
"'
,,,
"'
FHTS
ff LTO
FCMP
nC MP
FPCMP
....."',
s2.:

ICC
u - AOO• ot
v - AdO• ot
0-AOO t
A~gurne n1
Arg u~"'
ot FPCB
I 1
12
p.,,.+> A.•g...-nel'll l l
P...s.,A.rg~1'2
P...s"- P••1-nttr.W:i•e1
nP Ct.!P 100 x -P111rne1e•W::i•o PUS'I AO' ' ot fPCli
LBSR FPR(G LBSR FPS1A11:,
FCB <oocode > fCB < OPtOClt>
Pu1• Rnui": Iii poeO·~:e c~·e i
NOTE Ret.ull 1t1.,•r.eo '"' 11'\f' CC •tg1~ · Fo< NOTf Rti""' rttll""t'o ""Tt>e CC •ew-s•e· tc·
o•tO•Cllt C0"'4ll't~ 1ntZ· B·1 1$H: .1 P't0·t.11t •egui.• cornDll•H Fo• pte01:-.111ecg,...pre~ 1 o·-EI
,, 1H1• med Clel·td .t Cl1Hli 1•mc::1 b1~ 1e~ "rt1.. meo on 11'\e 1ot 01 troe s~1:~
lhf !Hul:llft'O •I 1t11•rnec rill - US~ f ,•
a ·sa":•or.e:i .
l: P1t:'5C"'" P1r1-ne1t ' Vo::>'O P us• A •g~"I
V- AO::i · g! A·p~": PurP•K>S>O" P1·1~1e· \\':i•c
0-AOCI• cl FPC6 Pust-~· olfPCB
x. -AoCI· o'Res....1 LBS'! fPSlAll:,
LBSR FPRlG FC! U!.OV
FCB FMOV Pur:~
11( u - i." o1 O•Qi'IS"'ftSUlll
Y- AOd• ot A•gufne nl
0 -Alld• ot FPCB '
/II. - Add• ot Oec•P!'ll l Resu11
lBSR fPREG
H:B B1NDEC
·-·
P...s•. Afgumen1

P...s., Add• ot FPCB

LBSR FPSlAK
f.C6 811\0EC
Pu" BCOS1,.ng
OECB 1t1. u - A.0111 ol BCD ino .. ~ S111ng Pusl'I Ami· of BCD tnou~ S11ni;;
0 -Add• of FPCB P...sl'I AlSttl ot fPC B
x -AdOr ot 9,.,,.,, Res ut1 LBSR FPSlA.K
LBSR FPREG fCB OECB lh.
FCB OECB lh. PuP. e,,...,, Rnuti
1.-.1. • •g.,....,a e re p...sri.e:i O" tl'le si.acl 1..s1·Stgn1lit1!'\t bV'IU t.111 s o O\I: tht tltg ..·Ol'oe' tivte a. • lways cusnec 1111 , .,Cl rn1ou ,,. ~"f
liowH! l :l0 1 H~
1En11, pomu to the MC6839 a •e cletoneo es 1 0110~
fPREG • RO~ 111 11 ~ sJri
FPSlAK • ROM stlfh sJr

A·23/A·24
 APP ENDIX B
APPLICATION EXAMPLE
OF TH E QUADRATIC EQUATION

This appendix provides an appllcation eumple using the MC6839 Floating Point ROM.
The program shown below Is one that finds the roots to quadratic equations using the
classic formula:
-b:o:~
2a

Note that the program uses a standard HI of macro Instructions to set up the
parameters In the correct calling 1equence1. Perhaps the easiest way to program
MC6839 Floating Poi nt ROM Is through the use of these macro Instructions. Errors are
reduced because, once the macro Instructions are shown to be correct, their internal
details can be ignored allowing the programmer to concentrate only on the problem at
hand.

8-1
(1
• HERE JS A SJ•lPU: t:XAMPL£ JNVOLVJI'{; TH£ QUADRl\TIC t:QUATIOtl THAT
• SHOULD SERVE TO JLLIJ~"TAATE niE USE OF TH£ 1Cb03~ JN AN Al:l\JAL
• APPLICAn~.

• LINKJN:; IJJ/lllER DEFINITIOtlS

XOEF OUAD

XREF FPl!ffi

• RMBS FOR T"riE OPERA:JDS, BINARY 'I'O DEClt-i.tU. Cc:t-.'VEHSICIJ BUFFERS,

• AND THE FPCB.

ACOEFF R"lll 26 COEFFICIE"1' A IN AJCi + BX + C

BCOEFF RMB 2b CO£Ff'IC1"'1T I!
CCOEFF RMB 2b COEffICI"'1T C

REGl RMB REGISTER 1

REG2 R".B REGISTER 2
REG3 Rl'.B REGJSTEH 3

Fl'CB RMB FLOl\TING POil>'T CO>'TROL BLOCK

Ti..U FCS S40,0U,.Ou,ou FLOl\Tlr-G Pl'. COOSTANT TWO

FOOR FC8 $40,StW,OU,OO fUJR

.
• HERE All£ THE EOUl\TES ANO MACRO DEFINITIOtlS TO AC<.'O'IPA-;\' TH£
• OUADRl\TIC EOUl\TIOtl EXA...,PLE OF AN ICbOJ~ APPUCATI~ •

ND EQU DD , OPC'OOE VAUJES

SUI! EOU vi
MU~ El1ll vq
IJIV EOU D6
SQH"r ~\.1ll $l2
ABS EOU $IE
NEG EQU SW
BNIX: EQU SIC
OCl!N £QU $22

• Ml\CllO DEt"INITIONS

• n::ALL Si:TS UP A M(JW)lC REGI~-rt:R CALL.

'l r • USAlit:: ~ <INPUT OP!:RAND>,<OPERl\TlOO>,<RESULT>

B-2
 L&\Y \U,FCR POINTER TO 'I'll£ INPUT AAGUMlNI'
LEAX IPCB,IO: POltn'ER TO 'I'll£ FLOl\TING POINT CXNIK>L BLOCJ<
Tm X,D
u:AX \2,FCR POl~'l'l:R
TO 'n!E R!SULT
LBSR fl'JUI; CALL TO 'I'll£ 1'1:6839
FCB \l C»'COI)£

• OCALL SE:TS UP A DYADIC REGISTER C>.U.

• USl\GE: OCALL <AAGl!'ll:NT U>,<OPER/\TICN>,<AAGU~.!NT 12>,<RESULT>

IDJ.I \0,FCR POINTER TO AAGUl'l!Nr 11

!D.Y \2,FCR POINTER TO AR;Ul'l!Nr 12
L£AX FPCB,~ POINTER to 'I'll£ FLOl\TING POINT CCN'l'ROL Bl.DO<
TFR X,D
Ll:AX \) ,PCR POINTER TO TH£ RESULT
LBSR FPREG C>.U. TO T"r!E l'Cb839
FCB \l Ol'COOE

DECSIN llACR

..
• D£CBIN SE:TS UP .A REGISTER C>.U. TO Tll£ DECll'lllL 'IO BllWlY COO\IERSICN FUNCTICN •

• IJSAG£: D£CBIN <B:D S'JRING>,<SINARY RESULT>

L&W \0,PCR POINl'ER TO TH£ BCD INPUT S'JRING

u;,a.x FFCB I FCR POINTER TO THE !"UV.TING POINT C!Nl'ROL BLOCJ<
TFR X,D
LEAX \l,PCR POltm:R TO 'I'll£ RESULT
LBSR FPREG Cl\LL ro TK£ 1'1:6839
FCB llt:BI' OPCOOE

BINOEX: llACR

• BINDEC SE:TS UP A REGISlU CALL 'IO 'I'll£ BINARY TO DECll'lllL CONVERSICN FUNCTIOO.

• IJSACE: BlllDEC <SINAAY INPUT>,<Bal RESULT>,<I CF SIGNIFICANT DIGITS RESULT>

I.DU \2 f CF SIGNinCANT DIGITS IN Tl!£ RESULT

L&\Y \O,PCR POINTER 'IO 'I'll£ BllWlY INPUT
LEAX FPCB, PCR POINTER TO Tl!£ FLOl\TING POINT CXNIK>L BLOCJ<
~ X,D
LEAX \l,PCR ___ ______ _ POINTER 'l'O Tl!£ BCD R!SULT
-2-
 LBSR FPREX:; CALL TO THE MC6839
FCl! BNDC OPCOOE

.
QUAD

I.re
EQU

ISbFFF
•

INITIALIZE THE STACK POINl'Ell

LF>.X FPCB,PCR
I.DB f4
lo\'HILE B,CT,10 INITIALIZE STACK FAA-IE TO
DECB sI,,,;;LE, RC1JND NEAREST.
CLR B,X

• CO#l:HT THE lNPtrr OPl:RJ\.-ai FRO'< BCD STRI,,,;;s 10 THE 1"TERNAL

* SINGLE RINAAY F.:>RM .
OECBIN ACOEFF ,ACOEFF
OECBIN &...""OE.FF ,SCOOT
DECBIN CCOEFF ,CCOCFF

.
·• No.< START THE ACTUllL CALCULATIOOS FOR THE QUAI:AATIC EQUllTION

OCAll 8COEFF ,MUL,BCOEf'F ,R.EX;l CALCUIATE e-2

OCALL ACOEFF ,MUL,CCOEFF ,REXi2 CALCUIATE l\C
OCALL REX;2,MUL,FOJR,Rffi2 CALCUIATE V.C
ICALL REX;! ,SUB, RIXi2 ,JUX;l CALCUIATE e-2 - 4l\C

.
• CHECK RESULT or e-2 - 41\C TO SEE IF noors
.
ME REAL OR Il'W>INARY

SIGN IS POSITIVE; ROOl'S RF.AL

REI:il , SOnT, RIX;} CALCULATE SQRT ( e-2 - 4AC l

. '
DCAl.L
ACOEFF,MUL,"I\\t>,RIX;2
BCOEFF I NDJ' BCOEFF

BCOEFF,ADO,Rml,RmJ
CALCUIATE 2A
NffiATE B

CALCUIATE -B + SORT ( e-2 - 41\C l

DCAl.L REX:;J,DIV,RJ:::;2,Rm3 CALCUIATE (-B + Sc;RT( e-2 - 4AC ll/2A
BINDEC RffiJ,l'.COEFF,15 ca-VERT RESULT TO DECIMl\L

0C>.LI. BCO£FF ,SUB,R!r.l ,REG3 CAL!lJIATE -B - s~ c e-2 - v.c l

DCA1.L RD;),OIV ,RII;2,Rn:;3 CALQJIATE (-B + S;;RT( e-2 - 4AC ll/2A
BINDEC RffiJ,BCOEFF ,t5 ca-VERT RESULT TO DECIMl\L

Lill\ ISFF SllmNAL SIGNAUN; 'l111'.T ROOTS AAE REAL

STA CCOEFF,FCR

ELSE SIGH IS on:;,t,TlVE; ROOTS 1>11\GINAAY

M:AU. REXil ,MS ,RECl w.r.E SIGH POSITIVE
f'l:AU.. REX;l, SQRT ,Rml CALOVUt: ~ ( S-2 - VIC l
(v-- OCALL ACOEFF,MUL,"rt.10,REG2 CALCU!ATI: 2A
t:cALL R!Xil ,DIV I RD'.;2 I RECl CALCU!ATI: ( SQRT ( s-2 - 4AC ))/2A

IX:l\LL BCOEF'F ,DIV ,R£C2,R£C2 CALCU!An: -tira.

. l'CAU. FUI:;2,NEXi,R£C2

BINDEC RIX:! ,BCOEFF ,15 cruvi:RT -f3/2A TO DECIOW.

l!IND~'C Rll'.>2,ACOEFF, 15 CDNVERT ( SQRT ( s-2 - 4AC 11 /2A

CUI CCOEFF, PCR SENTIAAL SIGAALIN:; IP'>AGIIWU' ROOTS

DIDIF

NOP
NOP
-4-

('
 APPENDIXC
DETAILED DESCRIPTION OF OPERATIONS

C.1 INTRODUCTION

This appendix contains detailed algorithmic Information for each operation. Some Im·
plementation Is also given to help explain how the MC6839 Floating Point ROM operates.

C.1.1 Argument Typo Motrlx

In order to speed up execution of the operations, tables are used to define special ac-
tions required for most operations. That Is, most operations require special handling of
values such as + 0, -0, Infinities, etc . For monadic opera1ions, the type of arg2 is used
to index Into a one dimensional table . The index is determined by the type of argument.

Index
(·~ Normalized 0
Zero 2
arg2 Infinity 4
NAN 6
Not Normalized 8
For dyadic operations, the type of bo!h arguments d~termlne the Index.

erg2
Normalized Zero Infinity NAN Not Normalized
Normalized 00 02 04 06 08
Zero 10 12 14 16 18
arg1 Infinity 20 22 24 26 28
NAN 30 32 34 36 38
Not Normalized 40 42 ~ 46 48

The Index Is used by each operation to jump Indirectly through a table of values that
specifies the offset from the start of the ROM to the routine to be executed.

C.1.2 Rudlng The Metrlx Table

Argument type matrix tables are used In the discussion of each operation which follows .
An entry In the table that contains "arg1 " or "arg2" means that the operation will return
l\. ,---., that argument as the result and that no other processing Is necessary. A letter In the

C-1
 matrl• Indicates tha t the operati ons specified In the paragraph with that letter wlll bee•-
ecuted to ca lculate the result. An uample table and e•planatlon Is given below:

z
Normalized a
Zero erg2
arg2 Infinity c
NAN arg2
Not Normalized b

In th is eumple, If the Input argument (arg2) Is normalized, Infinity, or not normalized,

then refer to a, b, or c (of that part icular paragraph) respectively. If the input argument is a
NAN .or zero, then return that NAN or zero (arg2) as the result .

In the following operation , description "Z" Is used to represent the floating point result of
an operation and "I" Is used to represent an \nteger result.

If a trapping NAN Is one of the operands (arg1 and arg2) and the Invalid operation trap Is
enabled, then an Invalid operation (=5) tra p will be taken before the operation begins
and, hence, the matrix table will not be used. Trapping NANs can be used by the user to
create new or spe cial data types or to provide special handling .

If "NAN " appears I~ the table as the result , It implies that a new NAN Is created. The
MC6839 Floating Point ROM will return the address of the Inst ruction Immediately
following the operation that caused the NAN to be generated. Since the NAN i~ a new
NAN , the "d" (double NAN), and '1" (trapping NAN) bits will be set to zero. See Section 2
for NAN details .

The final step for most arithmetic operations where the operands are well behaved In-
cludes checking for underflow, lnvaild'Operatlon, round ing, and overflow. In the operation
descriptions, the following fun ctions and procedures are used In algorithms without
detailed explanations. For clarification, calls to these procedures and function& are
always In upper case in the description of the operations. The functions and procedures
used are:

CKINVALID Check for Invalid result .

OVERFLOW Function. Returns true If overflow occurred.
UNDERFLOW Function. Returns true If underflow occurred.
OVFLNO_TRAP Handles overflow when traps are disabled.
SUB_BIAS Handles overflow when traps are enabled by subtracting a
bias.
UNFL_NO_TRAP Handles underflow when traps are disabled.
ADD_lllAS Handles underflow when traps are enabled by adding a
bias.
ROUND Does correct rounding .

l..._ " Detailed descriptions of the algorithms used for these functions and procedures are In
Appendix D.

C-2
( -
C.2 ADD (FADD), SUBTRACT (FSUB)

Z=arg1 + arg2; Z= arg1 + (- arg2)

Opcode= $00 (FADD)
Opcode= $02 (FSUB)

arg2
Normalized Zero lntinlh NAN Not Normalized
Normalized b b arg2 arg2 b
Zero b a arv2 arg2 b
arg1 Infinity arg1 arg1 c arg2 arg1
NAN arg1 arg1 arg1 m arg1
No1 Normalized b b arg2 arg2 b

..
-0
arg1+
"-'OC.L.::....JL...;...;;,..

d= + 0 in rounding modes RN, RZ, RP

- 0 in rounding mode RM

C-3
 b.
1) Align binary points of arg1 and arg2 by unnormallzlng the operand with the smaller
exponent until the exponents are equal. Note If both operands are unnormalized.
2) Add the operands In Internal form.
3) If arithmetic overflow occurs, right shift fraction one bit and Increment exponent.
4) If all bits of the unrounded result are zero, then
=
sign (Z) +In rounding modes RN, RZ, RP
sign (Z) =-In rounding mode RM
If either arg1 or arg2 was normalized after step 1, then exponent
(Z) =most negative value (I.e., true zero).
Else (0 Not all bits are zero•)
If, after step1, both operands were unnormalized,
then go to step 5.
else
Normalize the result, If necessary, by shifting left while decrementing
the exponent until n = 1.
Zero or s may be shifted Into r from the right.
5) If UNDERFLOW then
If trap enabled then
ADD_BIAS
ROUND
else
(r- UNFL_NO_TRAP
end if
else
ROUND
CKINVALID
If OVERFLOW then
If trap enabled then
SUB_BIAS
else
OVERFLNO_TRAP
endif
endif
end if

c . If affine mode:

arg2
+Infinity -Infinity
1' infinity +Infinity cl
argl -Infinity cl -Infinity

c1 . Slgnal Invalid operatlon=2. Z= NAN

If pro)ective closure mode, return NAN and signal Invalid operatlon=B.

m. Return arg2 but set the "d" bit In the NAN to Indicate that this Is a "double" NAN .
C.3 MULTIPLY (FMUL)

Z=arg1 x arg2
Opcode=S04

The sign of Z Is the "exclusive OR" of the signs of arg1 and arg2.

arg2
Normalized Zero Infinity ·NAN Not Normalized
Normalized a o· Int• arg2 a
Zero o· o· b arg2 o·
arg1 Infinity Inf" b Inf• arg2 Inf
NAN arg1 arg1 arg1 m arg1
Not Normali zed a o· Int• arg2 a
•sign determined by arg1 "exclusive OR" arg2

a.
1) Generate sign and exponent. Multiply the signlficands In internal form .
2) If arithmetic overflow occurs , then right shift the significand one bit and lncre·
ment the exponent.
3) If UNDERFLOW then
If tra p enabled then
ADD_BIAS
ROUND
else
UNFLNO_TRAP
end if
else
ROUND
CKINVAUD
Iv OVERFLOW then
If trap enabled the n
SUB_BIAS
else
OVERFLNO_TRAP
endif
end if
end if

b. Signal Invalid opera\ion=9. Z= NAN .

m. Return arg2 but ae\ the "d" bit In the NAN to Indicate that this Is a "double" NAN .
 C.4 DIVIDE (FDIV)

Z=arg11arg2 with algn of Z equal to the "exclusive-OR" of the algns of arg1

and arg2.
Opcode=S06

arg2
Normallzod Zero Infinity NAN Not Normallzad
Normal ized c a o· arg2 b
Zero o· b o· arg2 o·
arg1 Infinity Inf Inf• b arg2 Inf•
NAN arg1 arg1 arg1 m arg1
Not Normalized c a . o· arg2 b
·with correct sign

a . Signal Division by zero.

Z =infinity with correct sign

b. Z =NAN. Signal Invalid operation= 4.

c.
1) Generate s\gn and expOnent. Divide the slgnilicands in Internal format.
( ,...._ 2) If n; 0 , then left shitt signiticand one bit and decrement exponent.Sneed not par-
ticipate In the left shift. A zero or s may be shifted into r from the right.
3) If UNDERFLOW then
If trap enabled then
ADD_BIAS
ROUND
else
UNFLNO_TRAP
endif
else
ROUND
CKINVALID
If OVERFLOW then
If trap enabled then
SUB_BIAS
else
OVFLNO_TRAP
endif
endif
end it

m . Return arg2 but set the "d" bit In the NAN to Indicate that this Is a " double"' NAN .
C.5 REMAINDER (FREM)

Z=arg1-arg2 x n
Where n =Integer part of arg1/arg2 In round nearest.
Opcode=$08

arg2
Normalized Zero Infinity NAN Not Normalized
Normalized
Zero
b
arg1
•a arg1
arg1
arg2
arg2
a
•a
arg1 Infinity a a a arg2
NAN arg1 arg1 arg1 m arg1
Not Normalized b a arg1 arg2 a

a. Signal Invalid operation= 10. Set Z to NAN.

b. Create number of Integer bits In quotient "n" as:

n=exp1-exp2-1
Generate "n" quotient bits , leaving raw remainder .. r."
If r>arg212
then
rema inder:: r- arg2
else
remainder= r.
Normalize remainder
11 UNDERFLOW then
If trap enabled then
ADD_BIAS
ROUND
else
UNFL_NO_TRAP
end if
else
ROUND
CKINVALID
11 OVERFLOW then
If trap enabled then
SUB_BIAS
else
OVFLNO_TRAP
endif
end If
end If

m . Return arg2 but set the "d" bit In the NAN to Indicate that this ts a ~double" NAN.

C.7
((
C.6 SQUARE ROOT (FSQRT)

z=SQRT (arg2)
Opcode=S12

z
Normalized a
Zero arg2
arg2 Infinity c
NAN arg2
Not Normalized b

a.
1) For a positive normalized number: compute Z= SORT (arg2) to the number of bits
requ ired to produce a correctly rounded result. To round correctly in all cases,
calculate two more bits of Z than the precision of the destination. ROUND as In
Appendix C.
2) For negative normalized numbers: signal Invalid operation= 1; Z= NAN.

b. Signal Invalid operation= 1; Z =NAN.

c.
c- 1) For proie.ctive mode signal Invalid operafion-1 ; Z= NAN.
2) In affine mode. for plus Infinity, set Z=arg2. For minus Infinity, signal Invalid
operation= 1; Z= NAN .
C.7 INTEGER PART (FINT)

Z= Integer part of arg2

Opcode=S14

z
Normalized a
Zero arg2
arg2 Infinity arg2
NAN arg2
Not Normalized a

a.
1) If arg2 has no traction bits In Its signficand. then set Z to arg2. This occurs It the
exponent is so Jarge that no fraction bits exist, for example, In single precision a
number with an unbiased exponent greater than or equal to 23.
2) If arg2 has fraction bits, right shltt the arg2 slgnlticand. while Incrementing the ex·
ponent, until no bits (zero or nonzero) of the fractional part of arg2 lie within the
rounding precision In effect. When this occurs, the unbiased exponent will be:
single 23
double 52
extended 63
3) ROUND as specified in Append ix D.
=
4) If all signlficand bits are zero, then Z 0 with the sign of Z, otherwise, normalize Z.
=
Zero or s Is shifted into g from the righ\ since s 0 after rounding .

c.e ABSOLUTE VALUE (FAB)

Z= jarg2 [
Opcode= S1E
--z-
Normalized a
Zero a
arg2 Infinity a
NAN arg2
Not Normalized a

a . Z = arg2 with zero (plus) sign.

T~ C.9 NEGATE (FNEG)

Z= -arg2
Opcode=S20
-z--
Normalized -arg2
Zero -arg2
arg2 Infinity -arg2
NAN arg2
Not Normalized -arg2

C.10 COMPARE (FCMP, nCMP, FPCMP, FTPCMP)

CC= arg1 - arg2

Compare arg1 to arg2 and set condition codes accordingly or generate a true/false value
for a predicate.

The four versions of compare are:

FCMP (Opcode - SSA) - Compare arg1 with arg2 and set the condition codes. Do not
trap on unordered unless the trap on the unordered bit (UNOR) is set in the enable byte of
the FPCB. .

nCMP (Opcode - SCC) - Compare arg1 with arg2 and set the cond ition codes: Trap If
the unordered condition occurs regardless of the state of the UNOR bit In the enable byte
of the FPCB.

FPCMP (Opcode - SSE) - Compare ,arg1 with arg2. Either affirm or dlsaffirm an Input
predicate. Do not trap on unordered unless the UNOR bit ls set In the enable byte of the
FPCB. For reg ister calls. the Z·bit In the condition code register Is aet to 1 for affirm or
true, and set to 0 for disaffirm or false . For stack calls, a byte of zeros Is pushed on the
top of the stack for true and a byte of ones ($FF1 Is pushed for false. Predicate compares
are used often by HLLs when evaluating the conditional expression In control
statements like tf.

nPCMP (Opcode - SDO} - Compare arg1 with arg2. Either affirm or disaffirm an Input
predicate. Store the true or false Indication In the result . Trap It the unordered condition
occurs regardless of the state of the UNOR bit In the enable byte of the FPCB.

Since a compare allows different precision arguments, the X-register, on the call, con·
talns a parameter specifying the precision of arg1 and arg2 and the predicate, It this is a
predicate call. The format of the X-register Is:

I 0 I arg1 I 0 I arg2 I

C-10
 Where arg1 or arg2 Is defined:
000 Single
001 Double
010 Extended
011 Unused (defaults to extended)
100 Unused (defaults to extended)
101-111 Undef ined

The predicates are > , =, •, <,and unordered or the combinations: i!: or s .

Once the a rguments have been expanded into Internal format, the following comparisons
are made with the internal values .

arg2
Normalized Zero Infinity NAN Not Normalized
Normalized
Zero
•a a
g
b
b
f
f
d
d
arg1 Infinity c c e f c
NAN f I f f I
Not Normal ized d d b f d

STEP 1.
( a.

arg1~
•Compare magnitudes of arg1 and arg2. Go to step 2.

b . If affine mode, then

If arg2 = + Infinity then < else > . Go to step 2.
If projective mode, &lgnal unordered. Go to step 2.

c. If affine mode, then

If arg1= +Infinity, then> else< . Go to step 2.
If projective mode , then signal unordered. Go to step 2.

d. Normalize one or both of the Input arguments.

Set unnormal zeros to true zeros .
If both arguments are zero. then go to " g" else go to " a."

e. In projective mode set to equal. In affine mode:

arg2
+Inf. -Int.
+Inf. <
arg1
-Inf. <
go to step 2.

C-11
f . Set unordered. Go to step 2.

g. Set to equal. Go to step 2.

STEP 2.
1) If condition codes are to be returned (FCMP or FTCMP), then set the returned con·
di\ion code bits In the following pa\\erns:

N z v c
> 0 0 0 0
< 1
,
0 0 0

I =
Unordered
0
0 0
0
0
0
1

This allows the following signed branches to be taken Immediately following the
return from FCMP or FTCMP.

Condition Branch Test tor Br•nch

> (l)BGT (not (N •VII and (no\ ZJ 1 =
(l)BGE not (NeV)=1
"'< · (L)BLT not (N•V)=O
s (l)BLE (not (N • VD and (not Z) = 0
= (L)BEO Z=1
(L)BNE Z=O
"
Unordered ll)BCS C=1

II CMP and the unordered trap Is disabled, a BCS should immediately follow the
call and precede any of the other branches:
CMP arg1, arg2
ecs unordered
BGE label

II unordered occurred, then set the UNDR bit in the status byte of the FPCB so
that the trap will be taken during post processing.

2) If a predicate Is to be returned , then:

less than affirms: < •
equal affirms : = s ~
greater than affirms: > ~ •
unordered affirms: unordered •
less than disalfirms: = ~ > unordered
equal dlsaffirms : < > • unordered
greater than disaffirms: = s < unordered
unordered disaffirms: < s = ~ >
The result returned for affirmed Is a zero byte and for disaffirmed It Is a minus 1 or
SFF byte for a stack call. For a register call, Z= 1 Ill affirm.

C-12
(
If unordered occurred, then aet the UNOR bit In the status byte of the FPCB so
that the trap will be taken during post-processing. Add itionally, If the predicate is
-. , then set the result to true to give the user a test for a NAN; I.e .. If A• A returns
true, then "A" Is a NAN.

If unordered and TPCMP or PCMP then

If,. then
set result true
else If not(= or unordered) then
signal unordered and Invalid operation = 6
so that a trap will be taken during
post-p r ocessi~g
endif
end ii

C.11 FLOATING TO BINARY INTEGER (FFIXS, FFIXD)

I= INTEGER (arg2)
I= 16 bit signed integer tor FFIXS (Opcode= $16)
I= 32 bit signed integer for FFIXD (Opcode= $18)

The resultant integer Is stored on the internal stack In the first 2(4) bytes of the fraction
for the result wHh the lower address conta ining the most significant byte .

Normalized d
Zero 0
arg2 Infinity a
NAN b
Not Normalized d

STEP 1.
a . Set V bit in returned condition code register and integer overflow bit in status . Set
I as shown be low:
short pos itive 32767
short negative -32768
long positive 2,147,483,647
long negative -2,147,483,648

b . Signal Invalid operation= 3; return I= address of the Instruction following the call
to the floating point package .

c. If arg2 ls not an Integer, then call FINT to convert It to an Integer. Convert arg2 to a
binary Integer and return It to the destination. If the integer exceeds the size ct the
destination, then go to "a" above.
(
STEP 2.
Set the Zand N bits In the returned condition codes N will already be set If overflow DC·
curred) according to the resultant Integer.

C.12 BINARY INTEGER TO FLOATING (FFLTS, FFLTD)

Z =FLOAT (arg2)
arg 2 = 16 bit signed Integer for FFLTS (Opcode= $24)
arg2 = 32 bit signed Integer for FFLTD (Opcode= $26)

The Integer Is stored on the internal stack In the first 2(4) bytes of the fraction for arg2.

a. Convert arg2 to floating representation. If arg2 cannot be represented exactly,

the n ROUND as described In Appendix D.

C.13 BINARY FLOATING TO DECIMAL FLOATING STRING (BINDEC)

Opcode=Sic
Required Functions and Tables.

For both BINDEC and DECBIN, several functions and tables are required . BINSTR and
( STRBIN are required as well as a function to find the log_base_10(X). BINSTR converts
a binary floating integer to a signed unpacked BCD string. STRBIN converts a signed
decimal unpacked BCD string to a binary floating Integer. Fortunately, the
log_base_10(X) can be derived from :
log_base--2(X) x log_base_10(2).

Also, the log_base_10(X) need onl y !>e calculated to the nearest Integer. Fortunately,
this can be accomplished by noting that log_base-2(X) is approximately equal to the
unbiased exponent of X. A table of the powers of 10 (in Internal formal) will be oeeded.
This table need not contain all powers of 10 as some can be derived from the others.
Negative powers shall be obtained by dividing by the corresponding positive powers In·
stead ol multiplying . The following 31 values (to full internal accuracy) will be required in
the table:
100
101
 Argument Requirements

For reg ister calls, the U register conta ins the constant "k" that specifies the number of
significant digits desired .

For stack calls, the input stack looks like :

l-n-111-2- IBytes
I/1 Iarg2 Ik IFPCB I
s
Where n = 4, 8, or 10 bytes
S =hardw are stac k pointer

The re t urn string is a standar d BCD string as defined in Section 2 (BCD Strings).

Conversion Process
Given binary floating point number arg2 and an integer k (passed in arg1) with 1sks9 for
s ingle precision and 1sks17 for double precision, we can compute the signed decimal
stri ngs I and E such that I has k significant d igits and interpreting I and E as the integers
they represent :

c- arg2= Ix 1o(E + 1 - ~> = sd dddddddd x 10E

where s is the sign of arg2 and the ds are the k decimal digits of I.

The size of I and E are defined by the output string generated by BINSTR for the sup·
ported precisions.

STEP 1.

Sirin
Normalized c
Zero b
arg2 Infinity a
NAN d
Not Normalized

a. For +infinity, de fi ver a nondecimal string with se =SOA and the remaining bytes
equal to zero .

For - infinity, deliver a nondecimal string with se =SOB and the remaining bytes
equal to zero .

b. f =string of "+ O" or "-0"; E =String of "0." Go to step 2.

C.15
 c.
1) Remember • ign of arg2. Let p = absolute_value (arg2).
Remembe r whether arg2 ls normalized.
1a) If arg2 I• unnormal zero, then go to b.
2) If p Is not denormalized, compute Q=long_base_10(p); otherwise let
q = log_base_10 (smallest normalized number).
3) Remember the current rounding mode. Compute:
v= FINT(q)+ 1 -k
with round ing mode RZ.
4) Compute w=FINT (p/10V) using powers of 10 from the tables w ith round ing
mode RN . Restore original round ing mode.
5) Adjust w for special cases:
I. If W2:.{10k)+ 1, then increment v and go to 4. ·
II. If w = 10k, then increment v, divide w by 10 (e<actly) and go to 6.
Ill. If w~ 10(k-1)-1 and arg2 was normalized in step 1, then decrement v
and
go to 4.
6) I= BINSTR (w with sign of arg2); E = BINSTR (v).

d. Deliver a nondecimal string with se;: SOC followed , in the exponent field, by the
unpacked hex add ress where the NAN was created .

STEP 2.
Return a BCD string as defined in Section 2 (paragraph 2.5) with p = O.

C.14 DECIMAL FLOATING STRING TO BINARY FLOATING (DECBIN)

Opcode=$22
Required Funtlon• and Tables

For both BINDEC and DECBIN, several functions and tables are required . BINSTR and
STRBIN are reQuired . BINSTR converts a binary floating Integer to a signed unpacked
BCD string. STRBIN converts a signed unpacked BCD string to a binary floating integer.
A table of the powers of 10 (in Internal format) will be needed. This table need not conta in
all powers of 10 as some can be derived from the others. Negative powers shall be ob·
tained by dividing by the corresponding positive powers Instead of multiplying. Those re·
quired in the table are :
1oO
101

1()26
1o27
1Q54
10108
1Q216

C-16
 Argument Requirement•
For stack calls the Input stack looks like:

\BCD String FPCB I

s
For the format of the BCD string see Section 2 (BCD Strings Paragraph). The total size of
the BCD string Is 26 bytes.

The result for stack call s Is on lop of the stack.

For reg ister calls:

X= result
D= FPCB
U =pointer to lnpul BCD string

The Input argument Is a standard BCD string as defined in Section 2 (BCD Strings
paragraph) whe re "p" Is set to the number of fraction digits to the right of the decimal
point.

Conversion Process
· The number to be converted (arg 2) can be thought of as a number of the form:
arg2 = sddddd .DDDDDDDDD x ioE

On entry, arg2 contains a pointer to a string as defined In paragraph 2.4. Let

t = sddddd.DDDDDDDDD. arg2 conta ins an Integer p that Indicates how many digits ol 1
are to the right ol the decimal point such that:
arg2= I x(10- P) x (10E)

1) Compute U = STRBIN (I) and w = blnary_lnteger_of (E)

2) Compute result : z = u x iotw - Pl

3) If UNDERFLOW then
If trap enabled then
Z=NAN
else
UNFLNO_TRAP
end if
end If
If OVERFLOW the n
If trap enabled then
Z=NAN
e lse
OVFLNO_TRAP
endif
endlf

C-17
C.15 MOVE (MOV)

Move erg2-result
Opcode=S9A

Since move allows for arguments of different precisions, It requires that the precisions
be specified by the calling program In a size word parameter. The U-register Is used to
hold the size word In register calls. In stack calls the size word Is pushed onto the top of
the stack above arg2 but before the pointer to the FPCB. The format of the size word is:
15 8 6 0
00000000
I0 I arg2 result

Where arg2 (source) or result (destination) Is defined:

000 Single
001 Double
010 Extended
011 Extended round to single
100 Extended round to double
101·111 Illegal

For stack calls the calling stack looks like:

arg2 Size Word Pointer to FPCB I

s
Move allows the Input argument and \he resuH to _be of different precisions. For stack
calls the MOV operations transform the stack top from the source precision to the
destination precision.

For moves where the precision of arg2 equals the precision of the result, the arguments
will not be moved to the stack since no conversion is really needed; otherwise, the source
argument (arg2) will be moved onto the internal stack. This Is necessary since If the MOV
were a conversion from a shorter to a longer precision value at the same address, the
result might overwtite parts of the source before they have been read .

Result
(Destination)
Normalized a
Zero arg2
arg2 Infinity arg2
(Source) NAN arg2
Not Normalized b

C.18
 a.
( If the destination Is ahorter than the aource, then Zcarg2.
H UNDERFLOW then
II trap disabled then
UNFL._NO_TRAP
•i•e
deliver to the trap handler the result In lnternel
format but rounded to the precision of the destination.
end II
end If
ROUND to the precision of the destination
CKINVALIO
If OVERFLOW then
If trap disabled then OVFLNO_TRAP
else
deliver to the trap handler the result In Internal
format but rounded to the precision of the destination.
end II
end II
If the destination field Is wider than the source, then the
move Is exact.

b.
If (single to double) then Invalid operation= 15
Else If (source= ext) and (dest< >ext) and (not denormalized)
( Invalid operation= 16
else
goto a.
endll
end II
 APPENDIX D
ROUNDING AND EXCEPTION CHECKING ROUTINES

D.1 INTRODUCTION

The following rout ines and functions are used after the arithmetic operations to round
and to detect·error conditions.

0.2 ROUNOING

Round ing is accomplished using the v, 1, g , "4, ands bits as defined in the internal for-
mats. In general, the significand of the number to be rounded looks like:

I I
v n.fff •••. . •. . . .... . . .. .. ..1 I0 I rr .• 4 I tJ
(
where:
v =overflow bit
n = 1 (explicit 1.0)
f =fraction
I= 1s bit of fract ion
o=ouard bit
r=round bits
&=sticky bit

The s bit is the logical '"OR .. of all the bits to the right of the r bits. Thus during the
calculation stage of an arithmetic operation, any nonzero bits which are generated that
are to the right of the r bits show as a 1 In the s bit. If the precision mode specified in the
control byte of the FPCB is 6 or 7, then rounding should be to the precision specified. The
following algorithm Is used to round the result to 1 of the four rounding modes :

begin
If o = s = r = 0 then result Is exact

0.1
 else (not all zero)

aet Inexact result flag bit

case rounding mode of

RM: If sign= 1 then add 1 to I
RP: If sign= O then add 1 to I
RN: If g=1 and r=s=Othen
If 1 -1 t hen add 1 to g
else add 1 tog
(RZ falls through)
end case
If v = 1 then
shift right
increment exponent
end if
set g = r=s = O
endif
end

where :
RM= round to minus
RP= round to plus
RN= round to nearest
RZ =round to ze ro

D.3 EXCEPTION HANDLING

D.3.1 Invalid Operation

Invalid operation encompasses problems arising In a variety of arithmetic operations; it

is the blanket cove rin g those errors which do not occur frequently enough or are not im-
portant enough to merit their own fault condition. The result to be delivered by an invalid
operation Is a NAN .

D.3.2 Underflow

In a general sense, underflow Is the condition that exists when an arithmetic operation
creates a result that Is too small to be represented In the normal memory format for the
destination. If the trap ls enabled when underflow occurs, the user can determine what
he wants to do. The actual result of the operation will not be lost since the Internal for·
mats are capable of representing the und~rflowed number. If no trap ls enabled, the
floating point package will automatically denormalize the result as discussed previously
(gentle underflow). In the case of trap enabled, but the trap wishes to return the result ,
the delivered exponent wlll be the result of adding a bias adjust for each precision as

0-2
shown below. This bias adjusts the exponent so that tt wlll contain a number in the mid·
die of fhe exponent range .

Bias adjust for overflow/underflow

Single 192
Double 1536
Extended 24576

D.3.3 Overflow

In a general sense, overflow Is the condition that exists y.ihan an arithmetic operation
creates a result that is too large and cannot be represented in the normal memory format
for the destination.

Overflow Is handled much more harshly and quickly than underflow and with a cor-
responding loss of information. The number system chosen Is slightly biased towards
underflow for this reason. tf a trap Is to be taken on overflow, then a bias is subtracted
from the exponent to wrap It around into the range of valid exponents. The bias for each
precision Is given above. If no trap is to be taken, then a suitable result Is returned.

D.3.4 Division by Zero

This exception occurs when a normal zero divisor occurs In a division. 11 the divisor is nor-
mal zero and the dividend is finite and nonzero, the default result Is Infinity with the cor-
rect &ign. ff the cfr~ision by zero trap is enabled, then It Is taken and the default result is
returned.

D.3.5 Inexact Result

11 the rounded result of an operation ls not exact or if it overflows to Infinity, then the in·
exact exception shall be signaled unless the result would be an Invalid result. If the trap
Is enabled, It Is taken; otherwise, the rounded result or the infinity that resulted from
overflow shall be the default value returned .

D.3.6 Integer Overflow

This occurs when a large floating point number Is converted to an integer that cannot be
represented In the destination. if the trap Is enabled, II will be taken and the caller can
"fix" the result. If no trap Is enabled, the largest positive or negative Integer Is returned.

D.3.7 Unordered

Unordered occurs when a comparison Is made between a NAN and anything else or when
Infinity i• compared to anyihlng except Itself In projective closure.
c D.3.8 Error Trap Handling

When an error trap occurs, the post processin g code passes control to the location
specified Jn the FPCB vector with the U register pointing to the stack frame. The trap
routine may then modify the result on the stack frame or It may choose to create a new
result and store the result d irectly In memory. If the result on the stack frame Is modified,
the routine must remember that this number is In Internal format. On return from the error
trap routine, II the C.blt Is set, the result Jn the stack frame will be moved to memory. II
the C.blt Is cleared , no resu lt will be delivered to the destination.
On entry to the trap routi ne, the U-register wlll contain the pointer to the current stack
frame . The temporary status stored in the stack fram e should be used to determine the
st atus of the last operation. If more than one bit Is set In the st atus register, the floating
point package will determine which trap should have pre cedence as d iscussed in Se ction
"(Exception Modes pargraph}. In the case where the highest precedence exception does
not have Its trap enabled, then the next highest precedence will be checked, etc., until
the highest precedence enabled trap, II any, Is found .

D.4 ALGORITHMS FOR EXCEPTION PROCESSING

The following are the algorithms implemented in the MC6639 to che ck for the process ex·
ceptions .

D.4.1 Check for Invalid (CKJNVALID)

procedure CKINVALID
begin
If not infinity or true zero then
If destination precision Is single or double then
If result is denormallzed
fix exponent for denorm resu lt
else
If not normallzed then
Jop:16
end if
endi f
end if
endif
end

D.4.2 THI for Overflow (OVERFLOW)

function OVERFLOW
begin
("test for overflow•)
If the rounded result Is finite and Its exponent Is too large for the destination
then OVERFLOW:= true ; aet overflow flag
else OVERFLOW: : false
end
 D.4.3 Overflow With Traps Dlubled (OVFL NO TRAP)

procedure OVFLNO_TRAP
begin
set Inexact result flag;
If rounding mode Is round to - Infinity
then
clear overflow flag
If result Is positive
then
If result Is normalized
then
deliver largest positive
number to destination
else
deliver slgnificand and largest
exponent to destination
endif (•result Is normalized·)
else ("result Is negative •)
deliver - Infinity to destination
endif; (*result Is positive•)
endif; ("rounding mo~e Is to - Infinity•)
If rounding mode is round to +infinity
( then
clear overflow flag
lf result Is negative
then
If result Is normalized
then
deliver largest negative number to destination
else
deliver slgnlficand and largest
exponent to destination
endlf; ("result Is normalized)
else ("result is positive•)
deliver +Infinity to destination
endif; ("result Is negative")
endif; ("rounding mode Is to +Infinity")

If rounding mode ls to nearest or to zero

then
deliver properly signed Infinity to desti nation
endif; (*round to nearest or to zero·)
end

[).5
 D.4.4 Subtract Blas on Overflow (SUB BIAS)

procedure SUB_BIAS
begin
subtract b ias (from tab le shown In parag ra ph D.3.2) from exponent
end

D.4.5 Test for Underflow (UNDERFLOW)

function UNDE RFLOW

begin
If exponen t not= $8000 (true zero)
If exponent ls too small for destination format
then UNDERFLOW: = true; set underflow tlag
else UNDERFLOW: = fa lse
endif
else UNDERFLOW: = fa lse
end if
end

D.4.6 Add Bias on Underflow (ADD BIAS)

Procedure ADD_BIAS
begin
add bias (from table shown in paragraph D.3.2) to exponent
end

D.4.7 Underflow With Treps Disabled (UNFL NO TRAP)

Procedure UNFLNO_TRAP
begin
denormalized unrounded result ;
ROUND denormalized resul t;
If fra ction =0 then set to true zero
deliver denormalized and rounded (only once)
result to destination;
If rounding mode Is either round
to - Infinity or to +Infinity
then
clear underflow flag ;
endif ; ("round to infinity")
end

0-6
 APPENDIX E
PROGRAM DETAILS AND STACK FRAME
DESCRIPTION

E.1 PRE·P ROCESSINGIPOST·PROCESSING

All operatio ns unde rgo a pre.processing step where the calling arguments are moved
from the ir present locations to an internal stack frame and a post-proces sing step where
the resu lts are returned from the stack frame . In general, the operation of any function
looks like:
save caller registe rs on the stack
determine function opcode
If reg ister call then
Initialize stack frame for reg ist er call
move argument(s) into interna l sta ck frame
If no Input erg is a trapping NAN , then do function
check for traps
If (no traps) or (trap handler wants result returned )
then move result to user
cleanup stack
else (stack call)
adjust stack If necessary•
Initialize stack frame for stack call
move argument(s) to Internal stack frame
If no Input arg Is a trapping NAN , then do function
check for traps ,
If (no traps) or (trap handler wants result returned)
then move result to stack top
cleanup stack
adjust stack If necessary•
end if
restore caller registers
retu rn

E.1.1 Stack Frame

Upon execution, the floating point package Immediately reserves an area on the active
hardware stack for Its execution time local variables. Once this .. stack frame"is initializ·
ed, It Is used by all the modules of the program. The stack frame area Is released on exit
from the call.

·~, . adjulllrtg the alack blfort o r attar Pft>CeSllng may bl NC9nary H tM tol• l • LH ot the Input a rguments
•not 9Qt.11. I to tM al.la ot the output a rgument.

E·1
The user may need to know the details of the stack frame If he plans to write trap
routines to manipulate results In the Internal format . Append ix F contains Information on
the Internal format for floating point numbers on the st ack frame.

Figures E·1 and E·2 are examples of the stack frame configuration. Figure E-1 Is tor a
reg ister call and Figure E-2 ls for a stack cal l. Notice that from mnemonic ''TYPE 1" down
to the bottom of the stack, the two stack frames are Identi cal. This allows the actual
operation rout ines to be Identica l regardless of the type of call. During execution ol the
operation, the lJ.reglster always points to the bottom of the st~ck frame .

Mn!'mon1:
Cal•r·$ PC:
CALL PC
VREG . PAFG1 Po<•llr• 10 Argu<ne·.1 1 C.1\f'"sU
YREG . ?ARG2 Potrne• 10 Arg u"""": 2 c.11e··s Y
ltREG . PRE.SUL Po•nte• 10Res.i•1 C.1ie•'s K

DREG PFPCE~ P oin1e: 10 FPCB c.11e•s:>

CC RIG t o,,d•t1on CoOt~ C.•ir··s CC
IP.[ GPC IREOs Re:u•r PC

}-·
a·gi lvt>t 1l 6.·1t •
TY P[ 1
fra:11:i·
19 B1~rs •

FFiA Cll 1n1e m1 ' Fonna:

If\
l\JB1in1
E X~1 f • PO"'f " \ 12•
S•Gt..i . 1·~1 S•;·
a·~lo c-+ : <fi,:t

}-'
lYPt.2
F11::•:-·
t9B1·1u 1
1n lrlleml' Forma:
fRACT2
113Byinl
EK P~ , E•r::>... r: !~ •
SIGl\1. 11•;11 Sig·
'

}-
l'le~u!: 1 ~Pt- 11 81tel
lYPEJI
fr1t1 •0"
19 Bv1es •
F RI.CTR
"' 1n1e·"'' Forma:
113 Bvtn1
EXPF hponen112 1
S•g"

}..-~-
StGNI\. RES Ul l
ST1i;;y S 11tlv B11e
TPAJIAM lempol'•'v Parame1e1l l2 •
151 .t.l l C'ft'lt)Ofa•v Sa1us 121
PPF.EC Auul1 P•K'5•0"
PFP:B P o ....1e1 to FP CP
Pl OS Poi..1e· 1010S

FUNCl 0 D(;C~ - u

Flguro E·1. Roglstor Call Stock Frame

E·2
 Figure E·2. Stack Call Stack Frame .

Special handling of the stack frame occurs for BCD string conversions. The actual BCD
strings will not be moved onto the stack frame . A pointer to the strings will be stored In
the stack frame Instead. The operations will access the strings directly In the user·s
memory or stack.

E-3
 Special handling also occurs for MOV with equal precision arguments. In this case the
stack frame will not normally be created since It would slow down rather than speed up
the operation. However, a stack frame will be created for a MOV with different precision
arguments. This enables the trap handler to do Intelligent processing.

All operations have a result except for nonpredicate compares which only return with the
appropriate bits set In the condition code register. Predicate compares only return a
1·byte "yes" or "no" as the result.

For operations that convert from an integer to floating point, the Integer will be stored in
the fraction of argument 2. For operations that convert from floating point to an integer,
the resulting integer Is stored in the fraction of the result.

N ote that space for argument 1 Is reserved on the siack frame even If the call is monadic.
This insures consistent use of subroutines to manipulate arguments on the stack.

II bit 3 (NRM) of the control byte In the FPCB Is set, then all denormalized (not unnor-
malized) numbers wlll be normalized during the move onto the stack frame.

E.1.2 FP (Floating Point) Variables

fj - E.1.2.1 POINTER TO FPCB (PFPCB). This word contains the address of the start of the
\
FPCB to be used by this call.

E.1.2.2 TOS (TOP OF STACK) POINTER (PTOS). For stack calls, this word points to the
top floating point argument on the stack when the floating point package was initially
called. This may not be the address just above the caller return PC, since II might have
been necessary to reserve some empty stack space when the result of a function uses
more bytes on the stack than the Input arguments. Note that the pointer to the FPCB, as
passed by the user, Is always at PTOS-2.

E.1 .2.3 TEMPORARY PARAMETERS (TPARAM). This temporary two byte location Is used
by DECB IN and BINDEC to store parameters. It ls also used by calls to MOV or the com-
pares to store the parameter word and may be used by other operations as a scratch
location.

E.1.2.• TEMPORARY STATUS (TSTAn. This temporary two byte status Is used by the
floating point package to generate status bytes of this operation. The first byte (lower ad·
dress) has a format Identical to the status byte In the FPCB. Al the completion of the
operation this temporary status Is logically "ORed" Into the existing status In the caller
FPCB. The second byte contains a temporary byte that has the same format as the
secondary status byte In the FPCB. At the completion of the operation, II an Invalid
operation occurred, this byte wlll be written Into the secondary status.

E_.
E.1.2.S RESULT PRECISION (RPREC). The Index stored at this location defines the preci·
slon of the result.
Index Precision
0 Single
2 Double
4 Extended
6 Extended Rounded Single
8 Extended Rounded Double
For compares, this loc ation contains the index of arg2 instead of the result.

E.1 .2.6 OPCODE (FUNCT). This byte contains the opcode picked up from the user's call·
Ing sequence. This is used by various subroutines. It also allows an error trap to deter-
mine what operation caused an error. Some bits In the opcode have special meaning:
bit 7=1 =M ixed size arguments (MDV, CMP)
bit 6 = 1 =Trap on unordered compare
bit 5=0= Function number

E.1.2.7 STICKY BYiE (STIKY). This byte is used during arithmetic operations to "OR" all
the least significant bits of an 'operaHon. The sticky byte is then used during rounding .
Some sticky bits are also picked up by " ROUND " from the low order bits of the internal
fraction .

E.1.2.8 ARGUMENT TYPE (TYPEx). A byte is reserved for each argument to Indicate its
type . The routine that Initializes the stack frame Initializes the values for TYPE 1 and
TYPE 2. The values are :
0 =Normal, In range , normalized .value
2 =Normal zero
.C= Inf init y
6 = Not a number
e =Not normalized
Note that an unnormalized zero will have an Index= e, • 2.
This byte occupies the highest address of the fraction for each argument.

The type of the result may not be valid at the time of a trap.

E.1.2.9 SIGNX, EXPX, FRACTX. The bytes describe the fields In tnternal lormat numbers.
Appendix F provides details of internal format numbers.

E·5/E-6
(

APPENDIX F
INTERNAL FORMATS

F.1 INTRODUCTION

The memory formats are chosen to provide the greatest amount of precision in the least
amount of memory, whereas, the Internal formats are selected to permit the easiest and
fastest implementations of the desired operations. A caller to a floating point subroutine
passes arguments in memory formats and receives the result In memory format;
however, internally the floating point package converts to the internal formats, does the
operation, and then converts the result back to memory format.

F.2 SINGLE INTERNAL FORMAT

This format consists of 7 bytes:

f4--8Bits--+l
I Sign I
~16 Bits-----+!
I Unbiased Exponent I
f - - 2 4 Bits-~......,,..--~s Bits----+1

where :
sign =positive or negative byte
containing the sign of the fraction.
Only the most significant bit Is defined:
b7 =0= plus; b7=1 =minus
unbiased exponent =twos complement exponent
g =guard bit
r =rounding bits
• =Sticky bit

The g, r, and s bits are used for rounding as described In Appendix D.

F-1
F.3 DOUBLE INTERNAL FORMAT
i.-BB l ts~

I Sign I
~16 Bits---+l
I Unbiased Exponent I
~====54~B~i~l·~==~!:;:~10 Bits----..;
I~_1_._s_3_B_i1_F_ra_c_ti_o_n_~lo~I~·....[~

F.4 EXTENDED INTERNAL FORMAT

i--BBits~

I Sign I
~16 Bits---+l
1 Unbiased Exponent I
~ Bits-- -.;---e Bits-----+i
I 1. 63Bit Fraction lgl rl rl rl rjrl • l t J

Note that single , double, and exte~ded internal formats differ only In the number and
location of the g, r, ands bits .

F.5 ZERO

Zero is represented by a number with the sma\leist unbiased exponent and a zero signifi-
cand :

I • I100. .. . 0000 I o

F.I INIFINITY

Infinity has the maximum unbiased exponent and a zero slgnlficand:

I• 1011111 .. .. 11 I 0

F·2
F.7 NANS

NANs have the largest unbiased exponent and a nonzero slgnificand. The operation ad·
dresses, ..t" and " d," are Implementation features and are defined in Section 2 (Not a
Number paragraph).

Id I 011 ..... 1111 I I l

0 t Operation Address I 00000000

The ope ration addre ss always appears In the 16 bits Immediately to the right of the t bit.

F.8 INTERNAL UNNORMALIZED NUMBERS

Unnormalized numbers occur only Jn extended or Internal format. Unnormalized numbers

have an exponent greater than the Internal formats minimum (i.e., they are not denor-
malized or normal zero) and the explicit leading bit Is a zero. If the signlficand Is zero, this
Is an unnormalized ze ro. Even though unnormalized and denormalized numbers are
handled sim ilarly in most cases , they should not be confused . Denormalized numbers are
numbers that are very small (have minimum exponent) and hence have lost some bits of
significance. Unnormalized numbers are not necessarily small (the exponent may be
large or small) but the significand has lost some bits of significance,_hence, the explicit
b it and possibly some of the bits to the right of the explicit bit are zero.

I I>
s 100... 000 I O. Signlficand

Note that unnotmali.zed numbers cannot be represented (hence cannot exist) for single
and double formats. Unnormalized numbers come Into existence when denormalized
numbers, In single or double formats , are represented in extended or internal formats .

F-3/F~
 APPENDIX G
BASIC LEVELS OF PRECISION

G.1 SINGLE PRECISION SPECIFICATION

Length In Bits 32

Fields:
& =sign ,
e=exponent 8
f = significand (1)+23

Storage Format:
I· I e I
Interpretation of Sign:
positive 0
negative 1

Normalized Numbers:
Interpretation of e unsigned Integer
bias of e 127
range of e 0<e<225
Interpretation of f 1.f
relation to represent real numbers (- 1)2x2(e-127)x1.f

Signed Zeros:
•=
f=
0
0

Reserved Operands :
Denormalized Numbers:
e= 0
bias of e 126
Interpretation of f O.f
range off nonzero
relation to represent real numbers (-1)S x2-126 xO.f

Signed Infinities:
•=
f=
255
0

NANs:
3= 255
I= nonzero
Interpretation of f don't care

G·1
( Ranges:
maximum positive normalized 3.4x1()38
minimum positive normalized 1.2x10-38
minimum positive denormalized 1.• x -•S

G .2 DOUBLE PRECISION SPECIFICATION

Length In Bits

Fields:
s= sign 1
e =exponent 11
f = sign ificand (1)+52

Storage Format:
I· I e I
Interpretation ct Sign:
positive 0
negative 1

Normalized Numbers
Interpret ation of e unsigned integer
bias of e 1023
range of e 0<e<2047
Interpretation of f 1.1
relation to represent real numbers (-1)S x2(e-1023)x 1.f

Signed Zeros:
e= 0
f: 0

Reserved Operands:
Denormalized Numers :
e :0
bias of e 1022
Interpret ation off 0.f
range off nonzero
relation to represent real numbers (- 1)S x 2-1022 x O.f

Signed Infinities
e= 2047
f: 0

NANs:
e= 2047
I: nonzero
Interpretation of f don't care

G -2
(
Ranges :
maximum po sitive normalized 18x1()307
min imum positive normalized 2.2x10-308
minimum positive denormalized 4.9 x 10-324

G.3 EXTENDED PRECISION SPECIFICATION

Length In Bits 80
Fields :
s::: sign 1
e =expon ent 15
j =Integer part 1
I= slgnlfic and 63

Storage Form at:

Interpretation of sign:
I• I e I j.I

positive 0
negat ive 1

Normalized Numbers:
( - Interpretation of e
bias of e
twos compl ement Integer
0
range of e -163S4se<16383
Interpretation of signlficand j.f
relation to represent real numbers (-1)5 x 2"Xj.I

Signed Zeros:
•=
slgnificand =
-163S4 ($4000)
0

Reserved Ope rands :

Denormalized Numbers:
•=
bias of e
-163S4
0
Interpre tation of signlficand 0.1
range off nonzero
relation to represent real numbers (-1)5 x2-163S4 xO.f

Signed Infinities:
e= 16383 ($3FFF)
algnlficand = 0

NANs:
e= 16383 ($3FFF)
a lgnlficand = nonzero
Interpretation of slgnlficand don't care
(<
Ranges:
maximum positive normalized 6x1Q4931
minimum positive normalized Bx10-4933
minimum positive denormalized 11x10-4952

G-4
G -5/G-6
 APPENDIX H
DEFINITIONS AND ABBREVIATIONS

This appendix defines several terms and abbreviations used in this manual which are
peculiar to the MC6839 Floating Point ROM . Many of these definitions are also found in
the IEEE P1oposed Standard for Binary Floating Point Arithmetic Draft 8.0.

User - The user of a floating point system Is considered to be any person, hardware, or
program having access to and controlling the operations of the programming environ·
ment.

Binary Floating Point Number - A bit string characterized by three components: a sign,
a signed exponent, and a significand. Its numerical value, If any, is the signed product of
Its significand and two raised to the power of Its exponent. A bit string ls not always
distinguished from a number It may represent.

Ex.ponent - That component of a binary floating point number which signifies the power
to which two Is raised in determining the value of the represented nµmber. Occasionally,
c the exponent Is caHeO signed or unbiased exponent.

FP - An abbreviation for "floating point."

FPCB - An abbreviation for "floating point control block."

Biased Exponent - The sum of the exponent and a constant (bias} chosen to make the
range of the biased exponent non·negcltive.

Slgnlficand - That component of a binary floating point number which consists of an ex·
plicit or lmpliclt leading bit to the left of Its binary point and a fraction field to the right of
the binary point.

Fraction - The field of the slgnlflcand that lies to the right of Its implied binary point.

Normal Zero - The exponent Is the minimum established for format and the slgnlficand
Is zero. Normal zero may have either a positive or negative sign. Only the extended format
has any unnormalized zeros.

Danormallnd - The exponent Is the minimum established for the format, the explicit or
lmpllclt leading bit ls a zero, and the number Is not normal zero. To denormalize a binary
floating point number means to shift Its slgnlficand right while Incrementing Its expo-
nent until It ls a denormalized number.

Unnorm1Jlz1d - The exponent Is greater than the minimum established for the extended
format and the explicit leading bit is zero. If the signlficand is zero, this is an unnormaliz·
ed zero.

H-1
er Normallzo - II the number Is nonzero, ahllt Us algnlllcand left while decrementing Its ex·
ponent until the lead ing algnlflcand bit becomes one; the exponent Is regarded as If Its
range were unlimited. 11 the algnlficand Is zero, the number becomes normal zero. Nor·
mallzlng a number does not change Its algn.

Doublo Rounding - Double rounding occurs If any single operation causes a result to be
rounded more than once.

NAN - Not a number.

Sticky Bit - A &talus bit that, once sel by t he system as t he result of some operalion, re·
mains sel until explicitly cleared by the user. This fealure relieves the user of the con·
strain! of having to examine th is bit In any particular t ime window.

Hardware Slack - The stack defined on the MC6809 by the S (or SP) register. This stack
Is also used by the hard ware during subroutine calls and Interrupts.

Floating Point Package - A package of subroutines thal supports the basic capablllties
required to do calculati ons with rea l numbers.

lnlernal Format - A format resembl ing extended format that Is used by the MC6B39 dur·
Ing calculati ons. It does not exist before the package Is called nor does It exist after the
package returns and ft Is only an intermediate format.
(

H·2