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Before Moving To Systemverilog Concepts, We Will Look in To What Is Verification? What Is Verified? Why Do We Need To Verify? How To Verify?

Verification is carried out to ensure a design is correct according to its specification and free of bugs. This is done by driving inputs into modules and systems on chips to check that the design behaves as expected for both correct and erroneous inputs. A testbench is used to generate stimulus, apply it to the design under test, capture the response, check for correctness, and measure progress toward verification goals.

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36 views

Before Moving To Systemverilog Concepts, We Will Look in To What Is Verification? What Is Verified? Why Do We Need To Verify? How To Verify?

Verification is carried out to ensure a design is correct according to its specification and free of bugs. This is done by driving inputs into modules and systems on chips to check that the design behaves as expected for both correct and erroneous inputs. A testbench is used to generate stimulus, apply it to the design under test, capture the response, check for correctness, and measure progress toward verification goals.

Uploaded by

siddu. siddu
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction

Before moving to SystemVerilog concepts, we will look in to what is Verification? What is verified?
Why do we need to verify? How to Verify?

We need to verify the design to make sure that the design is an accurate representation of the
specification without any bugs. Verification is carried out to ensure correctness of design, to avoid
surprises at a later time, to avoid a re-spin of the chip and to enter the market on time with good
quality.

In the process of verification we are going to verify modules, SOC’s (System On Chip) by driving the
input to check the design behavior. we should check the behavior of the design by driving correct and
error input, in both the cases need to observe the design as it is behaving as expected, if not then
there will be an bug.

In verification we use Testbench/Verification environment to determine the correctness of the design


under test (DUT).
below are the functionality of the Testbench/Verification environment,
 Generate stimulus
 Apply stimulus to the DUT
 Capture the response
 Check for the correctness
 Measure progress against the overall verification goals

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