LSN 2

Microcontroller Architecture (PIC18F)

Department of
ECT358 – Microprocessors II Engineering Technology
 LSN 2 – Processor Architecture Review

• Harvard
– Separate data and program memory space (busses)
• Von-Neumann
– Only one bus between CPU and memory

Von Neumann
Harvard
Architecture Architecture

8-bit Bus Data

Memory

16-bit Bus
CPU 8-bit Bus Program
& Data
Memory
Program CPU
Memory

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 LSN 2 – Processor Architecture Review

• RISC
– A minimal set of simple instructions when combined can
accomplish every needed operation
• CISC
– A large set of complex instructions can singularly provide all
needed operations

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 LSN 2 – Processor Architecture Review

• Instruction Cycle

• Registers
– Special purpose (PC)
– General purpose

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 LSN 2 – Microchip’s MCU Families

10 – 12 MIPS
Up to 128 KB Program Flash
18 – 100 Pins

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 LSN 2 – PIC18 Families

Traditional PIC18

PIC18 J-series

PIC18 K-series
4KB 32KB 128KB
Program Flash
Typically products with higher memory also have higher pin-counts and higher levels of integrated peripherals

Traditional PIC18 PIC18 J-series PIC18 K-series

40 MHz, 10 MIPS, 5V 40-48 MHz, 10-12 MIPS, 3V 64MHz, 16 MIPS, 3V
Flash endurance 100k Flash endurance 1k – 10k Flash endurance 10k
EEPROM Emulate EEPROM EEPROM
Premium Features Most cost effective >32KB Flash Most cost effective <32KB Flash

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 LSN 2 – 8-bit PIC® Architecture

Program Space Data Space

21-bit Table Access 12-bit Data RAM

Program
Peripherals
Flash
Program Bus Data Bus
16-bit 8-bit CPU 8-bit
I/O Ports

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 LSN 2 – PIC18 Program Memory Map
Reset Vector 000000h

High Priority Interrupt Vector 000008h

Low Priority Interrupt Vector 000018h

21-bit Program Counter On-chip Program Memory

007FFEh

Stack Level 1 008000h

Stack Level 2

Stack Level 30
Unimplemented
Stack Level 31
Program Memory
(Read as ‘0’)
31 Level Stack
1FFFFEh

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 LSN 2 – PIC18 Data Memory Map

ACCESS RAM PIC18F

Register File Map
Bank 0 GPR

Bank 1 GPR

Bank 2 GPR

ACCESS RAM
ACCESS SFR

Bank 13 GPR

Bank 14 GPR

Bank 15 GPR

ACCESS SFR

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 LSN 2 – PIC18 Registers

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 LSN 2 – PIC18 Registers

• Status register
– Contains arithmetic status of the ALU
– Bits set or cleared according to the device logic

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 LSN 2 – PIC18 Programmer’s Model

Register File Program

(RAM) Memory
(Flash)
FSRn
ALU TBLPTR Constant
TABLAT Data
PC
BSR
WREG
STATUS
TOS
Stack
STKPTR

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 LSN 2 – PIC18 Pipelining

• Allows processor to overlap the execution of several

instruction to achieve higher instruction throughput
– Utilizes the fact that different processor components are not
fully utilized during the instruction execution process
– Prefetches instructions during execution of current
instructions

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 LSN 2 – PIC18 Pipelining

• PIC18 utilizes a two-stage pipeline for instruction

fetch and instruction execution

• Problems can arise from pipelining (Hazards)

– Data dependency hazard
– Control hazard
– Beyond scope of this class

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 LSN 2 – PIC18 Instruction Format
Data Memory
(Register File)

w f 07h

ALU 08h

09h

Data Bus
0Ah

0Bh
d
w f 0Ch

0Dh

0Eh

0Fh

10h
WREG

Decoded Instruction
Opcode d a Address
from Program
Memory:
Arithmetic/Logic Function
to be Performed Result
Destination
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 LSN 2 – PIC18 Instruction Format

• Byte oriented file register instructions

• Byte-to-byte move operations (2 words)

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 LSN 2 – PIC18 Instruction Format

• Bit-oriented file register operations

• Literal operations

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 LSN 2 – PIC18 Instruction Format

• Control operations

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 LSN 2 – PIC18 Instruction Format

• Mnemonic notation
– ‘F’ or ‘W’ indicate that the source or destination address is
the original register file location (F) or the working register
(W)

• Number formats
– Hex 0x7f, 20 (default), H’7f’ (alternative)
– Binary B’10011100’
– Decimal D’32’
– Octal O’777’
– ASCII A’C’, ‘C’ (alternative)
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 LSN 2 – PIC18 Instruction Format

• Instruction formats presented use 8-bits to specify a

register file (f field)
– Uses BSR to select only one bank at a time
– When operating on a data register in a different bank, bank
switching is needed
• Access Register
– When operands are in the access bank, no bank switching is
needed
– Most SFRs are in the access bank

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 LSN 2 – PIC18 Addressing Modes

• All MCUs use addressing modes to specify the

operand to be operated on

• Register direct mode

– Use an 8-bit value to specify a data register
MOVWF 0x25, A MOVFF 0x40, 0x50

• Immediate mode
– Actual operand provided, no need to access memory
MOVLW 0x25 ANDLW 0x40

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 LSN 2 – PIC18 Addressing Modes

• Inherent mode
– Operand is implied in the opcode field, opcode does not
provide address

• Indirect mode
– A special function register (FSRx) is used as a pointer to the
actual data register
LFSR FSR0, 0x25
MOVWF INDF0
MOVWF PREINC0

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 LSN 2 – PIC18 Addressing Modes

• Bit-direct mode
– Five instructions to deal with bits (BCF, BSF, BTFSC,
BTFSS, BTG)
BTG PORTB, 2

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 LSN 2 – PIC18 Instructions

• PIC18 has 77 instructions

• Data movement instructions

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 LSN 2 – PIC18 Instructions

• Add instructions

• Subtraction instructions

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 LSN 2 – Homework

• Reading
– 1.4 – 1.10

• Assignment – HW1
– E1.4, E1.5, E1.6, E1.7, E1.11, E1.12, E1.15, and E1.19

• References
– Microchip MCU2121 Course Notes
– Huang, H., PIC Microcontroller: An Introduction to
Software & Hardware Interfacing, Delmar Cengage
Learning 2007

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