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Low-Power and Fast Full Adder by Exploring

The document proposes new circuits for XOR/XNOR and XOR-XNOR gates that have lower power consumption and delay. Six new hybrid 1-bit full adder circuits are also proposed based on these novel gates. Extensive simulations show the proposed designs have superior speed and power over other designs in 65nm technology. A new transistor sizing method is also presented to optimize power-delay product using particle swarm optimization with fewer iterations.

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106 views

Low-Power and Fast Full Adder by Exploring

The document proposes new circuits for XOR/XNOR and XOR-XNOR gates that have lower power consumption and delay. Six new hybrid 1-bit full adder circuits are also proposed based on these novel gates. Extensive simulations show the proposed designs have superior speed and power over other designs in 65nm technology. A new transistor sizing method is also presented to optimize power-delay product using particle swarm optimization with fewer iterations.

Uploaded by

vishwas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Abstract: In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR
functions are proposed. The proposed circuits are highly optimized in terms of the power
consumption and delay, which are due to low output capacitance and low short-circuit power
dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel
full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits
in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To
investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso
simulations are performed. The simulation results, based on the 65-nm CMOS process
technology model, indicate that the proposed designs have superior speed and power against
other FA designs. A new transistor sizing method is presented to optimize the PDP of the
circuits. In the proposed method, the numerical computation particle swarm optimization
algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The
proposed circuits are investigated in terms of variations of the supply and threshold voltages,
output capacitance, input noise immunity, and the size of transistors.

Existing system:
TODAY, ubiquitous electronic systems are an inseparable part of everyday life. Digital circuits,
e.g., microprocessors, digital communication devices, and digital signal processors, comprise a
large part of electronic systems. As the scale of integration increases, the usability of circuits is
restricted by the augmenting amounts of power and area consumption. Therefore, with the
growing popularity and demand for the battery-operated portable devices such as mobile phones,
tablets, and laptops, the designers try to reduce power consumption and area of such systems
while preserving their speed.
Optimizing the W/L ratio of transistors is one approach to decrease the power-delay product
(PDP) of the circuit while preventing the problems resulted from reducing the supply voltage.

Further Details Contact: A. Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd Floor,
AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects
Proposed Method:
In this paper, we evaluate several circuits for the XOR or XNOR (XOR/XNOR) and
simultaneous XOR and XNOR (XOR–XNOR) gates and offer new circuits for each of them.
Also, we try to remove the problems existing in the investigated circuits. Afterward, with these
new XOR/XNOR and XOR–XNOR circuits, we propose six new FA structures.

Applications:
 Calculator, Digital Signal Processing, Image Processing.
Advantages:
 Power, area and delay.

System Configuration:-

In the hardware part a normal computer where TANNER TOOL software can be easily
operated is required, i.e., with a minimum system configuration

HARDWARE REQUIREMENT

Processor - Pentium –III

Speed - 1.1 GHz

RAM - 1 GB (min)

Hard Disk - 40 GB

Floppy Drive - 1.44 MB

Further Details Contact: A. Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd Floor,
AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects
Key Board - Standard Windows Keyboard

Mouse - Two or Three Button Mouse

Monitor - SVGA

SOFTWARE REQUIREMENTS

 Operating System :Windows95/98/2000/XP/Windows7

 Back End : TANNER TOOL

Further Details Contact: A. Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd Floor,
AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects

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