CS220A Lab#1

Introduction to Spartan-
Spartan-3E
and
d
Xilinx ISE

Mainak Chaudhuri
Indian Institute of Technology Kanpur
 Sketch
• Brief on Xilinx Spartan-3E FPGA
• Xilinx Integrated Synthesis Environment
(ISE)
– Example implementation of a full adder
• Verilog HDL
• Schematic

2
Field--programmable gate array
Field
• T
Two-dimensional
di i l array off generic
i
logic/storage cells interconnected by
programmable switches
– Each cell can be programmed to carry out simple
combinational functions
– The interconnection switches can be
programmed to decide how the result of one
function is input to another function or stored in
memory
– Typically the programming bits are downloaded
to the FPGA and the circuit is ready
• Done in the field as opposed
pp to in the fabrication
facility; hence the name FPGA
3
Field--programmable gate array
Field

Image source: Chu. FPGA Prototyping by Verilog Examples

4
 Xilinx Spartan 3E FPGA
• A 2D array off configurable
fi bl logic
l i blocks
bl k
(CLBs)
– Each
h CLB has
h four
f logic/memory
l / slices
l
– Each of the two logic slices (SLICEL) has
• Two four-input 16-entry look-up table (LUT) function
generators (can store any four-input function)
• Two registers
• Two multiplexors
• Arithmetic logic
g and carryy (two
( full adders))
– Each of the two memory slices (SLICEM) has
• Everything
y g of a logic
g slice
• Two 16-bit memory blocks (RAM16)
• Two 16-bit shift registers (SRL16) 5
 Xilinx Spartan 3E FPGA
• A 2D array off configurable
fi bl logic
l i blocks
bl k
(CLBs)
• I/O blocks (IOB)
– Controls I/O between logic/storage and the user
interfaces (slide switches, LEDs, LCD, etc.)
• Block RAM (random access memory)
– Each block can store 18K bits
• Multiplier blocks
– Each multiplier operates on two 18-bit inputs
• Digital clock manager (DCM)
– Routes clock throughout the FPGA 6
Xilinx Spartan 3E FPGA

Image source: Xilinx 7

Xilinx Spartan 3E FPGA

Image source: Xilinx 8

Xilinx Spartan 3E FPGA

Image source: Xilinx 9

 Xilinx Spartan 3E FPGA
• Five
Fi ffamily
il members
b
– 100K, 250K, 500K, 1200K, and 1600K logic gates
– We will use XC3S500E
• 500K gates
• 1164 CLBs
CLB (4656 slices);
li ) 46 rows, 34 columns
l
• Some CLB rows and columns are taken up by block
RAM, multiplier blocks, DCM
• 360K-bit block RAM (20 RAM blocks, each 18K bits)
• 20 multiplier blocks
• 4 DCMs

10
 Xilinx ISE
• Rest of the slides go over multiple examples
demonstrating how to use Xilinx ISE
– Can simulate Verilog code
– Can synthesize hardware on Spartan-3E FPGA
• Synthesizing a hardware means programming the
FPGA so that it models the desired hardware
• A subset of the CLBs, RAM blocks, multipliers, and the
switches will participate in implementing the specified
hardware
• In this lab,, you
y will do two syntheses
y
– Full adder: Verilog to synthesis
– Full adder: Mixed Verilogg and schematic to
synthesis
– Each synthesis task carries two marks 11
 Xilinx ISE
• Insert your USB stick in the USB drive and
accept ok when it prompts for opening the
medium
• Create a new directory/folder
y/ in yyour USB
stick
– You may call it CS220Labs
– For today’s lab, create two directories/folders
under CS220Labs
• You may name them Lab1_1, Lab1_2

12
 Xilinx ISE
• Click on the file manager (left bottom corner)
and navigate to /opt/Xilinx/14.7/ISE_DS
• Double-click
Double click run
run_ise.sh
ise sh and click on
“Execute”
– This will launch Xilinx Project Navigator,
Navigator the
primary interface for using the Xilinx ISE
• Click ok on “Tip
Tip of the Day”
Day panel
• If you receive a message telling you that a
license was not found
– The license manager will pop up automatically
– Load the license by browsing to
/opt/Xilinx/14.7/ISE_DS/common/licenses/Xilinx.l
ic 13
 Xilinx ISE
• In the Xilinx Project Navigator
– Click on File->New Project
j
– In Location box, write /media/CS220Labs/Lab1_1
– In Name box,, write full_adder
– Select HDL in top-level source type
– Click on Next
– For Evaluation Development Board, select
Spartan-3E
p Starter Board
– Leave everything else unchanged and click Next
– Click Finish
14
 Xilinx ISE
• In the Xilinx Project Navigator
– Click on Project->New Source
– Select Verilog Module from left menu
– Write full_adder in File name box
– Tickk the
h Add
dd to project box
b
– Click Next
– Leave
L everything
thi blank
bl k ini the
th nextt page and
d
click on Next
– Click Finish
– full_adder.v should automatically open in the
right
g pane
p of Xilinx Project
j Navigator
g
– You need to fill in the module full_adder
15
 Xilinx ISE
module
d l full_adder(a,
f ll dd ( b, b cin,
i sum, coutt
);

input a;
input b;
input cin;

output sum;
wire sum;
output cout;
wire cout;

assign sum = a^b^cin;

assign cout = (a & b) | (b & cin) | (cin & a);

endmodule
16
 Xilinx ISE
• In the Xilinx Project Navigator
– Save your Verilogg module by clicking
g the save
icon in the menu bar above
– Up to this point the procedure is same for
simulation and synthesis
– We will now explore how to simulate the full
adder design using the Xilinx ISim simulator

17
 Xilinx ISE: Simulation
• In the Xilinx Project Navigator
– We need to build a top-level environment Verilog
module
d l
– Project -> New Source
– Select Verilog Test Fixture from the left menu
– Write full_adder_top in File name
– Tick Add to project box
– Click Next
– Click Next
– Click Finish
– The code for full_adder_top.v
full adder top v will open
automatically for editing
18
 Xilinx ISE: Simulation
• In the Xilinx Project Navigator
– Remove the initial block and insert the following
code; leave everything else unchanged

always @(sum or cout) begin

$displa ("time %d %b + %b + %b = %b,
$display("time=%d: %b cout
co t = %b\n",
%b\n" $time
$time, a
a, b
b, cin,
cin
sum, cout);
end

iinitial
iti l begin
b i
a = 0; b = 0; cin = 0;
#5
a = 0; b = 1; cin = 0;
#5
a = 1; b = 0; cin = 1;
#5
a = 1; b = 1; cin = 1;
#5
$finish;
end 19
 Xilinx ISE: Simulation
• In the Xilinx Project Navigator
– Save the top-level module
– On left top side, change View from
Implementation to Simulation

– Select full_adder_topp in the Hierarchyy p

pane just
j
below the View
– In the lower left p
pane,, the ISim Simulator option
p
should appear; expand that option by clicking on
+ 20
 Xilinx ISE: Simulation
• In the Xilinx Project Navigator
– Double-click Behavioral Check Syntax under ISim
Simulator
– If you see a green tick, syntax check passed
• If not
not, see the errors in the dialog box at the bottom
and fix them; rerun syntax check
– Double-click
oub e c c SSimulate
u ate Behavioral
e a o a Model
ode
– ISim will open; check the results in the bottom
box
– Click on Default.wcfg to get a visual display of
the simulation; zoom to full view

21
 Xilinx ISE: Synthesis
• Synthesis on FPGA does not require a top-
level module
– The FPGA board provides the environment
– The inputs
p are provided
p through
g switches and
buttons
– The outputs are observed through LEDs
– The inputs and outputs are specified through a
user constraints file (UCF)
• Close ISim and switch to ISE Project
Navigator
g
– Change View from Simulation to Implementation
22
 Xilinx ISE: Synthesis
• We will map the three inputs on three slide
switches in the FPGA board
• We will map the two outputs on two LEDs
• Need to know the FPGA pin numbers
connecting to the switches and the LEDs
• Refer to Xilinx Spartan
Spartan-3E
3E user guide
– https://www.xilinx.com/support/documentation/
boards and kits/ug230 pdf
boards_and_kits/ug230.pdf
– Download and save it for future use

23
 Xilinx ISE: Synthesis
• Pages 15 and 16 of Spartan-3E user guide
discuss the slide switches
– The UCF location constraints specify the pin
numbers (L13, L14, H18, N17) and IO standards
of the switches
– Note the location of the switches on your FPGA
b d (should
board ( h ld be
b in
i one off the
h corners))

– We will tie “a” to L13, “b” to L14, and “cin” to

H18 (SW0, SW1, SW2) 24
 Xilinx ISE: Synthesis
• Pages 19 and 20 of Spartan-3E user guide
discuss the discrete LEDs

– We will map “sum”

sum to F12 and “cout”cout to F9
(LED0 and LED7)
– Notice
ot ce location
ocat o oof tthe
e LEDss in you
your FPGA
G boa
board
d
• Should be above the slide switches
25
 Xilinx ISE: Synthesis
• Let’s come back to the Xilinx ISE Project
Navigator and prepare the UCF
– Expand the User Constraints option in the
second pane on the left by clicking +
– Double-click I/O Pin Planning (PlanAhead) – Pre-
Synthesis

– This will launch PlanAhead (click on Yes)

26
 Xilinx ISE: Synthesis
• Close the Welcome to PlanAhead pane by
clicking Close
• In I/O Ports pane expand the Scalar ports by
g+
clicking
– This will list the inputs and outputs of the
full_adder
_ module

27
 Xilinx ISE: Synthesis
• PlanAhead
Pl Ah d pin
i assignment
i t
– For each input (a, b, cin), select its row, and set
Site (L13
(L13, L14
L14, H18),
H18) check Fixed,
Fixed set I/O Std to
LVTTL, and Pull Type to PULLUP
– For each output (sum, cout), select its row, and
set Site (F12 and F9), check Fixed, Set I/O Std to
LVTTL, and Drive Strength to 8

– Save by clicking the save icon located at top left

corner (below File)
– File->Exit->Ok (this will close PlanAhead) 28
 Xilinx ISE: Synthesis
• PlanAhead tip
– Ensure that all fields for a pin as specified in the
user guide are filled in
– For example, if the user guide specifies PULLUP
or PULLDOWN for a pin, you cannot leave that
unspecified in PlanAhead

29
 Xilinx ISE: Synthesis
• Return back to the ISE Project Navigator
– Next step is to synthesize and implement the
design
– Double-click on Synthesize – XST option in the
second pane on the left (below User Constraints
option which you expanded)
– Once you get a green tick indicating completion
of synthesis, you can click on Design Summary
(Synthesized) at the bottom of the pane on the
right
• See how many CLB slices and LUTs your design has
consumed
30
 Xilinx ISE: Synthesis
• In the ISE Project Navigator
– Double-click Implement Design
g option (just
j
below Synthesize – XST)
– Once this step completes successfully, you can
go back to the Design Summary (Implemented)
tab and select Pinout Report from the left menu
• Ch
Checkk that
th t a, b,
b cin,
i sum, coutt are mapped
d to
t th
the
correct pins
– Double-click Generate Programming File option
(just below Implement Design option on the
second left pane)
p )
• This will generate the bits needed to program the
FPGA so that it can implement your design 31
 Xilinx ISE: Synthesis
• In the ISE Project Navigator
– Double-click Configure Target Device option (just
b l
below Generate
G t Programming
P i File)
Fil )
• Click ok
• This will launch iMPACT,
iMPACT the Xilinx tool for
programming the FPGA
– In the FPGA board, the JTAG jumpers need to
configured
fi d correctly
l first
fi
• Page 26 of the user guide shows the correct jumper
configuration (you need to keep only the middle
jumper connected)
• DO NOT LOSE ANY OF THE JUMPERS; BEFORE
RETURNING THE BOARD
BOARD, REMEMBER TO PLACE THE
JUMPERS BACK
32
 Xilinx ISE: Synthesis
• JTAG jumper configuration

33
 Xilinx ISE: Synthesis
• After doing the jumper setting, power on the
FPGA board
– The red LED beside the power switch should
light up
– Connect the USB cable between the computer
and the FPGA board
• The green LED beside the cable port on the FPGA
board should light up indicating a healthy connection
• In iMPACT menu
men
– Double-click on Boundary Scan
– Right-click on the main area and select Initialize
Chain; select Yes 34
 Xilinx ISE: Synthesis
• In
I iMPACT
– Automatically a file selection will open for
programming the FPGA
• Select
/media/CS220Labs/Lab1_1/full_adder/full_adder.bit
• It will ask you if you want to attach a PROM; say No
• Select Bypass for the next one
• Select Bypass for the next one too
– A Programming Properties selection menu will
ope
open
• Click on Apply and then Ok
– You will see a chain of three devices
• The green one is the FPGA; the other two are memory
devices which we bypassed 35
 Xilinx ISE: Synthesis
• Right-click on the green FPGA
– Select Program
g
– If the FPGA is programmed correctly it will say
Program Succeeded and you will see the orange
Done LED light up
• Now the FPGA is running your hardware
– We need to give inputs and observe the outputs
– Use the slide switches to p
provide values for a,, b,,
cin
– Check if the correct LEDs glow
• This concludes the first assignment of Lab1
36
 Notes for healthy FPGA
• Always power on the FPGA after doing the
jumper setting
– Never change jumper setting with the FPGA
powered on
• Always connect the USB cable after powering
on the FPGA
• Always power off the FPGA before
disconnecting the USB cable
– Do not pull out the USB cable when the FPGA is
powered on
• Keep all jumpers connected to the board
when you are not using the board
37
 Xilinx ISE: Synthesis
• Save the iMPACT project
– /media/CS220Labs/Lab1_1/full_adder/full_adder.i
pf
• File->Exit
– Agree to save when it asks
– This will close iMPACT
• We will now start the second assignment

38
 Xilinx ISE: Assignment#2
• We will learn how to create schematics of
digital design in Xilinx
• Start a new project in Project Navigator
– File ->
> New Project
– Location: /media/CS220Labs/Lab1_2
– Name: full_adder_schematic
full adder schematic
– Top-level Source Type: Schematic
– Click Next
– Select Evaluation Board
– Click Next
– Click Finish 39
 Xilinx ISE: Assignment#2
• Idea of the assignment
– We will create a Verilog
g module to define a two
input xor gate
– We will use this xor gate to create a schematic of
the full-adder
– Next we will simulate this by writing a Verilog
Test Fixture
– We will also synthesize it on FPGA

40
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– Project -> New Source -> Verilog Module
• Name: myxor
• Next, Next, Finish
module myxor(x,
myxor(x y,
y z);
input x;
input y;
output z;
wire z;

assign z = (x & ~y)

y) | (~x
( x & y);
endmodule
41
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– To be able to use myxor in a schematic, we need
to create a symbol for it
– Select myxor (myxor.v) in left upper pane
– Expand Design Utilities in left lower pane and
double-click Create Schematic Symbol
– Project -> New Source -> Schematic
• File name: fuller_adder_sch
• Click Next, Finish
– The schematic drawing board will open now
– You can add components by selecting the
Symbols tab at the bottom of the left pane 42
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– Select General category
g and title from symbols
• Place the title box at the left bottom corner of the
drawing board
• Right-click
Ri ht li k on the
th title
titl bbox andd select
l t Object
Obj t
properties
• Put Full adder as the NameFieldText
• Click Apply and ok
– Select yyour p
project
j path
p in category
g y and myxor
y
from symbol
• Place two myxor symbols on the drawing board
– Select Logic category
• From symbol, select three and2 and one or3 gates43
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– Connect the g
gates to build the full adder
• Use the wiring icon to draw wires

– Use the I/O Marker icon to name the inputs and

outputs
– Right-click on a marker, select Object Properties
44
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– Use the I/O Marker icon to name the inputs and
outputs
– Place a I/O Marker on a terminal by selecting the
I/O Marker icon and then clicking on the terminal
– Right-click on a placed marker of a terminal,
select Object Properties, change Name under
Nets
– Click
Cli k Apply
A l and d then
th Ok
– Name the inputs a, b, cin
– Name the outputs sum, cout
– Save the schematic by clicking the save icon 45
 Xilinx ISE: Assignment#2
• In Xilinx ISE Project Navigator
– Next we will simulate the design
g and then
synthesize
– This procedure is same as the previous
assignment starting from slide 18
– Follow the steps from there

46