Experiment No: 1

Date:

FAMILIARISATION OF LOGIC GATES

Aim:-
To familiarize with logic gates IC packages and to verify the truth table of the logic gates.

Components and equipments required:-

ICs 7400
7402
7404
7408
7432
7486
IC trainer Kit

Theory:-
Circuit that takes the logical decision and the process are called logic gates. Each gate has one or
more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE:
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The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.

Procedure:-
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

NAND GATE:

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

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NOR GATE:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

NOT GATE:

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A Y
0 1
1 0

AND GATE:

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

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OR GATE:

A B Y
0 0 0
0 1 1
1 0 1
1 1 1

EXOR GATE:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

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Result:-
Familiarized with logic gates IC packages and verified truth table of logic gates.

Experiment No: 2
Date:

UNIVERSAL GATES
Aim:-

To verify the property of NAND and NOR gate.

Components and equipments required:-

ICs 7400
7402
Digital trainer kit

Theory:-
NAND and NOR gate are known as universal gates. Because using three gates we can
implement all other gates such as AND, OR, XOR and NOT.

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NAND as NOT
We have 2-input NAND gate whose input are properly connected together so that variable
A is applied to both in this configuration ,NAND gate simply act as an inverter.

NAND as AND
NAND gate is used as an inverter to change AB=AB which is the desired AND functions.

NAND as OR
The OR operation can be implemented using NAND gates as connected in figure NAND 1
and 2 are used as in erters to complement the inputs so as to y=A+B using De Morgan’s theorem.

NAND as NOR
Here NAND gate 1 and 2 are used for inversion of AND 4th gate is used to invert the result
A+B as A+B.

NAND as XOR
XOR function is implemented dy using four NAND gate. The last is y=A. (A+B) +B.
(A.B) where is simplified to change y=AB+BA, using de Morgan’s theorem.

NAND as X-NOR
X-NOR function is implemented dy using five NAND gate. The NAND gate is used to
complement the functions to obtain the desired X-NOR function.

NOR AS NOT
The two inputs of the NOR gates are property connects together. In this combinations the
NOR gate is simply to get B=A.

NOR as OR
Nor gate is used to complement A+B to get the OR function A+B.

NOR as AND
NOR gates 1 and 2 are used for complementing the inputs and the result of these inverted
outputs are used to get desired AND functions.

NOR as NAND
Here the output obtained from AND function inverted using NOR gate in order to get
desired NAND function.

NOR as X-OR
Four NOR gates are used to implemented the XOR function. The final output is simplified
to get XOR function.

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NOT using NAND

A Y
0 1
1 0

AND using NAND

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR using NAND
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

NOR using NAND

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

XOR using NAND

A B Y
0 0 0
0 1 1
1 0 1

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1 1 0

NOT using NOR

A Y
0 1
1 0

OR using NOR
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

AND using NOR

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

NAND using NOR

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

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XOR using NOR

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Procedure:-
1. Verify that all the components and wire are in good condition.
2. Set up the circuits and send the input bit combination.
3. Observe the output corresponding to the input condition and enter it in the truth table.

Result:-
Verified the property of NAND and NOR gates.

Experiment No: 3
Date:

VERIFICATION OF DE-MORGANS THEOREM

Aim:-
To verify De-Morgan’s theorem for two variables.

Components and equipments required:-

ICs 7400
7402
IC trainer kit

Theory:-
De-Morgan’s theorem states that

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A+B=A.B
A.B=A+B
De-Morgan’s theorem is very useful to simplify the Boolean expressions. When the
expression is small the number of logic gate required to realize a Boolean expression is less. In
other word De-Morgan’s theorem helps to save the hardware cost and reduce the circuit
complexity.

A.B=A+B

A B A.B A+B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

A+B=A.B

A B A+ B A.B
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

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Procedure:-
1. Test all components using digital IC tester.
2. Set up the circuit as shown in the figure and one by one observe the output
corresponding to the input combinations are enter into the truth table.

Result:-
Verified the De-Morgan’s theorem.

Experiment No: 4
Date:

HALF ADDER AND FULL ADDER

Aim:-

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1. To design and set up a half adder using

a) XOR gates and NAND gates.
b) NAND gates only.
2. To design and set up a full adder using
a) XOR gates and NAND gates.
b) NAND gates only.

Components required:-
ICs 7400
7486
IC trainer kit

Theory:-
Arithmetic circuits are those circuits which perform arithmetic operations. A half adder
adds two binary digits giving sum as S=A+B and a carry bit C=A.B. A half adder has no
provision to add a carry from lower bit’s when binary numbers are added. When two inputs and
a carry are to be added, the number of inputs bit become 3 and inputs combinations increases to
8. For this a full adder is used. A full adder adds 2 inputs A & B and a carry from the previous
addition called carry in Cin and outputs the sum bit S=A+B+ Cin and Cout=A.B+A.Cin+B.Cin
or Cout=AB+(A+B.Cin).

Half adder using XOR gates and NAND gates.

A B S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half adder using NAND gates only

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Full Adder

A B C Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 SUM = A’B’C + A’BC’ + ABC’ + ABC
1 1 0 0 1
1 1 1 1 1

CARRY = AB + BC + AC
Simplification

Sn = C+ B + ABC + A

= ( +C( + A B)

= A⊕B) + C (A + )(

= ( A⊕B ) + C ( )

= (A⊕B) + C ( ⊕ )

= A⊕B⊕C

Cn =C B + CAB +C A + AB

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=C( +( +C ) AB

= C (A⊕B) +AB)
Full adder using XOR gates and NAND gates

Full adder using NAND gates only

Procedure:-
1. Verify whether all the components and wires are in good condition.
2. Set up the half adder circuit and feed the input bit combinations
3. Observe the output corresponding to input combination and enter it in the truth table.
4. Repeat the above steps for full adder circuits

Viva:-
1. Differentiate between half adder and full adder.
2. Realize half adder and full adder using NOR gate.

RESULT:-
A half adder & full adder circuits designed and setup & truth table of both has been verified.

Experiment No: 5

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Date:

HALF AND FULL SUBTRACTOR

Aim:-
To design and set up a half sub tractor and a full sub tractor and realize it by using basic
gates and NAND gates.

Components and equipments required:-

ICs 7404

7408

7486

7400

7432

IC trainer kit

Theory:-
A half subtractor is a combinational circuit that subtracts two bits and procedure their
difference. It also has an output to specify a 1 has been a borrow.
It is the simplest binary subtractor circuit. It has two inputs and two outputs. One is the difference
D and other is the borrow B.
Half subtractor is used to subtract the LSB of the subtrahend from the LSB
of the minuend. The difference D=A+B and borrow Bout =AB.If there is a borrow during the
subtraction pf the LSB’s it aspects the subtraction in the next higher column; the subtraction bit is
subtracted from the minuend bit, considering the borrow from that column. This is performed by
full subtractor. It subtracts open bit(B)from another bit (A) when there is a borrow Bin.In full
subtractor circuit difference is given by D=A+Bin and Bout=AB+ABin+BBin.

Half subtractor using basic gates

A B D Bn
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Half subtractor using NAND gates only

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Full subtractor

A B C D Bn
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0 D=B⊕A⊕C
1 1 1 1 1

Bn=A (B⊕C ) + C

Simplification

D = C+ B + ABC+ A

=C( +AB)+ ( B+A )

= C[ ]+ (A⊕B)

=C( ) + C (A ⊕ B )

= C⊕A⊕B

Bn = C+ BC+ B+ A B C

= B (C+ ) + C ( + AB)

= B+C( + AB)

= C [( + AB) + B]

=C( ⊕ )+ B

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Full subtractor using basic gates

Full subtractor using NAND gates only

Procedure:-

a) Verify whether all the components and wires are in good condition.
b) Set up the half subtractor circuit and feed the input bit combinations.
c) Observe the output corresponding to input combination and enter it in the truth table.
d) Repeat the above steps for full subtractor circuit

Viva:-

Differentiate between half subtractor and full subtractor.

Result:-

Half subtractor and full subtractor circuits are designed and setup and truth table is verified.

Experiment No: 6

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Date:

ADDER AND SUBTRACTOR CIRCUITS USING 7483

Aim:-
To design and set up the following arithmetic circuits using 4 bit binary adder IC 7483

1 4 bit binary adder

2 8 bit binary adder
3 4 bit add/subtract circuit
4 Single digit BCD adder

Components and equipments required:-

ICs 7400
7483
7486
7410
IC trainer kit

Theory:-
Several parallel adders are available as ICs. The most common one is a parallel adder IC
that contains four inter connected full adders and a carry look ahead circuit needed for high
speed operation. 7483 is a TTL 4 bit parallel adder chip. The inputs of 7483 are 4 bit numbers
A3A2A1A0 and B3B2B1B0 and the carry in to the LSB position. The outputs are the sum bits
S3S2S1S0 and carry out of the MSB position. The addition of large binary numbers can be
accomplished by cascading two or more parallel adder chips.

Using 7483 ICs can do subtraction. In the 2’s complement method,

the subtrahend is changed to its 2’s complement from and then added to the minuend. The sum
output of the adder circuit represents the difference between the numbers. Since the 2;s
complement of the number is obtained by adding one to 1’s complement from, C in is made to 1
and added to LSB of adder.

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Single digit BCD adder

S3 S2 S1 S0 c
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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Procedure:-
1. Test all components and ic packages using multimeter and digital ic tester
2. Set up the nibble adder and try a few nibble addition.
Verify the working of the circuit.

3. Set up the byte adder and verify the working of the circuit trying out with bytes.
4. Set up the add/subtractor circuit. Make sub=0 and verify whether it work as a nibble
adder
5. To function as a subtractor make SUB =1 A3A2A1A0 =1010 and B3B2B1B0=1001.Verify
whether the S3S2S1S0=0001.
6. Keep SUB =1, reverse the value of the nibble and verify the output =1111=2’s
complement of 0001.
7. Set up BCD adder and verify the result

Viva:-
1. Set up a 9’s complement circuit using 7483
2. Set up a one digit BCD subtractor
3. Set up a one digit BCD adder/subtractor with control input.

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Result:-
Designed and set up the following circuits using 7483 for

a) 4bit binary adder

b) 8 bit binary adder
c) 4bit add/subtract circuit
d) Single digit BCD adder

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Experiment No: 7
Date:

CODE CONVERTERS
Aim:-
To design and set up the following circuits

i.) 4 bit binary to gray code converter.

ii.) 4 bit gray to binary code converter.
iii.) 3 bit binary to gray and gray to binary code converter using mode controller.

Components and equipments required:-

ICs 7486
7408
IC trainer kit

Theory:-
To convert the binary number to corresponding gray code, the following rules are applied
1. The MSB in the gray code is same as the corresponding bit in the binary
number
2. Going from left to right, add each adjacent pair of binary digits to get the gray
code digit.
Disregard carries
As the first step to design a binary to gray code converter, set up a truth table with binary
number B3B2B1B0 And corresponding gray code numbers.G3G2G1G0.Set up a circuit realizing the
simplified logic expressions obtained using k-maps for Gs as the function of Bs
To convert from gray code to binary, the following rules are applied
a) The MSB in the binary is same as corresponding bit in the gray code
b) Add each binary bit generated to the gray code bit in the next adjacent position.
Disregard the carry
To design the gray to binary code converter, set up the truth table and get simplified
expressions using K-maps for each binary bit as a function of gray code bots. Each gray code
number differs from the preceding by a single bit.

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4-bit binary to gray code converter

Binary Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
B3B2
0 0 0 0 0 0 0 0 B1B0 00 01 11 10
0 0 0 1 0 0 0 1 00 0 0 0 0
0 0 1 0 0 0 1 1
01 1 1 1 1
0 0 1 1 0 0 1 0
11 0 0 0 0
0 1 0 0 0 1 1 0
10 1 1 1 1
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1 G0=B0⊕B1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
B3B2
1 0 0 1 1 1 0 1
B1B0 00 01 11 10
1 0 1 0 1 1 1 1
00 0 1 1 0
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0 01 0 1 1 0
1 1 0 1 1 0 1 1 11 1 0 0 1
1 1 1 0 1 0 0 1 10 1 0 0 1
1 1 1 1 1 0 0 0
G1=B1⊕B2

B3B2 B3B2
B1B0 00 01 11 10 B1B0 00 01 11 10
00 0 1 0 1 00 0 0 1 1
01 0 1 0 1 01 0 0 1 1
11 0 1 0 1 11 0 0 1 1
10 0 1 0 1 10 0 0 1 1

G2=B2⊕B3 G3=B3

4-bit binary to gray code converter

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4-bit gray to binary code converter

Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 G3G2
0 0 0 1 0 0 0 1 G1G0 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 1 1
0 0 1 1 0 0 1 0 01 0 0 1 1
0 1 0 0 0 1 1 1 11 0 0 1 1
0 1 0 1 0 1 1 0 10 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1 B3=G3
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0 G3G2
1 0 1 0 1 1 0 0 G1G0 00 01 11 10
1 0 1 1 1 1 0 1 00 0 1 0 1
1 1 0 0 1 0 0 0 01 0 1 0 1
1 1 0 1 1 0 0 1
11 0 1 0 1
1 1 1 0 1 0 1 1
10 0 1 0 1
1 1 1 1 1 0 1 0

G2=G2⊕G3

G3G2
G1G0 00 01 11 10
00 0 1 0 1
01 0 1 0 1
11 1 0 1 0
10 1 0 1 0

B1= + + G1 G3 + G3

= G1 ( +G3 G2) +G1 ( + G3 )

= G1 ( ⊕ )+ (G3⊕G2)

= ⊕ ⊕

G3G2
G1G0 00 01 11 10
00 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0

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⊕ ⊕ ⊕ ⊕

⊕ ⊕ ⊕ ⊕

⊕ ⊕ ⊕

4-bit gray to binary code converter

3-bit binary to gray/gray to binary code converter using mode converter

M D2 D1 D0 Y2 Y1 Y0 MD2
0 0 0 0 0 0 0 D1D0 00 01 11 10
0 0 0 1 0 0 1 00 0 1 1 0
0 0 1 0 0 1 1 01 0 1 1 0
0 0 1 1 0 1 0 11 0 1 1 0
0 1 0 0 1 1 0 10 0 1 1 0
0 1 0 1 1 1 1
0 1 1 0 1 0 1
0 1 1 1 1 0 0 Y2=D2
1 0 0 0 0 0 0
1 0 0 1 0 0 1 MD2
1 0 1 1 0 1 0 D1D0 00 01 11 10
1 0 1 0 0 1 1 00 0 1 1 0
1 1 1 0 1 0 0 01 0 1 1 0
1 1 1 1 1 0 1 11 1 0 0 1
1 1 0 1 1 1 0 10 1 0 0 1
1 1 0 0 1 1 1
Y1=D1⊕D2

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MD2 Y0 = MD2 + D0 + D0 D2 + D1 D0 MD2 +

D1D0 00 01 11 10 D1 + D1
00 0 0 1 0
01 1 1 0 1 =MD2 ( ⊕ )+ (D1⊕ D0) + (D1⊕ D0)
11 0 0 1 0
10 1 1 0 1 = MD2 ( ⊕ )+( + ) (D1⊕ D0)

= MD2 ( ⊕ )+ (D1⊕ D0)

=MD2 ⊕ D1 ⊕ D0

Procedure:-
1. Test all the components and IC packages using multimeter and digital IC tester.
2. Verify the truth tables of the circuit by feeding the output bit combinations

Viva:-
1. Design and set up a circuit to convert BCD no: intoexcess-3
2. Set up BCD to gray code converter
3. Set up a gray to BCD code converter

Result:-
Designed and implemented the following
a) 4 bit binary to gray code converter
b) 4 bit gray to binary code converter
c) 3 bit binary to gray and gray to binary code converter using mode controller.

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Experiment No: 8
Date:

MULTIPLEXERS
Aim:-
To study multiplexer using gates and to study the functions of multiplexer IC 74151

Components and equipments required:-

ICs 7411
7432
7404
74151
IC trainer kit

Theory:-
Multiplexing means sharing. A multiplexer (MUX) or data selector is a logic circuit that
accepts several data inputs and allows only one of them at a time to get through output.

The sorting of the desired data input to the output is controlled by select inputs, determines which
data input will be switched to the output. For e.g. The output z will equal to the data input D 0 for
some particular input code; z will equal to the data input D1 for some particular input code so on.
In other words we can say that a multiplexer selects one of out of N input data sources and
transmits the selected data to a single output channel. This is called multiplexing.

Pin out 74151

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IC symbol

Circuit diagram

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Implementation of the Boolean expression using multiplexer

F(A,B,C,D) = Σm(8,7,9,13,15)

i0 i1 i2 i3 i4 i5 i6 i7
0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15

0 A 0 0 A 0 1

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Procedure:-
1. Test all components and IC packages using multimeter and IC trainer kit
2. Set up the circuit using IC 74151 and verify the truth table.

Viva:-
1. Design a 4 line to 1 line multiplexer using NAND gates only
2. What are the applications of multiplexer?

Result:-
Designed and set up multiplexer circuits and observe its response.

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Experiment No: 9
Date:

DECODERS
Aim:-
To study the combinational logic design using decoders.

Components and equipments required:-

IC 74154
7411
7404
IC trainer kit

Theory:-
Decoder can be used to realize logic circuits. A decoder is nother but a demultiplaxer with
data input grounded the 1:16 demultiplexer is IC 74154 can be used as a decoder also if function
as a 4 to 16 decoder when its data i/p and the strobe input are grounded .since the data input is
grounded output is at active low. For example if we select input word ABCD is 1010. 1/10 will be
at logic 0 state and all other input will be at logic high state.
Suppose the decoder is used for implementing the Boolean expression
f(A,B,C,D)=ABCD+ABCD+ABCD+ABCD+ABCD. It ans that the min terms are
corresponding to the numbers 2,4,7,8 and 12. If binary numbers corresponding to the these are
applied at the select input, corresponding data output will be 0. The output ½, 1/4, 1/7, 1/8 and
1/12 must be invert followed by OR is equivalent to NAND.

S1 S0 D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D

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IC 74154

Implementation of Boolean expression using decoder IC 74154

F(A,B,C,D) = Σm(2,4,7,8,12)

Data select o/p

A B C D o/p
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

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Procedure:-
1 Test the IC and connecting wires before doing the experiment.
2 Set up the circuit as shown in figure and verify its truth table.
3 Implementation of Boolean expression using a decoder. The function that is to be
implemented using a decoder. f(A,B,C,D)=ABCD+ABCD+ABCD+ABCD.
Decoder IC 74154 is used to realize the function. The given function is also expressed
as F(A,B,C,D) = Σm(2,4,7,8,12) output of IC 74154 are active low . when active low input are
fed to a NAND gate input it is equivalent to OR operation.

Result:-
Designed and set up a decoder circuit and observed its output response.

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Experiment No: 10
Date:

FLIP FLOP USING GATES

Aim:-
To design and set up the following flip flops using gates
a) Clocked SR flip flop
b) JK flip flop
c) Master slave JK flip flop
d) D flip flop
e) T flip flop
To familiarize flip flop ICs 7473, 7474 and 7476

Components and equipments required:-

ICs 7400
7410
7473
7474
7476
IC trainer kit

Theory:-
Flip flop is the basic building block in any memory system. Since its output will
remain in its forced to change by some means. Flip flop has mainly two states SET or RESET
state. Flip flops are classified as +ve edge triggered and –ve edge triggered flip flops.

Clocked SR flip flop:

S and R stands for set and reset. There are four input combinations possible at the inputs.
But S=R=1 is forbidden since the output will be indeterminate. When the flip flop is switched
ON its output state will remain uncertain. When an initial state is to be assigned, two separate
inputs called preset are used .They are active low inputs.

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JK flip flop:

In JK flip flop, J and K are two inputs. When J=1, the flip flop is in set state and when K=1
the flip flop will be in reset state, the indeterminate output state of SR flip flop S=R=1 is avoided
by converting it to JK flip flop

Master slave JK flip flop:

The race-around condition of JK flip flop is reduced in master slave. Racing is the
toggling of output more than once during a +ve clock edge. Master slave JK flip flop is created
by cascading two JK flip flops. The clock fed to the master is inverted and fed to the slave. This
ensures that the slave follows master eliminates chance of racing.

D flip flop

It has only one input referred to as D input or data input. The input data is transferred to
the out put after clock pulse applied flip flop can be derived from JK flip flop by using J input as
the D input and J is inverted and fed to the K input.

T flip flop

T stands for toggle. The out put toggles when a clock pulse is applied. That is the out put of
the flip flop changes state for an input pulse. TFT can be derived from JK flip flop by shorting J
and K inputs.

Flip flop ICs:

7476 is a dual –ve edge triggered master slave JK flip flop with preset and clear
facility. When the flip flop is switched on, its output state will be uncertain. When an input pulse
is to be assigned, two separate inputs called preset and clear is used. This 7476 is a 16 pin
chip.7473 is a dual –ve edge triggered master slave JK flip flop. It does not have preset input.
7476 is a +ve edge triggered dual D flip flop with preset and clear.

input output
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 X

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Clocked D flip flop

Input Output
D Qn+1
0 0
1 1

JK flip flop

input output
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn

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JK flip flop with clear and preset

input output
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn

D flip flop using JKFF

Input Output
D Qn+1
0 0
1 1

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Master Slave JK flip flop

input output
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn

T flip flop using JKFF

Input Output
T Qn+1
0 Qn
1 Qn

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Pin out of IC 7473, 7474, and 7476

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Procedure :-
1. Test all components and ic packages using multimeter and ic trainer kit
2. Set up the flip flop using gates and verify their truth table.
3. Verify the truth table s of 7473,7474 and 7476 ics.
Viva:-
1. What is race around problem? How is it avoided?
2. How does a flip flop act as a memory element?
3. How does a flip flop act as a frequency divider?
Result:-
Designed and set up the flip flop and truth tables is verified. Flip flop ICs are
familiarized and its truth table is verified.

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Experiment No: 11
Date:

SHIFT REGISTERS
Aim:-
To set up and verify the performance of the serial in parallel out shift register using JK
and D flip flop.

Components and equipments required:-

ICs 7476
7474
IC trainer kit

Theory:-
A register is simply a group of the flops that can be used to store a binary number. A shift
register is nothing but a register which accepts a binary number and shift it. The data can be
entered to the shift register either in parallel or series. Similarly, the output can be taken from it
either serial or in parallel. four basic register type can be constructed like, serial in serial
out(SISO),serial in parallel out (SIPO),parallel in serial out(PISO),parallel in parallel out(PIPO).

Serial input shift register

As its name suggests, serial input shift register allows them to enter serially. The output
data can be available in parallel or serial.

Serial / parallel right shift register using mode control

In this type of shift register data can be fed in serial or parallel using mode control pin.
Output is taken either in serial or in parallel. Serial input is fed thought ‘A’ input and parallel
input is fed thought ‘ABCD’. Serial output is taken from ‘QD’ and parallel outputs from QA QB
QC QD.

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Serial input right shift register using JKFF

Serial input right shift register using DFF

Input: 1011 Waveforms for right shift register

Clock Q0 Q1 Q2 Q3
0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 0 1 1 0
4 1 0 1 1

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Serial / parallel right shift register using mode control

Procedure:-
1. Test all components and IC packages using multimeter and digital trainer kit
2. Set up serial input shift register using JKFF. Clear all the flip flops using CLEAR pins. A
low input to CLEAR and PRESET will Q output 0 and 1 respectively.
3. Apply a 1HZ clock and observe the bits are shifting right. Repeat the above step using D
flip flop
4. Set up serial/parallel input shift register. Enter a data serially keeping load /shift=1.Apply
clock pulses and note the output after each clock pulse.
5. Enter the data parallel with load/shift=0.Output can be obtained in parallel or in serial
form. Repeat for various input combinations.
Viva:-
1. How much time is required to shift a 12 bit number into a serial 12 bit serial shift register
if the clock is 1 MHZ?
2. What do you mean by the modulus of a shift register?
Result:-
The give shift register has been set up truth is verified.

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Experiment No: 12
Date:

ASYNCHRONOUS COUNTERS
Aim:-
To design and set up the following counters using JK flip flop.

i.) 4 bit binary up counter(mod 16)

ii.) 4 bit binary down counter(mod 16)
iii.) 3 bit binary up-down counter
iv.) Decade counter
Components and equipments required:-
ICs 7476 or 7473
7400
7486
IC trainer kit
Theory:-
A counter is a circuit that produces a set of unique outputs combination in relation to
the number of applied pulses. The no. of unique output of a counter is known as it’s modulo or
mod number.

In asynchronous counters, the flip flops are not given the clock simultaneously.
Therefore the propagation delay increases with number of flip flop used. Four JK flip flops must
be used in toggle mode to count 16 states (JK flip flop can be converted to T flip flop by
shorting J and K inputs)

4 bit binary up counter (Ripple counter)

In the circuit set up all flip flops are connected to a high state.7476 is a dual JK master slave
flip flop with preset and clear. A ripple counter comprising of n flip flop can be used to count up
to 2n pulses. A circuit with 4 flip flops gives a maximum count of 24=16.The counter gives a
natural binary count from 0 to 15 and resets to initial condition on 16th input pulse.

With the application of the first clock pulse Q0 changes from 0 to 1.Q1,Q2 and Q3
remains unaffected. With second clock pulse,Q0 becomes 0 and Q1becomes 1. At the arrival of
15th clock pulse all Q output will become 13.at the 16th clock pulse all Q outputs reset and the
cycle repeats.

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4 bit binary down counter (Ripple counter)

In this circuit, the succeeding flip flops are clocked by the Q output at preceding flip flop.
The outputs are taken from Q outputs, all the Q outputs are set.0At the arrival of 16th clock pulse
all Q output become rest and cycle continues.

3 bit binary up down counter:

The direction of counting sequence is made depend on a mod control input. Output of
preceding flip flop is connected to clock input of the succeeding flip flop. When mod control is
one, Q output are connected to the clock inputs of the succeeding flip flops. If mod control is 0
the q output is connected to the clock input.

Decade counter:

The circuit of the decade counter is similar to 4 bit ripple counter but with the aid of a
logic circuit, the count is limited to 9.as soon as the count 1010 takes place, a NAND gate clears
the flip flops and counting restarts fro 0.

4- Bit binary up counter:

State diagram

0 1 2 3 ------------- 15

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Clk Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
.
.
.
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

Waveforms of 4-bit binary up counter:

4- Bit binary down counter:

State diagram

15 14 13 12 ------------- 0

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Clk Q3 Q2 Q1 Q0
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
.
.
.
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0 Waveforms of 4-bit binary up counter:

3- Bit up/down counter:

M=1 State diagram

0 1 2 3 ------------- 7

M=0 State diagram

7 6 5 4 ------------- 0

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Decade counter:

State diagram

0 1 2 3 ------------- 9

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Procedure:-
1. Test all ics using multimeter and ic trainer kit
2. Set up the circuit for 4 bit ripple counter. Connect PRESET to 5v to disable it.
3. Clear all flip flops output initially connecting common CLEAR terminal to logic
0.after the usage of clear pins connect them to logic one or keep them open. Apply
mono pulses, counter starts counting up.
4. Move clock inputs of every flip flop except FF0 fro Q output to the Q outputs. Preset
all FFs by connecting common PRESET terminal to logic 0.Apply mono pulses
,counter will starts counting downwards.
5. Set up the decade c counter circuit and repeat the steps for counting up.
6. Set up 3 bit up/down counter and observe the forward(up)counting when mod control
is one and backward(down)when mod control is 0.

Viva :-
1. How many flip flops are needed to count mod-128 binary counter?
2. How many flip flops are needed to count up to 999
3. How many flip flops are required to build an asynchronous counter to count 0 to 19
4. What is meant by the clock out of a counter?
Result :-
Designed and set up the following counters using JK flip flop
a. 4bit binary up counter(mod 16)
b. 4 bit binary down counter(mod 16)
c. 3 bit binary up-down counter
d. Decade counter

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Experiment No: 13
Date:

RING COUNTER AND JOHNSON COUNTER

Aim:-
To design and set up a 4- bit Ring counter and Johnson counter using flip flop.

Components and equipments required:-

ICs 7476

7474

7486

IC trainer kit

Theory:-
Shift counters give a specific set of counters. It is obtained by shifting a specific array of
binary inputs. Ring counter and Johnson counter are two important shift counters.

Ring counter:

Ring counter are basically shift registers. It is constructed using JK flip flops by
connecting Q and Q outputs from one flip flop to the J and K input of the next flip flop. The
outputs of the final flip flop are connected to the input of the first flip flop. To start the counter,
first flip flop is set using preset facility and the remaining flip flops are reset. When clock signal
arrives, this set condition continues to shift around the ring.

Johnson counters:

A ring counter can be converted to a Johnson counter by connecting Q and Q outputs of

the last flip flop to the J and K inputs of the first flip flop respectively. The mod number of the
counter is double of that of the ring counter. Johnson counter is also called twisted ring counter
or divide by 2N counter.

Ring counter using JKFF:

Clk Q0 Q1 Q2 Q3
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1

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Waveforms of Ring counter:

Johnson counter:

Clock Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

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Ring/Johnson counter using mode control:

Procedure :-
1. Set up the ring counter and set any Q output using PRESET and apply mono pulses
using de bouncer switch in the trainer kit to the clock input
2. Note down the states of the ring counter outputs on the truth table for successive
clocks.
3. Set up the Johnson counter. Clear all Q outputs by connecting clear pins to logic 0.
After clearing deactivate clear pins. Apply clock pluses and verify its operation.
4. Set up the ring/Johnson counter using mode control. Apply logic 0 to mode control M
and do set p no.1 and 2 to function as a ring counter.
5. Apply logic 1 to mode control pin and do set p no.3 to function as a Johnson counter.
Viva:-
1. Give an application of the ring counter.

Result:-
Designed and set up a 4- bit ring counter and Johnson counter using flip flops.

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Experiment No: 14
Date:

SYNCHRONOUS COUNTERS
Aim:-
To design and set up and verify the working of the following circuits using JK flip flops
1. 4 bit up counter
2. 4 bit down counter
3. 3 bit up/down counter
4. Self starting mod 5 counter
5. Self starting counter for a sequence of 0,2,4,5 repeatedly
Components and equipments required:-
ICs 7476 or 7473
7408
7400
7432
Theory :-
Synchronous counters asynchronous counters provide same outputs. The difference is
that in the synchronous counters all the flip flops work in synchronism with the input clock
pulse. That means, the output of all the flip flops in the counter change at the same instant.
Therefore, the propagation delay occurring in asynchronous counter is eliminated in
synchronous counters. Synchronous counters for any given count sequence or modulus can be
designed and set up the following procedure.
1. Find the number of flip flops using the relation M=2n where M is the
modulus of the counter and N is the minimum no. of flip flops required
.N=log2M
2. Write down the count sequence (FF out puts)in a tabular form.
3. Determine the flip flop inputs which must be present for the desired next
state using excitation table of flip flops.
4. Prepare Karnaugh maps for each flip flop input in terms of FF output as the
input variables obtain the minimized expressions from k-maps.
5. Set the circuit using flip flop and other gates.
Up/down counter
An up/down counter is capable of progressing the counting in either direction through a
certain sequence. An up/down counter can have any specified sequence of states. A mod control
pin is used to decide whether the counter should count up or down.

Self starting counters:

While the counting progresses, there is a chance of the counter falling to an unused or
undesired state. If it happens, the next state will be unknown to the counter and it

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might not progress as desired. To avoid this kind of lock out, a logic circuit designed to make
the counter start from the initial state if the counter falls to an undesired state. Refer to the truth
table. Counter has to count from 0 to 4.Precaution should be taken in the design so that if the
count happens to be an undesired one, next count is made 0 to reset the counter.

Design of 4- bit binary up counter:

Excitation table of JKFF Excitation table of TFF

Qn Qn+1 J K Qn Qn+1 Tn
0 0 0 * 0 0 0
0 1 1 * 0 1 1
1 0 * 1 1 0 1
1 1 * 0 1 1 0

Counter states JK FF input

Present state Next state
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 1 0 * 0 * 0 * 1 *
0 0 0 1 0 0 1 0 0 * 0 * 1 * * 1
0 0 1 0 0 0 1 1 0 * 0 * * 0 1 *
0 0 1 1 0 1 0 0 0 * 1 * * 1 * 1
0 1 0 0 0 1 0 1 0 * * 0 0 * 1 *
0 1 0 1 0 1 1 0 0 * * 0 1 * * 1
0 1 1 0 0 1 1 1 0 * * 0 * 0 1 *
0 1 1 1 1 0 0 0 1 * * 1 * 1 * 1
1 0 0 0 1 0 0 1 * 0 0 * 0 * 1 *
1 0 0 1 1 0 1 0 * 0 0 * 1 * * 1
1 0 1 0 1 0 1 1 * 0 0 * * 0 1 *
1 0 1 1 1 1 0 0 * 0 1 * * 1 * 1
1 1 0 0 1 1 0 1 * 0 * 0 0 * 1 *
1 1 0 1 1 1 1 0 * 0 * 0 1 * * 1
1 1 1 0 1 1 1 1 * 0 * 0 * 0 1 *
1 1 1 1 0 0 0 0 * 1 * 1 * 1 * 1

From the direct inspection J0=K0=1

Q3Q2 Q3Q2 Q3Q2

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
00 0 0 0 0 00 0 * * 0 00 0 0 * *
01 1 1 1 1 01 0 * * 0 01 0 0 * *
11 * * * * 11 1 * * 1 11 0 1 * *
10 * * * * 10 0 * * 0 10 0 0 * *

J1=Q0 J2=Q1Q0 J3=Q2Q1Q0

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Q3Q2 Q3Q2 Q3Q2

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
00 * * * * 00 * 0 0 * 00 * * 0 0
01 * * * * 01 * 0 0 * 01 * * 0 0
11 1 1 1 1 11 * 1 1 * 11 * * 1 0
10 0 0 0 0 10 * 0 0 * 10 * * 0 0

K1=Q0 K2=Q1Q0 K3=Q2Q1Q0

Circuit diagram for 4-bit binary up counter

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Design of 4- bit binary down counter:

Counter states JK FF input
Present state Next state
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
1 1 1 1 1 1 1 0 * 0 * 0 * 0 * 1
1 1 1 0 1 1 0 1 * 0 * 0 * 1 1 *
1 1 0 1 1 1 0 0 * 0 * 0 0 * * 1
1 1 0 0 1 0 1 1 * 0 * 1 1 * 1 *
1 0 1 1 1 0 1 0 * 0 0 * * 0 * 1
1 0 1 0 1 0 0 1 * 0 0 * * 1 1 *
1 0 0 1 1 0 0 0 * 0 0 * 0 * * 1
1 0 0 0 0 1 1 1 * 1 1 * 1 * 1 *
0 1 1 1 0 1 1 0 0 * * 0 * 0 * 1
0 1 1 0 0 1 0 1 0 * * 0 * 1 1 *
0 1 0 1 0 1 0 0 0 * * 0 0 * * 1
0 1 0 0 0 0 1 1 0 * * 1 1 * 1 *
0 0 1 1 0 0 1 0 0 * 0 * * 0 * 1
0 0 1 0 0 0 0 1 0 * 0 * * 1 1 *
0 0 0 1 0 0 0 0 0 * 0 * 0 * * 1
0 0 0 0 1 1 1 1 1 * 1 * 1 * 1 *
From direct inspection J0=K0=1

Q3Q2 Q3Q2 Q3Q2

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
00 1 1 1 1 00 1 * * 1 00 1 0 * *
01 0 0 0 0 01 0 * * 0 01 0 0 * *
11 * * * * 11 0 * * 0 11 0 0 * *
10 * * * * 10 0 * * 0 10 0 0 * *

J1=Q0 J2=Q1Q0 J3=Q2Q1Q0

Q3Q2 Q3Q2 Q3Q2

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
00 * * * * 00 * 1 1 * 00 * * 0 1
01 * * * * 01 * 0 0 * 01 * * 0 0
11 0 0 0 0 11 * 0 0 * 11 * * 0 0
10 1 1 1 1 10 * 0 0 * 10 * * 0 0

K1=Q0 K2=Q1Q0 K3=Q2Q1Q0

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Circuit diagram for 4-bit binary down counter

Design of 3- bit up/down counter

Counter states JK FF input
Present state Next state
Mode Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 * 0 * 1 *
0 0 0 1 0 1 0 0 * 1 * * 1
0 0 1 0 0 1 1 0 * * 0 1 *
0 0 1 1 1 0 0 1 * * 1 * 1
0 1 0 0 1 0 1 * 0 0 * 1 *
0 1 0 1 1 1 0 * 0 1 * * 1
0 1 1 0 1 1 1 * 0 * 0 1 *
0 1 1 1 0 0 0 * 1 * 1 * 1
1 1 1 1 1 1 0 * 0 * 0 * 1
1 1 1 0 1 0 1 * 0 * 1 1 * MQ2
1 1 0 1 1 0 0 * 0 0 * * 1 Q1Q0 00 01 11 10
1 1 0 0 0 1 1 * 1 1 * 1 * 00 0 0 1 1
1 0 1 1 0 1 0 0 * * 0 * 1 01 1 1 0 0
1 0 1 0 0 0 1 0 * * 1 1 * 11 * * * *
1 0 0 1 0 0 0 0 * 0 * * 1 10 * * * *
1 0 0 0 1 1 1 1 * 1 * 1 *
J1=MQ0+MQ0

MQ2 MQ2 MQ2

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10
00 * * * * 00 0 0 * 1 00 * 0 1 *
01 * * * * 01 0 * * 0 01 * 0 0 *
11 1 1 0 0 11 1 * * 0 11 * 1 0 *
10 0 0 1 1 10 0 * * 0 10 * 0 0 *

K1=MQ0+MQ0 J2=MQ1Q0+MQ1Q0 K2=MQ1Q0+MQ1Q0

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From direct inspection =J0=K0=1

Design of self Mode-5 up counter

Q2Q1
Counter states JK FF input Q0 00 01 11 10
Present state Next state 00 1 1 0 0
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 01 * * * *
0 0 0 0 0 1 0 * 0 * 1 * J0=Q2
0 0 1 0 1 0 0 * 1 * * 1
0 1 0 0 1 1 0 * * 0 1 * Q2Q1
0 1 1 1 0 0 1 * * 1 * 1 Q0 00 01 11 10
1 0 0 0 0 0 * 1 0 * 0 * 00 * * * *
1 0 1 0 0 0 * 1 0 * * 1 01 1 1 1 1
1 1 0 0 0 0 * 1 * 1 0 *
1 1 1 0 0 0 * 1 * 1 * * K0=1

Q2Q1 Q2Q1
Q0 00 01 11 10 Q0 00 01 11 10
00 0 * * 0 00 * 0 1 *
01 1 * * 0 01 * 1 1 *

J1=Q0Q2 K1=Q2+Q0

Q2Q1 Q2Q1
Q0 00 01 11 10 Q0 00 01 11 10
00 0 0 * * 00 * * 1 1
01 0 1 * * 01 * * 1 1

J2=Q0Q1 K2=1

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Circuit diagram for self starting mode-5 counter

Circuit diagram for self starting counter to count 0,2,4,5 repeatedly

Counter states JK FF input

Present state Next state Q2Q1
Q0 00 01 11 10
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
00 0 0 0 1
0 0 0 0 1 0 0 * 1 * 0 *
01 * * * *
0 0 1 1 0 0 1 * * 1 0 *
0 1 0 1 0 1 * 0 0 * 1 * J0=Q2Q1
0 1 1 0 0 0 * 1 0 * * 1
1 0 0 0 0 0 0 * 0 * * 1 Q2Q1
1 0 1 0 0 0 0 * * 1 * 1 Q0 00 01 11 10
1 1 0 0 0 0 * 1 * 1 0 * 00 * * * *
1 1 1 0 0 0 * 1 * 1 * 1 01 1 1 1 1

K0=1

Q2Q1 Q2Q1
Q0 00 01 11 10 Q0 00 01 11 10
00 1 * * 0 00 * 1 1 *
01 0 * * 0 01 * 1 1 *

J1=Q0Q2 K1=1

Q2Q1 Q2Q1
Q0 00 01 11 10 Q0 00 01 11 10
00 0 1 * * 00 * * 1 0
01 0 0 * * 01 * * 1 1

J2=Q0Q1 K2=Q1+Q0

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Procedure:-
1. Test all the components and IC packages using multimeter or digital ic tester.
2. Set up the circuit one by one and verify the counter states.
Viva:-
1. Differentiate between asynchronous counter and synchronous counter
2. Set up a sequence counter to generate a sequence 3, 4, 2, 2, 5….
Result:-
Designed and set up the following synchronous counters
1. 4 bit up counter
2. 4 bit down counter
3. 3 bit up/ down counter
4. Self starting mod 5 counter
5. Self starting counter to count 0,2,4,5 repeatedly.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING 61