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Static 0 Hazard and Dynamic Hazard: Digital Electronic Circuits

This document discusses static 0 hazard and dynamic hazard in digital circuits. Static 0 hazard occurs when the output should remain static at 0 according to Boolean logic, but a glitch occurs under certain input conditions. It can be detected using K-maps or by identifying adjacent zeros in the Boolean expression not covered by a common term. Static 0 hazard is removed by including additional sum terms to cover the adjacent zeros. Dynamic hazard occurs when multiple transitions are possible before reaching the final output value. It requires a circuit with three or more levels and specific input combinations. Dynamic hazard contains implicit static hazards that can be avoided by covering them.

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185 views

Static 0 Hazard and Dynamic Hazard: Digital Electronic Circuits

This document discusses static 0 hazard and dynamic hazard in digital circuits. Static 0 hazard occurs when the output should remain static at 0 according to Boolean logic, but a glitch occurs under certain input conditions. It can be detected using K-maps or by identifying adjacent zeros in the Boolean expression not covered by a common term. Static 0 hazard is removed by including additional sum terms to cover the adjacent zeros. Dynamic hazard occurs when multiple transitions are possible before reaching the final output value. It requires a circuit with three or more levels and specific input combinations. Dynamic hazard contains implicit static hazards that can be avoided by covering them.

Uploaded by

Hari Prasad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Electronic Circuits

Goutam Saha
Indian Institute of Technology Kharagpur

Static 0 Hazard and


Dynamic Hazard
Lecture 15
Concepts Covered:

 Static 0 Hazard

 Detection and Cover of Static 0 Hazard

 Dynamic Hazard
Static 0 Hazard

A.A’ = 0

Y = (A + C).(A’ + B)

B = 0, C = 0
Glitch
A:0→1
In Static 0 Hazard, output Glitch occurs
should remain static at 0
according to Boolean Logic
but glitch occurs under
certain input condition.
Detecting Static 0 Hazard
• Two logically adjacent cells with output 0 in K-Map not
covered by a common sum term.
• Boolean expression (A.A’) for certain condition.

Y = (A + C).(C + D’).(B + C’)


Glitch: Static 0 Hazard
ABCD : 0001→ 0011
1001→ 1011
Y = (A + B’).(B + C) Y = (B + C).(B’ + C’) 0000→ 0010
Glitch, ABC : 000 → 010 No Hazard for one
Static 0 Hazard variable changing
Static 0 Hazard and its Cover

Y = (A + C).(C + D’).(B + C’)


Y = (A + C).(A’ + B).(B + C) .(B + D’).(A + B)
Hazard-free circuit
(B + C) = 0 for B = 0, C = 0
This OR gate output when fed
Hazard-free by covering logically
to AND gate, suppresses glitch. adjacent 0s with common sum term
Hazard in NAND-NAND, NOR-NOR Circuit
1 0 Static 1 and Static 0
0 1
1 0 Hazards can be
1 0 avoided by adding
0
delay (controlled) in
1
0 the transition path.
1 1 0

Y = A’.C + A.B
Y = (A + C).(A’ + B)
B = 1, C = 1 Cover: (B.C)’ as Cover: (B + C)’
B = 0, C = 0
A:1→0 3rd input to as 3rd input to
A:0→1
Glitch occurs output NAND output NOR
Glitch occurs
Dynamic Hazard
• Potential for multiple transitions before settling to 0 1 0 1
final value while Boolean logic asks for only one
transition.
1 0 1 0
• One input variable is to have three or more paths to
the output.
• No. of levels three or more.
• For specific combination of input variables, Boolean
expression reduces to (A + A’).A or A + A’.A
Dynamic Hazard: Example
Y = (A.C + B.C’).(CD)’

To prevent, cover implicit Static 1.


Y = (A.C + B.C’ + A.B).(CD)’
Convert to 2-level circuit
and cover Hazard, if any.
References:
 Donald P. Leach, Albert P. Malvino, and Goutam Saha, Digital Principles &
Applications 8e, McGraw Hill
Conclusion:
• In Static 0 Hazard, output should remain static at 0
but glitch occurs for certain input combination.
• Static 0 hazard can be detected by examining the K-
Map or Boolean expression.
• Static 0 hazard can be avoided by including additional
sum terms.
• Static 0 and Static 1 Hazards can be removed by
adding appropriate delay.
• In Dynamic Hazard, potential for multiple transitions
exist while the logic relation asks for one.
• Dynamic Hazard requires 3 or more level circuit.
• Dynamic hazard has implicit Static 1, Static 0 hazard
which if covered, can avoid its occurrence.

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