International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015

ISSN: 2395-3470
www.ijseas.com

Design & Implementation of Advance Peripheral Bus Protocol

Heli Shah1 , Chinmay Modi2, Bhargav Tarpara3
P PR RP P P P P P

1, 2,
P M.Tech. VLSI, U.V.Patel College of Engineering and Technology, Kherva, Mehsana, India
P 0T 0T

3
P Verification Technical Assistant, eiTRA, Ahmedabad, India
P

Abstract- This design presents an intellectual Interface (AXI), (4) AMBA Advanced Extensible
property (IP) for inter-Advanced peripheral Interface Lite (AXI4-Lite).
bus (APB) protocol. The current VLSI design APB Revisions are (1) AMBA 2 APB
scenario is characterized by high performance, Specification (2) AMBA 3 APB Protocol
complex functionality and short time-to Specification v1.0, (3) AMBA APB Protocol
market. A reuse based methodology for SoC Specification v2.0. [1]
design has become essential in order to meet
these challenges. The work involved is of APB The AMBA 3 APB Protocol Specification v1.0
Protocol and its slave Verification. The idea defines the following additional functionality:
behind this is to test DUT. Propose model is • Wait states.
used for communication between master and • Error reporting.
slave. The entire design has been coded in These are PREADY is a ready signal to indicate
Verilog & verified using Spartan kit. completion of an APB transfer. PSLVERR an
Index Terms— Intellectual property (IP), error signal to indicate the failure of a transfer.
Advanced microcontroller bus architecture II. AMBA BUS
(AMBA), Advanced peripheral bus (APB), Field- 16T

programmable gate array (FPGA), Verilog. The AMBA specification are:

• This is development of embedded
16T

Protocol, Data, Advanced high performance bus

(AHB), Advanced system bus (ASB). microcontroller products with one or more
CPUs or signal processors.
I. INTRODUCTION • This is highly reusable peripheral
The Advanced Peripheral Bus (APB) is part of appropriate for full-custom, standard cell
the Advanced Microcontroller Bus Architecture and gate array technologies.
(AMBA) protocol family. It defines a low-cost • It provides a road-map for advanced
interface that is optimized for minimal power cached CPU cores and the development of
consumption and reduced interface complexity. peripheral libraries to minimize the silicon
The APB protocol is not pipelined, use it to infrastructure required to support efficient
connect to low-bandwidth peripherals that do not on-chip.
require the high performance of the AXI protocol. An AMBA is having backbone bus AMBA AHB
It relates a signal transition to the rising edge of or AMBA ASB. It sustains external memory
the clock, to simplify the integration of APB bandwidth, on which the CPU, on-chip memory
peripherals into any design flow. Every transfer and other Direct Memory Access (DMA) devices
takes at least two cycles. abide. This bus provides a high-bandwidth
The APB can interface with: (1) AMBA interface between the elements that are involved
Advanced High-performance Bus (AHB), (2) in the majority of transfers. Also it is a bridge to
AMBA Advanced High-performance Bus Lite the lower bandwidth APB. [1]
(AHB-Lite), (3) AMBA Advanced Extensible

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

AMBA APB provides the basic peripheral macro in the design of high performance 16 and 32-bit
cell communications infrastructure as a secondary embedded microcontrollers. It supports the
bus from the higher bandwidth pipelined main efficient connection of processors, on-chip
system bus. It consist of interfaces which are memories and off chip external memory
memory-mapped registers. interfaces with low-power peripheral macro cell
functions. The bus also provides the test
infrastructure for modular macro cell test and
diagnostic access. [1]

C. AHB VS APB
AHB stands for Advanced High-performance Bus
and APB sands for Advanced Peripheral Bus.
Both the Advanced High-performance Bus and
the Advanced Peripheral Bus are part of the
Advanced Microprocessor Bus Architecture
(AMBA). Though both the AHB and the APB
belong to AMBA, they differ in many way.

Difference between the two, the AHB uses a full

Figure 1 AMBA Bus Architecture [1]
duplex parallel communication whereas the APB
uses massive memory-I/O accesses. Both the
No high-bandwidth interfaces. It has been AHB and the APB are on chip Bus standards. The
accessed under programmed control. The external Advanced High-performance Bus is capable of
memory interface is application-specific and may waits, errors and bursts. The ADH, which is
only have a narrow data path, but may also pipelined, mainly connects to memories.
support a test access mode which allows the
internal AMBA AHB, ASB and APB modules to When comparing the usage, the APB is simpler
be tested in isolation with system independent than the AHB. Unlike the AHB, there is no
test sets.[1] pipelining in APB. The APB is mainly proposed
for connecting to simple peripherals. Looking at
A. AMBA AHB the AHB and the APB, it can be seen that the
Advanced High performance bus (AHB) is made APB comes with a low power peripheral.
for address the requirements of high-performance
synthesizable designs. AMBA AHB is a new It can also be seen that Advanced Peripheral Bus
level of bus for the APB and implements the is sometimes optimized for reduced interface
features high clock frequency systems including: complexity and minimal power consumption for
• burst transfers supporting peripheral functions. This Bus can
• split transactions also be used in union with either version of the
• Single cycle bus master handover system bus.
• Single clock edge operation
• Wider data bus configurations (64/128 bits). When looking at the features of AHB, it has a
single edge clock protocol, several bus masters,
B. AMBA ASB split transactions, single-cycle bus master
The Advanced System Bus (ASB) specification handover, burst transfers, large bus widths.
defines a high-performance bus that can be used

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

In AHB, the transaction consists of an address PWRITE Access when HIGH.

phase and a data phase. In case of AHB, there is PWDATA 32 bits. Write data .PWRITE is
only one Bus master at a time. HIGH.
When compared to Advanced High-performance PREADY Ready. To extend an APB
Bus, the Advanced Peripheral Bus is only used transfer.
for low bandwidth control accesses. Though the PRDATA 32 bits. Read data. PWRITE is
APB has an address phase and data phase as like LOW.
that of the AHB, it comes with a list of low PSLAVERR Slave error. This signal indicates
complexity signal. [4] a transfer failure,

A. Operating states of APB

IDLE is the normal state of the APB. When a
III APB BLOCK DIAGRAM transfer is necessary the bus relocates into the
SETUP state, where the suitable select signal,
PSELx, is asserted.

Figure 2 Interfacing of APB Master & Slave [2]

Table 1. List of APB signals [2][3]

Figure 3 State diagram [2][3]
Signal Signal Description
PCLK Clock. The rising edge of PCLK The bus only waits in the SETUP state for one
times all transfers on the APB. clock cycle and always moves to the ACCESS
PRESET System bus equivalent Reset. The state on the next rising edge of the clock.
APB reset signal is active LOW. ACCESS will enable signal, PENABLE, is
PADDR 32 bit. address bus asserted in the ACCESS state. The write, write
PSEL The slave device is selected and data signals, select, and address must remain
that a data transfer is required. stable during the transition from the SETUP to
PENABLE Enable. This signal indicates the ACCESS state. ACCESS state is controls when to
second and subsequent cycles of exit by the PREADY signal from the slave.
an APB transfer. These are the conditions one is if PREADY is

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

held LOW by the slave then the peripheral bus phase. The slave must provide the data before the
remains in the ACCESS state another is end of the read transfer.[2][3]
PREADY is driven HIGH by the slave then the
ACCESS state is exited and the bus returns to the
IDLE state if no more transfers are required after
that it will start the same cycle. [2][3]

B. Write cycle
At T1, a write transfer starts with PADDR,
PWDATA, PWRITE, and PSEL, being registered
at the rising edge of PCLK. It is called the
SETUP cycle. At the next rising edge of the clock
T2 it is called ACCESS cycle, PENABLE, and
PREADY, are registered. When asserted,
PENABLE indicates starting of Access phase of Figure 5 Read cycle
the transfer. When asserted, PREADY indicates
that the slave can complete the transfer at the next IV.SIMULATION RESULTS FOR DESIGN
rising edge of PCLK. The PADDR, PWDATA,
and control signals all remain valid until the Whenever clock signal goes high from an
transfer completes at T3, the end of the Access operator at that instance PENABLE and
phase .The PENABLE, is disabled at the end of PREADY goes high PADDR which is of 32-bit
the transfer. The select signal PSEL is also in length. After enabling PADDR it will take data
disabled unless the transfer is to be followed and write it on PWDATA and which is also
immediately by another transfer to the same transferred to the apb_write_data which all are 32
peripheral.[2][3] –bit in size

Figure 4 Write cycle

C. Read cycle Figure 6 Simulation result of write cycle

During read operation the PENABLE, PSEL,
PADDR PWRITE, signals are asserted at the
clock edge T1 (SETUP cycle). At the clock edge
T2, (ACCESS cycle), the PENABLE, PREADY
are asserted and PRDATA is also read during this

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

same as the data written to the given memory

location. Hence, the design is functionally
correct. Xilinx also ensures the functional
correctness of the design.

The electronic system level model of the same

design will be created in the future since ESL is
the requirement of the future because of
increasing design complexity. The results
Figure 7 Simulation result of Read cycle obtained after the simulation will be compared
with the results.
After transfereing the data on the adress and after
ready toggle once with penable after this VI. MOTIVATIONAL WORK
operation apb_read goes high and its reads the
data from the apb_write _data and put it on Here we have designed Advanced Peripheral Bus
apb_read_data. as a single slave but as we know APB is a
multiple slave interface so we can design that
accordingly.
V. CONCLUSION
This paper gives an outline of the AMBA bus
architecture and explain the APB bus in detail.
The APB bus is designed using the Verilog HDL
according to the specification and is verified
using Xilinx. The simulation results show that the
data read from a particular memory location is
So After completion of this, we can move to
physical design for IC fabrication for the same.

VII. REFRENCES

[1]URL:http://wwwmicro.deis.unibo.it/~magagni/
amba99.pdf
[2]ARM, “AMBA Specification Overview”,
available at http://www.arm.com/.
[3] ARM, “AMBA Specification (Rev 2.0)”,
available at http://www.arm.com.
[4]URL:http://www.differencebetween.net/techno
logy/difference-between-ahb-and-apb
[5] Samir Palnitkar, “Verilog HDL: A guide to
Digital Design and Synthesis (2nd Edition),
Pearson, 2008.
[6] URL:http://www.testbench.com.

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