American Journal of Engineering Research (AJER) 2015

American Journal of Engineering Research (AJER)

e-ISSN: 2320-0847 p-ISSN : 2320-0936
Volume-4, Issue-10, pp-86-91
www.ajer.org
Research Paper Open Access

CMOS BASED CURRENT FEEDBACK OP-AMP WITH

IMPROVED BANDWIDTH

Akshay Dubey
Research Scholar, Electronics Engineering department,
Institute of Engineering and Technology, Lucknow, India.

ABSTRACT : A current mode feedback operational amplifier designed using a complimentary MOS circuit
technology has been discussed in this paper. A class AB amplifier has been used in the design and the design
results in improvement of values of number of parameter when compared to the previously reported
architecture. The circuit is designed using 0.35µm technology. Bandwidth of the presented architecture was
obtained, that was always greater than 50MHz. On the other hand , bandwidth in case of previously reported
circuit was coming out to be always more than 2MHz. Thus in our proposed circuit, there is a considerable
improvement in the bandwidth of the circuit. Also the Slew rate, which was improved from 5.2V/µsec to 8.1V/
µsec. Settling time of the proposed circuit has been reduced to 134 nsec which was of order of 212 nsec in case
of the previous design.

Keywords - Amplifiers, CMOS, current-feedback operational amplifiers (CFOAs),Slew Rate.

I. INTRODUCTION
An operational amplifier (op amp) is a device whose output is the multiplication of its internal gain and
the differential voltage applied to its input terminals. It was initially used for analog computation and
instrumentation. It wasn't until the mid 1960's and the invention of the integrated circuit (IC) that the op amp's
full versatility was realized.
Earlier, an ideal op amp has been classified as a differential input, single ended output amplifier with
infinite gain, infinite input resistance, and zero output resistance. But after the invention of the first IC,
manufacturers of op amps have almost got very closer to approximate these characteristics of an ideal op amp.
There are continuous researches going all over the globe to find the ways to increase the input impedance, lower
the output impedance, offset currents and voltages and noise. Simultaneously, researchers have been trying to
push the bandwidths of the devices higher, and lower the settling-time characteristics. These characteristics are
very important, specially in applications such as high speed digital to analog conversion (DAC) buffers, sample
and hold (S-H) circuits, switching applications and video and IF drivers.
In spite of all electronic systems prominently being dominated by digital circuits and systems, the
analog circuits have neither become obsolete nor avoidable. In fact, analog circuits and techniques continue to
be indispensable and unavoidable in many areas since all real life signals are analog in nature [8]. Also many
basic functions such as amplification, rectification, continuous time filtering, analog to digital conversion and
digital to analog conversion etc. need analog circuits and techniques. Therefore analog circuits act as a bridge
between the real world and digital systems. Current feedback operational amplifiers (CFOAs) are the modified
version of conventional voltage op-amps and are used in number of applications [1]–[4] for their inherent
advantages over conventional op-amps, which are generally expressed in terms of high-speed properties [5], [6].
Also, the (inverting) closed-loop bandwidth of operational amplifier have becomes independent of the closed
loop gain, provided, the feedback resistance is kept constant. Besides, the input (output) stage of current
feedback op-amp are the voltage buffer that can be easily implemented through class-AB topologies. This
enable us achieving a reasonably high slew rate values.
In this paper, we will discuss the implementation of two CFOA architectures. The former was
originally proposed by one of the authors in [7], is based on a low-voltage alternative and is modified version of
the architecture that was presented in [8] which was based on a well-known class AB differential amplifier stage

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with high drive capability. The class AB differential amplifiers are here utilized in unity feedback, and thus
allowing us to achieve high slew rate and relatively low input and output resistances. This property also enables
a large variation of the closed-loop gain, while maintaining constant the bandwidth. Both the circuit topologies
are described in Sections 2 and 3, respectively. Simulations and experimental measurements are given in Section
4. Conclusions are summarized in Section 5.

II. EXISTING ARCHITECTURE

In the architecture presented in [8], the problem of high voltage requirement have been solved by adopting a
class-AB unity-gain buffer ,and thus the new architecture require low-voltage supply. The resulting simplified
schematic of the low-voltage CFOA is depicted in Fig. 1. M1-M13 form the first unity-gain closed-loop voltage
buffer. The input current at the inverting terminal is conveyed to the high impedance node at the drain of M22-
M23. Transistors M1b-M13b implement the output buffer. The minimum supply voltage is now reduced to V GS
+ 3VDS, SAT (path formed by M9b-M1b-M23-M24) and the maximum input swing is VGS + 3VDS, SAT from VDD –
VSS – VGS - 2VDS, SAT that was derived in [8].

Figure 1. Existing Architecture.

III. PROPOSED ARCHITECTURE WITH IMPROVED BANDWIDTH.

In the circuit presented in fig 3, M1-M13 form the first unity-gain closed-loop voltage buffer. The input current
at the inverting terminal is conveyed to the high impedance node at the drain of M22-M23. Transistors M1b-
M13b implement the output buffer. In the circuit shown in fig 1, the transistor such as M14, M14b,M11, M22
and M23 is intended to provide stability to the circuit and they are not performing any such special function.
Since all the MOS are operating in saturation region and if we are in a position to sacrifice the stability of the
circuit to some extent, in order to achieve some fruitful results such as improvement in various parameter, then
we can propose a circuit that is shown in fig 3.
In the proposed circuit shown in fig 3, MOSFET M11, M14, M14b, M22 and M23 has been removed and the
resultant circuit results were studied on a Tanner EDA tool. By doing so, we have achieved improvement in the
verious parameter.
Dominant-pole frequency compensation is obtained through capacitor CCwhereas resistor RC introduces, as
usual, a negativezero.The input resistance,(at the inverting input terminal) and the output resistanceare
expressed by:
 1 1
r in  || (1)
g m4 g m8

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American Journal of Engineering Research (AJER) 2015
1 1
r out  || (2)
g m 4b g m 8b

The gain bandwidth product is given by:

1 (3)
 GBW 
r in

 rout C C 

Figure 2. Proposed Architecture.

Figure 3. CFOA in inverting configuration.

III. PERFORMANCE COMPARATIVE ANALYSIS OF FIGURES AND TABLES

The proposed architecture shown in figure 2 has number of distinguished features. The number of MOS
transistors has been reduced and thus the architecture become much simplified. The aspect ratio of the various
transistors used in the proposed architecture has been summarized below in Table I.

TABLE I :TRANSISTOR ASPECT RATIO OF FIGURE 1

TRANSISTOR W/L
M1-M4, M1b-M4b 180/0.6
M9-M10,M21,M9b-M10b 40/1
M11b 80/1
M12-M13,M24,M12b 130/1
M13b 260/1

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III A. SIMULATION
The two proposed solutions have been designed using the 0.35µm technology and the results are verified using
tanner EDA tool version 14.11.Bandwidth of the modified architecture shown in fig 3.was obtained around
63MHz and 70 MHz for value of the feedback resistor of 3KΩ and 9KΩ respectively. On the other hand ,
bandwidth in case of base circuit shown in fig 3.2 was coming out to be always more than 2MHz.Thus in our
proposed circuit, it can be said that there is a considerable improvement in the bandwidth of the circuit and the
bandwidth is always found to be greater than 50MHz. Also, improvement in slew rates and setting time have
been reduced. Slew rates was coming out to be 8.1V/ µsec, which is more than the slew rate obtained for circuit
shown in Fig 1. Transistor dimensions of both circuits are summarized in Tables I and II, respectively. The two
circuits are here dimensioned for off-chip applications and to account for a larger capacitive load of 20 pF. Also
the power supply in both cases are kept equal to 2V. Total harmonic distortion of the modified architecture was
found to be almost same as that of the base architecture, but, the number of the MOS used has also been reduced
thus the complexity of the circuit had been improved.

TABLE II :COMPARISON OF PERFORMANCE OF THE EXISTING AND PROPOSED CIRCUITS.

PARAMETER FIG 1. FIG 3.

Bandwidth >2MHz >50MHz

Slew rate 5.2 V/us 8.1 V/us

Offset voltage 4.1 mV 6.7 mV

Settling time 212 ns 134 ns

Technology 350nm 350nm

Supply voltage 2V 2V

Load capacitance 20pF 20pF

THD -76.8 dB -75.5 dB

Impedence 577 Ω 1.4 KΩ

III B. EXPERIMENTAL RESULTS

Figure 3. Gain vs Frequency characteristics of proposed circuit.

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American Journal of Engineering Research (AJER) 2015

Figure 4. Response of CFOA with improved bandwidth, operating in inverting mode for different value
of feedback resistor.

Figure 3. output voltage and slew rate characteristics of proposed circuit.

IV. CONCLUSION

CMOS based current-feedback operational amplifiers with improved bandwidth proposed here. It was obtained
from two class AB voltage buffer configurations exploiting local feedback and providing low output resistance
and both high current drive and slew-rate capability. Number of improvements in various parameter have been
observed and the circuit has also been simplified. Comparison of the proposed circuit with the previous one has
been summarized in tabular form. Design examples using a 0.35-µm process were presented and simulations
along with experimental results, confirming the effectiveness of the solutions are also provided. The proposed
architecture gives high value of offset voltage. Also, circuit is not as stable as its previous counterpart.

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Appendix

.The proposed circuit design has been investing the parameters such as bandwidth, slew rate and
settling time with the CAD EDA tool. The netlist created and simulate the following extracted
parameters such as bandwidth >50MHz, slew rate 8.1V/µsec and settling time 134 nsec. The
theoretical description of these parameters are described below.

(I) BANDWIDTH

Bandwidth can be defined as a measure of the width of a range of frequencies. It is measured in hertz. It is also
defined as the difference between the upper and lower frequencies in a continuous set of frequencies.
If fH and fL are the high cutoff and low cutoff frequency respectively, then bandwidth can be given by
expression:
Bandwidth(B.W) = fH - fL (5)

(II) SLEW RATE

Slew rate is defined as the maximum rate of change of output voltage per unit of time and is expressed as volts
per second. Limitations in slew rate capability can give rise to non linear effects in electronic amplifiers.
Expression for slew rate is given by:
max (6)

(III) SETTLING TIME

The settling time of an amplifier is defined as the time it takes the output to respond to a step change of input
and come into, and remain within a defined error band, as measured relative to the 50% point of the input pulse.
Expression for settling time is given by:
Ts = 4/ζωn (7)

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