A PROJECT ON

A NEW APPROACH TO MINIMIZE LEAKAGE POWER IN

MASTER OF TECHNOLOGY
In
VLSI

Submitted By
L.S.R.TEJ.PUPPALA
(1221209111)

Under The Esteemed Guidance of

Mrs. G. Radha Rani, M.E.

Associate Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Signature of Project Coordinator

HOD E.C.E Department

Signature of Project Guide

Mrs. G. Radha Rani, M.E.

Associate professor
 ABSTRACT

Power consumption is one of the top concerns of VLSI circuit design, for which CMOS is the
primary technology. Power consumption of CMOS consists of dynamic and static components.
Dynamic power is consumed when transistors are switching and static power (leakage power) is
consumed regardless of transistor switching. Dynamic power consumption was previously (at
0.18um technology and above) the single largest concern for low-power chip designers since
dynamic power accounted for 90% or more of the total chip power. Therefore, many previously
proposed techniques, such as voltage and frequency scaling, focused on dynamic power
reduction. However, as the feature size shrinks, e.g., to 0.09 and 0.065 m, static power has
become a great challenge for current and future technologies. International Technology Roadmap
for Semiconductors (ITRS) projects that leakage power consumption may come to dominate total
chip power consumption as the technology feature size shrinks. So, Leakage is a serious problem
particularly for CMOS circuits in nano scale technology.

In this project I have implemented a novel ultra-low leakage CMOS circuit structure named
“sleepy keeper.” which reduces leakage current while saving exact logic state. This project
report first introduces previous approaches to reduce leakage power consumption and then
explains the methodology and findings regarding the sleepy keeper approach. The scope of this
report includes test procedures with schematics and layouts for all considered approaches as well
as test results such as data on delay plus dynamic and static power. The sleepy keeper results are
compared with the previous approaches. Based on experiments with a 4-bit adder circuit, sleepy
keeper approach achieves up to 49% less delay and 49%less area than the sleepy stack approach.

Here a review of previously proposed circuit level approaches for sub threshold leakage power
reduction is presented:-

The first approach and most well-known traditional approach is the “sleep approach”. In this
approach sleep transistors turn off the circuit by cutting off the power rails. By cutting off the
power source, this technique can reduce leakage power effectively. However, output will be
floating after sleep mode, so the technique results in destruction of state plus a floating output
voltage.

The second approach a variation of the sleep approach, the “zigzag approach”, reduces wake-up
overhead caused by sleep transistors by placement of alternating sleep transistors. Thus, this
approach uses fewer sleep transistors than the original sleep approach. But, this approach still
results in destruction of state (i.e., state is set to the particular pre-selected input vector), but the
problem of floating output voltage is eliminated.

The third approach for leakage power reduction is the “stack approach”, which forces a stack
effect by breaking down an existing transistor into two half size transistors. When the two
transistors are turned off together, induced reverse bias between the two transistors results in sub
threshold leakage current reduction. However, divided transistors increase delay significantly
and could limit the usefulness of the approach.
The fourth approach “the leakage feedback approach” is based on the sleep approach. This
approach uses two additional transistors to maintain logic state during sleep mode (i.e. state
saving) and the two transistors are driven by the output of an inverter which is driven by output
of the circuit implemented utilizing leakage feedback. But it results is leakage in inverter and
area penalty.

The fifth approach “the sleepy stack approach” which combines the sleep and stack
approaches. This technique divides existing transistors into two half size transistors like the stack
approach. Then sleep transistors are added in parallel to one of the divided transistors during
sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while
saving state. Each sleep transistor, placed in parallel to the one of the stacked transistors, reduces
resistance of the path, so delay is decreased during active mode. However, area penalty is a
significant matter for this approach since every transistor is replaced by three transistors.

Finally, the new leakage reduction technique, named as the “sleepy keeper” approach. The
structure of the circuits based on sleepy keeper approach consists of sleep transistors and two
additional transistors (keeper transistors) driven by output (NMOS to Pull-up Network, PMOS to
Pull-down Network) for state saving. The advantages of this approach are Ultra low leakage with
dual Vth, State-saving, less area penalty and faster than sleepy stack approach.

For the sleep, zigzag, sleepy stack and leakage feedback approach and sleepy keeper dual Vth
technology can be applied to obtain greater leakage power reduction.

In order to compare the results of our new approach with prior leakage reduction approaches,
experiments include all the techniques discussed above namely, stack, sleep , zigzag, sleepy
stack and leakage feedback approaches. In addition, we consider a base case and the newly
proposed sleepy keeper approach. A 4-bit adder is chosen to compare the sleepy keeper approach
to the other considered approaches. 4 bit adder Schematics are created based on Berkeley 0.18
μm, 0.13μm, 09μm, 0.65μm, 0.45μm process parameters. Netlists of test circuits for different
techniques are extracted from the schematics and then the comparison of different techniques is
done based on parameters: propagation delay, static power, dynamic power, area.

TOOLS TO BE USED:
1. Synopsys HSPICE to estimate delay and power consumption.
2. TANNER LAYOUT edit for layout extraction.