16 bit adder by cascading of 8 bit KSA and ripple carry adder

Aim: To design and simulate a 16-bit adder by cascading of 8-bit KSA and ripple carry adder using structural m
Verilog.

Tool used: XILINX VIVADO 2017.4.

Theory: For a 16- bit adder we are using two different adders. One is 8-bit kogge stone adder and other one is a 8-
bit ripple carry adder and by cascading of these two adders a 16-bit adder is modeled. In ripple carry adder we are
giving a input carry and 2 16-bit numbers a (8-bit a0 to a7) and b (8-bit b0 to b7) and resultant is sum s (s0 to s7)
and output carry. Output carry of ripple carry adder is given to kogge stone adder as input carry and other 8 bits
of a and b (a8 to a15 and b8 to b15) as two numbers for addition and resultant is sum (s8 to s15) and carry out.
Carry out of kogge stone adder is the final output carry and sum as s(s0 to s15).

Verilog code:

module adder16bit( module kogge_stone (x, y, sum, cin, cout);

input [15:0] a,b, input [7:0] x, y; output [7:0] sum;
input Cin, input cin; output cout;
output [15:0] s, wire [7:0] G_Z, P_Z, G_A, P_A,G_B, P_B,G_C, P_C;
output Cout ); //level 1
wire w1; GC level_0A(cin, P_Z[0], G_Z[0], G_A[0]);
ripple_carry_8_bit R1(a[7:0],b[7:0],Cin,s[7:0],w1); BC level_1A(G_Z[0], P_Z[1], G_Z[1], P_Z[0], G_A[1], P_A[1]);
kogge_stone K1(a[15:8],b[15:8],s[15:8],w1,Cout); BC level_2A(G_Z[1], P_Z[2], G_Z[2], P_Z[1], G_A[2], P_A[2]);
endmodule BC level_3A(G_Z[2], P_Z[3], G_Z[3], P_Z[2], G_A[3], P_A[3]);
BC level_4A(G_Z[3], P_Z[4], G_Z[4], P_Z[3], G_A[4], P_A[4]);
module ripple_carry_8_bit( BC level_5A(G_Z[4], P_Z[5], G_Z[5], P_Z[4], G_A[5], P_A[5]);
input [7:0] a,b, BC level_6A(G_Z[5], P_Z[6], G_Z[6], P_Z[5], G_A[6], P_A[6]);
input Cin, BC level_7A(G_Z[6], P_Z[7], G_Z[7], P_Z[6], G_A[7], P_A[7]);
output [7:0] s, //level 2
output Cout ); GC level_1B(cin, P_A[1], G_A[1], G_B[1]);
wire w1,w2,w3,w4,w5,w6,w7; GC level_2B(G_A[0], P_A[2], G_A[2], G_B[2]);
fulladder F1(a[0],b[0],Cin,s[0],w1); BC level_3B(G_A[1], P_A[3], G_A[3], P_A[1], G_B[3], P_B[3]);
fulladder F2(a[1],b[1],w1,s[1],w2); BC level_4B(G_A[2], P_A[4], G_A[4], P_A[2], G_B[4], P_B[4]);
fulladder F3(a[2],b[2],w2,s[2],w3); BC level_5B(G_A[3], P_A[5], G_A[5], P_A[3], G_B[5], P_B[5])
fulladder F4(a[3],b[3],w3,s[3],w4); BC level_6B(G_A[4], P_A[6], G_A[6], P_A[4], G_B[6], P_B[6]);
fulladder F5(a[4],b[4],w4,s[4],w5); BC level_7B(G_A[5], P_A[7], G_A[7], P_A[5], G_B[7], P_B[7]);
fulladder F6(a[5],b[5],w5,s[5],w6); //level 3
fulladder F7(a[6],b[6],w6,s[6],w7); GC level_3C(cin, P_B[3], G_B[3], G_C[3]);
fulladder F8(a[7],b[7],w7,s[7],Cout); GC level_4C(G_A[0], P_B[4], G_B[4], G_C[4]);
endmodule GC level_5C(G_B[1], P_B[5], G_B[5], G_C[5]);
GC level_6C(G_B[2], P_B[6], G_B[6], G_C[6]);
module fulladder(a,b,c_in,sum,c_out); BC level_7C(G_B[3], P_B[7], G_B[7], P_B[3], G_C[7], P_C[7]);
input a,b,c_in; GC level_7D(cin, P_C[7], G_C[7], cout);
output sum,c_out; //xor with and
wire w1,w2,w3; and_xor level_Z0(x[0], y[0], P_Z[0], G_Z[0]);
xor(w1,a,b); and_xor level_Z1(x[1], y[1], P_Z[1], G_Z[1]);
and(w2,a,b); and_xor level_Z2(x[2], y[2], P_Z[2], G_Z[2]);
xor(sum,w1,c_in); and_xor level_Z3(x[3], y[3], P_Z[3], G_Z[3]);
and(w3,w1,c_in); and_xor level_Z4(x[4], y[4], P_Z[4], G_Z[4]);
or(c_out,w3,w2); and_xor level_Z5(x[5], y[5], P_Z[5], G_Z[5]);
endmodule and_xor level_Z6(x[6], y[6], P_Z[6], G_Z[6]);
and_xor level_Z7(x[7], y[7], P_Z[7], G_Z[7]);
 //outputs
xor(sum[0], cin, P_Z[0]); //Verilog code for XOR block:
xor(sum[1], G_A[0], P_Z[1]); module and_xor(a, b, p, g);
xor(sum[2], G_B[1], P_Z[2]); input a, b;
xor(sum[3], G_B[2], P_Z[3]); output p, g;
xor(sum[4], G_C[3], P_Z[4]); xor(p, a, b);
xor(sum[5], G_C[4], P_Z[5]); and(g, a, b);
xor(sum[6], G_C[5], P_Z[6]); endmodule
xor(sum[7], G_C[6], P_Z[7]);
endmodule
//Verilog code for grey cell : Test bench code;
module GC(Gkj, Pik, Gik, G);
input Gkj, Pik, Gik; module adder16bit_Test( );
output G; reg [15:0] a,b;
wire Y; reg Cin;
and(Y, Gkj, Pik); wire [15:0] s;
or(G, Y, Gik); wire Cout;
endmodule adder16bit uut (.a(a),.b(b),.Cin(Cin),.s(s),.Cout(Cout));
initial begin
//Verilog code for black cell : Cin=1'b0; a=16'b0011110100110110; b=16'b10001100010011
module BC(Gkj, Pik, Gik, Pkj, G, P); #10 a=16'b1001101010110010; b=16'b0011110001101010;
input Gkj, Pik, Gik, Pkj; #10 Cin=1'b1; a=16'b1101010101110011; b=16'b1100101110001
output G, P; #10 a=16'b1111110000001111; b=16'b1000001111001110;
wire Y; #10 $finish;
and(Y, Gkj, Pik); end
or(G, Gik, Y); endmodule
and(P, Pkj, Pik);
endmodule

Simulation results:
Conclusion: 16-bit adder has been designed using structural verilog model and tested by testbench and observed
by simulation and schematic results. Its satisfies the functionality of 16-bit adder.