ELEMENTS OF PHYSICAL

DESIGN
Dr. Mohammed M. Farag
fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 2

fAcUlty of engineering - AlexAndriA University 2013

Physical Design
 What is physical design?
 To translating logic circuits into silicon
 Switch speed is critical
 The electrical characteristics of a logic gate depend on the aspect
ratios of the transistors (In Chapter 6, we will discuss it)
 In other words, this is due to both the current flow levels and the
parasitic resistance and capacitance (In Chapter 3)
 Layout can be very time consuming
 Design gates to fit together nicely
 Build a library of standard cells
 Standard cell design methodology
 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top Figure 5.1 Polygons in
physical design
 All gates include well and substrate contacts
EE 432 VLSI Modeling and Design 3
fAcUlty of engineering - AlexAndriA University 2013

Example: N-Well COMS Inverter

The cross-section view and layout

of a CMOS(n-well) inverter

EE 432 VLSI Modeling and Design 4

 fAcUlty of engineering - AlexAndriA University 2013
Minimum NIMP extension Minimum N-Well width 1.7
of N+ Diffusion 0.25 um um

Minimum POLY1 extension Minimum Metal1 extension

of Diffusion 0.4 um of Contact 0.15 um

Minimum Contact to Contact size 0.4 * 0.4 um

Contact spacing 0.4 um

Minimum Diffusion Minimum N-Well extension

extension of Contact is 0.15 of P+ Diffusion 1.2 um
um

Minimum Metal1 width 0.5

um

Minimum clearance from

Contact on Diffusion region
to a Poly gate 0.3 um Minimum Diffusion width
0.3 um

Minimum PIMP extension

Minimum Poly1 width 0.35 of P+ Diffusion 0.25 um
um

EE 432 VLSI Modeling and Design 5

fAcUlty of engineering - AlexAndriA University 2013

Basic Concepts
 Our study to this point shows that the topology of
the transistor network establishes the logic function
 Another aspect of logic is switching speed which is
crucially important to modern chip design
 The electrical characteristics of a logic gate depends
on the transistor aspect ratios (W/L)
 Physical design must address both of theses areas
 We will focus on studying the basics of circuit layout
in this chapter

EE 432 VLSI Modeling and Design 6

fAcUlty of engineering - AlexAndriA University 2013

Layout CAD Tools

 Layout Editor
 draw multi-vertices polygons which represent physical design
layers
 Manhattan geometries, only 90º angles
 Manhattan routing: run each interconnect layer perpendicular
to each other
 Design Rules Check (DRC)
 checks rules for each layer (size, separation, overlap)
 must pass DRC or will fail in fabrication

 Parameter Extraction
 create netlist of devices (tx, R, C) and connections
 extract parasitic Rs and Cs, lump values at each line (R) /
node (C)

EE 432 VLSI Modeling and Design 7

fAcUlty of engineering - AlexAndriA University 2013

Layout CAD Tools

 Layout vs. Schematic (LVS)
 compare layout to schematic
 check devices, connections, power routing
 can verify device sizes also
 ensures layout matches schematic exactly
 passing LVS is final step in layout

EE 432 VLSI Modeling and Design 8

fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 9

fAcUlty of engineering - AlexAndriA University 2013

Basic Structure of nWell

 nWell technology
1. Start with p-type substrate
2. nWell
3. Active
4. Poly
5. pSelect
6. nSelect
Figure 5.2 Minimum
7. Active contact line width and space
8. Poly contact  Manhattan geometries
9. Metal1 » Where all turns are multiples of 90o
10. Via » If in an arbitrary manner, then must be
11. Metal2 sure what the structures are supported
12. Overglass by the fabrication process

EE 432 VLSI Modeling and Design 10

fAcUlty of engineering - AlexAndriA University 2013

n-Wells
 An n-well is required at every location where a pFET is to be
made
 It is often possible to merge adjacent n-wells together into one
 n-well must be connected to the power supply VDD when used for pFETs

Wnw = minimum width of an n-well mask feature

Snw-nw = minimum edge-to-edge spacing of adjacent n-wells

(a) Cross-section (b) Mask set

Figure 5.3 n-well structure and mask

EE 432 VLSI Modeling and Design 11

fAcUlty of engineering - AlexAndriA University 2013

Example
 n-well
 requiredeverywhere
pMOS is needed
 rules
 minimum width
 minimum separation
to self
 minimum separation
to nMOS Active
 minimum overlap of
pMOS Active

EE 432 VLSI Modeling and Design 12

fAcUlty of engineering - AlexAndriA University 2013

Active Areas
 Silicon devices are built on active areas of the
substrate
Wa = minimum width of an Active feature
Sa-a = minimum edge-to-edge spacing of Active mask polygons

FOX = NOT (Active) (5.1)

FOX + Active = Surface (5.2)

(a) Cross-section (b) Active patterns

Figure 5.4 Active area definition

EE 432 VLSI Modeling and Design 13

fAcUlty of engineering - AlexAndriA University 2013

Example
 Active
 requiredeverywhere a transistor is needed
 any non-Active region is FOX
 rules
 minimum width
 minimum separation to other Active

MOSIS SCMOS rules; λ=0.3μm for AMI C5N

EE 432 VLSI Modeling and Design 14

fAcUlty of engineering - AlexAndriA University 2013

Doped Silicon Regions

 Thermal technique called diffusion
» Create n+ (ndiff, [Arsenic, As] or
[Phosphorus, p] ) and p+ (pdiff, [Boron,
B] ) regions
n+ = (nSelect)  (Active) (5.3)
(a) Cross-section (b) Mask set
Wa = minimum width of an Active area Figure 5.5 Design of a n+ regions
Sa-n = minimum Active-to-nSelect spacing

p+ = (pSelect)  (Active) (nWell) (5.4)

Wa = minimum width of an Active area

Sa-p = minimum Active-to-pSelect spacing
Sp-nw = minimum pSelect-to-nSelect spacing (a) Cross-section (b) Mask set

Figure 5.6 Design of a p+ regions

EE 432 VLSI Modeling and Design 15

fAcUlty of engineering - AlexAndriA University 2013

Example
 n/p Select
 defines regions to be doped n+ and p+
 tx S/D = Active AND Select NOT Poly
 tx gate = Active AND Select AND Poly
 rules
 minimum overlap of Active
 same for pMOS and nMOS

 several more complex rules available

EE 432 VLSI Modeling and Design 16

 fAcUlty of engineering - AlexAndriA University 2013

MOSFETs (1/2)
 Physically, the poly line is deposited
before the ion implant, and acts to
block dopants from entering the
silicon
 nFETs
Wp = minimum poly width (a) Cross-section (b) Layout view
Sp-p = minimum poly-to-poly spacing Figure 5.7 nFET structure
L = Wp = minimum width (length) of a Poly line
dpo = minimum extension of Poly beyond Active

nFET = (nSelect)  (Active)  (Poly) (5.5)

n+ = (nSelect) (Active)  (NOT [Poly]) (5.6)

Figure 5.8 Masks for the nFET

EE 432 VLSI Modeling and Design 17
fAcUlty of engineering - AlexAndriA University 2013

MOSFETs (2/2)
 pFETs
pFET = (pSelect)  (Active) (Poly) (nWell) (5.7)
p+ = (pSelect) (Active)  (nWell) (NOT [Poly] ) (5.8)

(a) Cross-section (b) Layout view

Figure 5.9 pFET structure Figure 5.10 Masks for the pFET

EE 432 VLSI Modeling and Design 18

fAcUlty of engineering - AlexAndriA University 2013

Example
 Poly
 high resistance conductor (can be used for short
routing)
 primarily used for tx gates

 rules
 minimum size
 minimum space to self
 minimum overlap of gate
 minimum space to Active

EE 432 VLSI Modeling and Design 19

fAcUlty of engineering - AlexAndriA University 2013

Drawn and Effective in MOSFETs

 Draw and Effective Values in MOSFETs
 The critical dimensions of a MOSFET are the
channel length L and the channel width W

 The physical length is small than L due to

lateral doping during the implant annealing
step
 Leff: electrical or effective channel length (a) Drawn Layout
 Lo: overlap distance on both sides
Leff = L – 2Lo (5.9)
Leff = L - ΔL (5.10)
 The channel width is also small than the
drawn value due to reduction of active area
by the field oxide growth
Weff = W – ΔW (5.11) (b) Finished view

W eff Figure 5.11 Drawn and

(5.12) effective dimensions of a
L eff MOSFET
EE 432 VLSI Modeling and Design 20
fAcUlty of engineering - AlexAndriA University 2013

Active Contacts
 An active contact is a cut in the Ox1 that
allows the first layer of metal1 to contact an
active n+ or p+ region
Sa-ac = minimum spacing between Active and Active
Contact
dac, v = vertical size of the contact (a) Cross-section
dac, h = horizontal size of the contact

 A square contact is obtained if, however, it is

not uncommon to have aspect rations other
than 1:1
dac, v = dac, h = dac (5.13) (b) General mask set

Figure 5.12 Active

contact formation

EE 432 VLSI Modeling and Design 21

fAcUlty of engineering - AlexAndriA University 2013

Design Rules: 3
 Contacts
 Contacts to Metal1, from
Active or Poly
 use same layer and rules for
both
 must be SQUARE and
MINIMUM SIZED
 rules
 exact size
 minimum overlap by
Active/Poly
 minimum space to Contact
 minimum space to gate

EE 432 VLSI Modeling and Design 22

fAcUlty of engineering - AlexAndriA University 2013

Metal1 (1/3)
 Metal1 is used as interconnect for signals
and power supply distribution
Wm1 = minimum width of a Metal1 line (a) Cross-section
Sm1-ac = minimum spacing from Metal1 to Active
Contact

 Every contact is characterized by a resistance

Rc = contact resistance Ω (b) General mask set
Figure 5.13 Metal1 line
 Since the contacts are all in parallel, the effective with Active Contact
resistance of the Metal1-Active connection with
N contacts is reduced to
1
Rc , eff  Rc (5.14)
N
Figure 5.14 Multiple contacts
EE 432 VLSI Modeling and Design 23
fAcUlty of engineering - AlexAndriA University 2013

Example
 Metal1
 low resistance conductor used for routing
 rules
 minimum size
 minimum space to self
 minimum overlap of Contact

EE 432 VLSI Modeling and Design 24

fAcUlty of engineering - AlexAndriA University 2013

Metal1 (2/3)
 Metal1 allows access to the active regions
of MOSFETs using the Active Contact
oxide cut as Figure 5.15

Sp-ac = minimum spacing from Poly to Active

Contact (a) Cross-section (b) Layout
Sa-p = minimum spacing from Active to Poly
Figure 5.15 Drain and source
FET terminals using Metal1
 A Poly Contact mask is used to allow
electrical connections between Metal1
and the polysilicon gate as Figure 5.16

Sp-p = minimum Poly-to-Poly spacing

(a) Cross-section (b) Layout

Figure 5.16 Poly Contact

EE 432 VLSI Modeling and Design 25

fAcUlty of engineering - AlexAndriA University 2013

Example
 Vias
 Connects Metal1 to Metal2
 must be SQUARE and MINIMUM
SIZED
 rules
 exact size
 space to self
 minimum overlap by Metal1/Metal2
 minimum space to Contact
 minimum space to Poly/Active edge
 Metal2
 low resistance conductor used for
routing
 rules
 minimum size
 minimum space to self
 minimum overlap of Via
EE 432 VLSI Modeling and Design 26
fAcUlty of engineering - AlexAndriA University 2013

Metal1 (3/3)
 Example: A pair of series-connected
FETs sharing the central n+ region as
Figure 5.17
Sp-p = minimum Poly-to-Poly
spacing

 Example: Parallel-connected FETs as (a) Cross-section (b) Layout

Figure 5.18
Figure 5.17 Series-connected FETs
Sg-g = dac + 2 Sp- (distance between the two gates)
ac

 Example: allow for the size of the

contact itself, plus two units of poly-
active spacing as Figure 5.19
 Enforced twice Sp-a
Figure 5.18 Parallel- Figure 5.19 Different
connected nFETs channel widths using
the same active region
EE 432 VLSI Modeling and Design 27
fAcUlty of engineering - AlexAndriA University 2013

Vias and Higher Level Metals

 Model CMOS processes add several additional
layers of metal that can be used for signal and
power distribution

Metal1 → Metal2 → Metal3 → Metal4

(a) Cross-section

dv = dimension of a Via (may be different for vertical direction)

wm2 = minimum width of Metal2 feature
sm2-m2 = minimum spacing between adjacent Metal2 features
sv-m1 = minimum spacing between Via and Metal1 edges
Sv-m2 = minimum spacing between Via and Metal2 edges
(b) Layout
Figure 5.20 Metal1-Metal2
connection using a Via mask
EE 432 VLSI Modeling and Design 28
fAcUlty of engineering - AlexAndriA University 2013

Latch-up
 Latch-up:is a condition that can
occur in a circuit fabricated in a
bulk CMOS technology
» The key to understanding latch-up is Figure 5.21 Latch-up
noting that the bulk technology gives a current flow path

4-layers pnpn structure between the

power supply VDD and ground
» If VDD reaches the breakover voltage
VBO, the blocking is overwhelmed by
internal electric fields
(a) Structure (b) Behavior

Figure 5.22 Characteristics

of 4-layer pnpn device

EE 432 VLSI Modeling and Design 29

fAcUlty of engineering - AlexAndriA University 2013

Equivalent circuit of CMOS latchup

• When one of the two
bipolar transistors gets
forward biased (due to
current flowing through
the well, or substrate), it
feeds the base of the
other transistor
• This positive feedback
increases the current
until the circuit fails or
burns out

EE 432 VLSI Modeling and Design 30

fAcUlty of engineering - AlexAndriA University 2013

Latch-up Prevention
 Latch-up avoiding method
» to steer the current out of the “bad” path
 Include and n-Well contact every time a pFET is connected to the
power supply VDD, and
 Include a p-substrate contact every time and nFET is connected to a
ground rail
» Silicon-on-insulator, SOI
» Twintub: using two separate wells for FETs, an n-well for
pFETs and a p-well for nFETs

EE 432 VLSI Modeling and Design 31

fAcUlty of engineering - AlexAndriA University 2013

Layout Editors
 n+ is formed whenever Active is
surrounded by nSelect; this is also called
ndiff.
 p+ is formed whenever Active is
surrounded by pSelect; this is also called
pdiff.
 A nFET is formed whenever Poly cuts an Figure 5.24 Layer key for layout
n+ region into two separate segments. drawings in this book

 A pFET is formed whenever Poly cuts an

p+ region into two separate segments.
 No electrical current path exists
between conducting layer (n+, p+, Poly,
Metal, etc.) unless a contact cut (Active
Contact, Poly Contact, or Via) is
provided.
(a) Structure (b) Behavior
Figure 5.25 Drawing complex
polygons using rectangles

EE 432 VLSI Modeling and Design 32

fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 33

fAcUlty of engineering - AlexAndriA University 2013

The Not Cell

(a) Schematic (a) Basic cell

(b) Cell layout (b) 2X cell

Figure 5.42 NOT gate width horizontal FETs Figure 5.43 Not layout using vertical FETs

EE 432 VLSI Modeling and Design 34

 fAcUlty of engineering - AlexAndriA University 2013

NAND2 and NOR2

(a) NAND2 (a) NAND2

(b) NOR2 (b) NOR2 Figure 5.47 Complex

logic gate example
Figure 5.45 NAND2 and NOR2 Figure 5.46 Alternate
layouts using vertical FETS NAND2 and NOR2 cells

EE 432 VLSI Modeling and Design 35

fAcUlty of engineering - AlexAndriA University 2013

Transistor Orientation
 Horizontal Tx (W run
vertically)
 can increase tx width with fixed pitch
(space between power rails)
 cells short & wide
 Vertical Tx (W runs
horizontally)
 pitch sets max tx width
 cells taller & narrow

EE 432 VLSI Modeling and Design 36

fAcUlty of engineering - AlexAndriA University 2013

Inverter Layout Options

 Layout with Horizontal Tx
 pitch sets max txsize
 Layout with Vertical Tx
 allows tx size scaling
without changing pitch
 Vertical Tx with 2x scaling

EE 432 VLSI Modeling and Design 37

fAcUlty of engineering - AlexAndriA University 2013

NAND/NOR Layout Alternatives

 vertical transistors
 for smaller pitch
(height) and wider
cell

 large horizontal
transistors
 for larger pitch
(height) and
narrower cell

EE 432 VLSI Modeling and Design 38

fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 39

fAcUlty of engineering - AlexAndriA University 2013

FET Sizing
 FET are specified by the aspect ratio (W/L)
 Combine with the processing parameters to give the
electrical characteristic of the transistor
 Given the gate area by AG = LW
CG = CoxWL (5.19)

ID  IS
 Since
 L 1
Rchan  Rs , c    Rchan  (5.21, 5.22)
W
  W
n   p
 Since  R
r  n  p  r (5.24, 5.25) (r = 2 ~ 3) Figure 5.36 Basic geometry
p Rn of a FET

W  W 
   r  (5.26) pFETs don’t conduct as well as nFETs
 L p  L n

CGp  rCGn (5.27) (Since C is proportional to W)

EE 432 VLSI Modeling and Design 40

fAcUlty of engineering - AlexAndriA University 2013

Unit Transistors
 Unit transistor is the minimum-size
MOSFET

W  w
   a (5.30) ( the aspect ratio )
 L  min wb

C G  C ox wa w p (5.31) ( gate capacitance) Figure 5.37 Geometry of a

minimum-size FET

dc = dimension of the contact

sa-ac = spacing between Active and Active Contact

» As Figure 5.38, the minimum width is

now

W = dc + 2sa-ac (5.32) (a) Active contact (b) Small

Wa
Figure 5.38 Minimum-size FETs
with Active Contact features

EE 432 VLSI Modeling and Design 41

 fAcUlty of engineering - AlexAndriA University 2013

Scaling Technology
 Once a unit FET has been selected, it’s useful
to allow it to be scaled in size
 Reference 1X  2X  4X
 However, Altering the size of the transistor
changes its resistance and capacitance
 Denote R1X and C1X be the R and C of the 1X Figure 5.39 Scaling of the unit transistor
device
WSX  SW1 X (5.33) (S: Scaling factor)

W4 X  4W1 X (5.34) (S = 4)

R1 X
RSX  C SX  SC1 X (5.35) (decided by FET size)
S
R1 X
R2 X  C 2 X  2C1 X (5.36) (S = 2)
2
Figure 5.40 Scaling of series-
2( R1 X / 2)  R1 X (5.37) (Figure 5.40) connected FET chain

EE 432 VLSI Modeling and Design 42

 fAcUlty of engineering - AlexAndriA University 2013

Gate Design for Transient Performance

1 2
 W  (Inverter reference starting) 
  k'    n (V DD  VTn )  N (VDD  VTn )
L
1 1
Rp  , Rn   N  2 n
 p (VDD  VTp )  n (V DD  VTn )

n   p W  W 
   2 
 L N  L n
W  W  (a) Inverter
   r   N  n (NOR2 vs Inverter)
 L p  L n
k ' 1 2
where r  n 
kp'  p (VDD  VTp )  P (VDD  VTp )
P   p (NAND2 vs Inverter)  P  2 p
R  RN  RN W  W 
   2 
 L P  L p
1
where R N 
 N (V DD  VTn ) (b) NAND2 (c) NOR2

R  Rn  2 R N Figure 7.34 Relative FET sizing

EE 432 VLSI Modeling and Design 43

fAcUlty of engineering - AlexAndriA University 2013

Gate Design for Transient Performance (2)

 Extend to large chains as Figure 7.35
 N  3 n ,  P   p (7. 177)

W  W  W  W 
   3  ,      (7. 178)
 L N  L n  L P  L  p

 N   n ,  P  3 p (7. 179)

W  W  W  W  (a) NAND3 (b) NOR3

     ,    3  (7. 180)
 L N  L n  L P  L p Figure 7.35 Sizing for 3-input gates

 Example
f  (a  b  c  d )  x (7. 181)

 N  3 n   N 1 (7. 182)

 P  2 p (7. 183)

 P1   p (7. 184)

 P1   P  2 P (7. 185)
Figure 7.36 Sizing of a complex logic gate
EE 432 VLSI Modeling and Design 44
fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 45

fAcUlty of engineering - AlexAndriA University 2013

The Cell Concept

 Each physical design file
is called a “cell”
 “Primitive” cells,
polygon-level
 create “cell library” of
basic functions
 Expanding library with
more complex cells
 primitive library cells
added as to higher level
cells to create more
complex logic functions
 the instantiated (added)
cell is called an “instance”

EE 432 VLSI Modeling and Design 46

fAcUlty of engineering - AlexAndriA University 2013

Layout Cell Definitions

 Cell Pitch = Height of standard cells
 measured between VDD & GND rails
 A: top of VDD to bottom of GND (we will
use this)
 B: interior size, without power rails
 C: middle of GND to middle of VDD
 Cell Boundary
 max extension of any layer (except nwell)
 set boundary so that cells can be placed
side-by-side without any rule violations
 extend power rails 1.5λ(or 2λto be safe)
beyond any active/poly/metal layers
 extend n-well to cell boundary (or beyond)
to avoid breaks in n-well
EE 432 VLSI Modeling and Design 47
fAcUlty of engineering - AlexAndriA University 2013

Cell Layout Guidelines

 Internal Routing
 uselowest routing layer possible, typically poly and metal1
 keep all possible routing inside power rails
 keep interconnects as short as possible

 Bulk (substrate/well) Contacts

 must have many contacts to p-substrate and n-well (at least 1
for each connection to power/ground rails)
 consider how signals will be routed in/out of the cells (don’t
block access to I/O signals with substrate/well contacts)

EE 432 VLSI Modeling and Design 48

fAcUlty of engineering - AlexAndriA University 2013

Cell Layout Guidelines (2)

 S/D Area Minimization
 minimize S/D junction areas to keep capacitance low
 I/O Pads
 Placement: must be able to route I/O signals out of cell
 Pad Layer: metal1 for smaller cells, metal2 acceptable in
larger cells
 Cell Boundary
 extend VDD and GND rail at least 1.5λbeyond internal
features
 extend n-well to cell boundary to avoid breaks in higher level
cell

EE 432 VLSI Modeling and Design 49

fAcUlty of engineering - AlexAndriA University 2013

Cell View and Cell Ports

 Cell View
 see only I/O ports (including power), typically in Metal1
 can’t see internal layer polygons of the primitive

 Ports
 all
signals that connect to higher level cells
 physical locations of the layout cell, typically in Metal1or
Metal2
 Metal1 vs Metal2 ports
 best to keep ports in Metal1 for primitives
 always try to use only the lowest level metals you can
EE 432 VLSI Modeling and Design 50
fAcUlty of engineering - AlexAndriA University 2013

Cell-based Design
 Cell-based: once a set are defined, they
may be used to create more complex
networks

 A function using unit gate of Figure 5.26

Figure 5.26 Logic gates as basic cells
f  a b (5.16)

 2 X NOT  X NAND (5.17)

 In this case, a new complex cell F1 will

become to the new unit component, and (a) Primitive (b) New complex cell
this block without decomposing it into
the primitive cells Figure 5.27 Creation of a
new cell using basic units

EE 432 VLSI Modeling and Design 51

fAcUlty of engineering - AlexAndriA University 2013

Cell-based:VDD & VSS Placement

 Power supply lines placement
» Both are shown on the Metal1

Dm1-m1 = Edge-to-Edge distance

between VDD and VSS

» Pitch

Pm1-m1 = Distance between the middle

of the VDD and VSS lines

» The two are related by, where WDD is the Figure 5.28 VDD and VSS
power supply lines
width of the power supply lines

Pm1-m1 =Dm1-m1 + WDD (5.18)

EE 432 VLSI Modeling and Design 52

fAcUlty of engineering - AlexAndriA University 2013

Cell-based: FET Placement

 Tiling Placement
 Arrays of parallel metal1are
used for interconnect
 Both Metal1 and Metal2 are
used for routing which gives
more flexibility
 Metal1 arrays consume
significant area leading to a
decreased chip density

EE 432 VLSI Modeling and Design 53

fAcUlty of engineering - AlexAndriA University 2013

Weinberger Image Placement

 A high-density technique is to
alternate VDD and VSS power
lines
 “Inverted logic cells” are defined
to be flipped in relation to the Figure 5.33 Weinberger image array

rows of “Logic cells”

 High-density placement rate

 Major drawback: must use

Metal2 or higher metal layer to
achieve this approach Figure 5.34 FET placement in
a Weinberger array

EE 432 VLSI Modeling and Design 54

fAcUlty of engineering - AlexAndriA University 2013

Outline
 Basic Concepts
 Design Rules
 Physical Design of Logic Gates
 FET Sizing and the Unit Transistor
 Cell Concepts
 Design Hierarchies

EE 432 VLSI Modeling and Design 55

fAcUlty of engineering - AlexAndriA University 2013

Design Hierarchies
 Top-down hierarchy design
 Bottom-up hierarchy design

Figure 5.48 Primitive polygon- Figure 5.50 Cell hierarchy

level library entries

Figure 5.51 Effect of the flatten operation

Figure 5.49 Expanding the library
with more complex cells
EE 432 VLSI Modeling and Design 56
fAcUlty of engineering - AlexAndriA University 2013

Hierarchical Design
 Start with Primitives
 basic transistor-level
gates/functions
 optimize performance and layout
 layout with polygons
 Build larger cells from primitives
 layout with instances of
primitives
 polygons for transistors and
routing
 Build even larger cells
 layout with instances of lower • Advantages of Hierarchical Design:
level cells • allow layout optimization within each cell
 polygons only for signal routing • eases layout effort at higher level
• higher level layout deal with
 Repeat for necessary levels of
hierarchy until Final Chip interconnects rather than tx layout

Primitives must be done using custom techniques, but higher

level layout can use automated (place-and-route) CAD tools
EE 432 VLSI Modeling and Design 57
fAcUlty of engineering - AlexAndriA University 2013

Hierarchical Design Concepts

 Building Functions from Primitives
 instantiate one or more lower-level cells to from higher-level
function
 Example: f = a

EE 432 VLSI Modeling and Design 58

fAcUlty of engineering - AlexAndriA University 2013

Hierarchical Design Concepts (2)

 Final Chip
 flatten all cells to create one level of polygons
 allows masks to be made for each layout layer
 removes hierarchy

IMPORTANT:
Don’t flatten your cells! There are other ways to peak (see) lower
level cells instantiated within a higher level cell

EE 432 VLSI Modeling and Design 59