Features _äìÉ`çêÉ∆RJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF

■ Fully qualified Bluetooth v2.1 + EDR specification Fully Qualified Single-chip

system
■ Best-in-class Bluetooth radio with 5.5dBm
Bluetooth® v2.1 + EDR System
transmit power and -91dBm receive sensitivity
Production Information
■ 64MIPS Kalimba DSP coprocessor
■ 16-bit internal stereo codec: 95dB SNR for DAC
BC57G687C
■ Low-power 1.5V operation, 1.8V to 3.6V I/O
■ Integrated 1.5V and 1.8V linear regulators
Issue 3
■ Integrated switch-mode regulator
■ Integrated battery charger

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ USB, I²C and UART with dual-port bypass mode
to 4Mbits/s
■ 16Mb internal flash memory
■ Multi-configurable I²S, PCM or SPDIF interface
■ Enhanced audibility and noise cancellation
■ 7 x 7 x 1.3mm, 0.5mm pitch 120-ball LFBGA
■ Support for IEEE 802.11 coexistence
■ Green (RoHS compliant and no antimony or
halogenated flame retardants)

General Description Applications

■ Bluetooth-enabled automotive wireless gateways
_äìÉ`çêÉ∆RJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF is a product from
CSR's Connectivity Centre. It is a single-chip radio and
■ High-quality stereo wireless headsets
baseband IC for Bluetooth v2.1 + EDR specification ■ High-quality mono headsets
systems. ■ Hands-free car kits
■ Wireless speakers
BlueCore5‑Multimedia Flash (16Mb) contains 16Mb ■ VoIP handsets
internal flash memory, which makes it one of the most
■ Analogue and USB multimedia dongles
powerful and flexible Bluetoooth audio solutions with
the smallest PCB footprint on the market today. When Contains auto-calibration and BIST routines to simplify
used with CSR's Bluetooth stack, it provides a fully development, type approval and production test.
compliant Bluetooth v2.1 + EDR specification for data
and voice. To improve the performance of both Bluetooth and
IEEE 802.11b/g co-located systems a wide range of
BlueCore5‑Multimedia Flash (16Mb) contains the coexistence features are available including a variety
Kalimba DSP coprocessor with double the MIPS and of hardware signalling: basic activity signalling, Intel
double the memory of BlueCore3-Multimedia, WCS activity and channel signalling.
supporting enhanced audio applications.
For further device performance and additional
BlueCore5‑Multimedia Flash (16Mb) is designed to information refer to the BlueCore5‑Multimedia Flash
reduce the number of external components required (16Mb) Performance Specification.
which ensures production costs are minimised.

XTAL SPI
Flash

PIO
RAM

USB

Baseband I/O
RF IN 2.4GHz
RF OUT Radio UART

MCU
Audio In / Out

Kalimba DSP
PCM/ I2C / SPDIF

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 Document History

Document History
Revision Date Change Reason
1 01 DEC 09 Original publication of document.
2 17 DEC 09 Updates to improve clarity of ESD Precautions and Power Consumption.
3 21 DEC 09 ESD updates.
If you have any comments about this document, email [email protected] giving
the number, title and section with your feedback.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Production Information
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© Cambridge Silicon Radio Limited 2009
 Status Information

Status Information
The status of this Data Sheet is Production Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Pre-production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
CSR Green Semiconductor Products and RoHS Compliance
BlueCore5‑Multimedia Flash (16Mb) devices meet the requirements of Directive 2002/95/EC of the European
Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).
BlueCore5‑Multimedia Flash (16Mb) devices are also free from halogenated or antimony trioxide-based flame
retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement
for CSR Green Semiconductor Products.
Trademarks, Patents and Licences
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its
affiliates. Bluetooth ® and the Bluetooth ® logos are trademarks owned by Bluetooth ® SIG, Inc. and licensed to
CSR. Other products, services and names used in this document may have been trademarked by their respective
owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by CSR plc and/or its affiliates.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
Refer to www.csrsupport.com for compliance and conformance to standards information.
No statements or representations in this document are to be construed as advertising, marketing, or offering for sale
in the United States imported covered products subject to the Cease and Desist Order issued by the U.S.
International Trade Commission in its Investigation No. 337-TA-602. Such products include SiRFstarIII chips that
operate with SiRF software that supports SiRFInstantFix, and/or SiRFLoc servers, or contains SyncFreeNav
functionality.

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 Contents

Contents
1 Device Details ................................................................................................................................................. 9
2 Functional Block Diagram ............................................................................................................................ 10
3 Package Information ..................................................................................................................................... 11
3.1 Pinout Diagram .................................................................................................................................... 11
3.2 Device Terminal Functions .................................................................................................................. 12
3.3 Package Dimensions ........................................................................................................................... 17
3.4 PCB Design and Assembly Considerations ......................................................................................... 18

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

3.5 Typical Solder Reflow Profile ............................................................................................................... 18
4 Bluetooth Modem .......................................................................................................................................... 19
4.1 RF Ports ............................................................................................................................................... 19
4.1.1 RF_N and RF_P ..................................................................................................................... 19
4.2 RF Receiver ......................................................................................................................................... 19
4.2.1 Low Noise Amplifier ............................................................................................................... 19
4.2.2 RSSI Analogue to Digital Converter ....................................................................................... 20
4.3 RF Transmitter ..................................................................................................................................... 20
4.3.1 IQ Modulator .......................................................................................................................... 20
4.3.2 Power Amplifier ...................................................................................................................... 20
4.3.3 Transmit RF Power Control for Class 1 Applications (TX_PWR) ........................................... 20
4.4 Bluetooth Radio Synthesiser ............................................................................................................... 21
4.5 Baseband ............................................................................................................................................. 21
4.5.1 Burst Mode Controller ............................................................................................................ 21
4.5.2 Physical Layer Hardware Engine ........................................................................................... 21
4.6 Basic Rate Modem .............................................................................................................................. 21
4.7 Enhanced Data Rate Modem .............................................................................................................. 22
5 Clock Generation .......................................................................................................................................... 23
5.1 Clock Architecture ................................................................................................................................ 23
5.2 Input Frequencies and PS Key Settings .............................................................................................. 23
5.3 External Reference Clock .................................................................................................................... 24
5.3.1 Input: XTAL_IN ....................................................................................................................... 24
5.3.2 XTAL_IN Impedance in External Mode .................................................................................. 24
5.3.3 Clock Start-up Delay .............................................................................................................. 24
5.3.4 Clock Timing Accuracy ........................................................................................................... 24
5.4 Crystal Oscillator: XTAL_IN and XTAL_OUT ....................................................................................... 25
5.4.1 Load Capacitance .................................................................................................................. 26
5.4.2 Frequency Trim ...................................................................................................................... 26
5.4.3 Transconductance Driver Model ............................................................................................ 27
5.4.4 Negative Resistance Model ................................................................................................... 27
5.4.5 Crystal PS Key Settings ......................................................................................................... 28
6 Bluetooth Stack Microcontroller .................................................................................................................... 29
6.1 TCXO Enable OR Function ................................................................................................................. 29
6.2 Programmable I/O Ports, PIO and AIO ................................................................................................ 29
6.3 WLAN Coexistence Interface ............................................................................................................... 30
7 Kalimba DSP ................................................................................................................................................ 31
8 Memory Interface and Management ............................................................................................................. 32
8.1 Memory Management Unit .................................................................................................................. 32
8.2 System RAM ........................................................................................................................................ 32
8.3 Kalimba DSP RAM .............................................................................................................................. 32
8.4 Internal Flash Memory (16Mb) ............................................................................................................. 32
8.4.1 Flash Specification ................................................................................................................. 32
9 Serial Interfaces ............................................................................................................................................ 33

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 Contents

9.1 UART Interface .................................................................................................................................... 33

9.1.1 UART Configuration While Reset is Active ............................................................................ 35
9.1.2 UART Bypass Mode ............................................................................................................... 35
9.1.3 Current Consumption in UART Bypass Mode ........................................................................ 36
9.2 USB Interface ...................................................................................................................................... 36
9.3 Programming and Debug Interface ...................................................................................................... 36
9.3.1 Instruction Cycle ..................................................................................................................... 36
9.3.2 Multi-slave Operation ............................................................................................................. 37
9.4 I²C Interface ......................................................................................................................................... 37
9.4.1 Software I²C Interface ............................................................................................................ 37
9.4.2 Bit-serialiser Interface ............................................................................................................ 37

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

10 Audio Interface .............................................................................................................................................. 38
10.1 Audio Input and Output ........................................................................................................................ 38
10.2 Stereo Audio Codec Interface .............................................................................................................. 38
10.2.1 Stereo Audio Codec Block Diagram ....................................................................................... 39
10.2.2 Stereo Codec Set-up .............................................................................................................. 39
10.2.3 ADC ........................................................................................................................................ 40
10.2.4 ADC Sample Rate Selection .................................................................................................. 40
10.2.5 ADC Digital Gain .................................................................................................................... 40
10.2.6 ADC Analogue Gain ............................................................................................................... 40
10.2.7 DAC ........................................................................................................................................ 41
10.2.8 DAC Sample Rate Selection .................................................................................................. 41
10.2.9 DAC Digital Gain .................................................................................................................... 41
10.2.10 DAC Analogue Gain ............................................................................................................... 42
10.2.11 Microphone Input ................................................................................................................... 42
10.2.12 Line Input ............................................................................................................................... 45
10.2.13 Output Stage .......................................................................................................................... 46
10.2.14 Mono Operation ..................................................................................................................... 47
10.2.15 Side Tone ............................................................................................................................... 47
10.2.16 Integrated Digital Filter ........................................................................................................... 47
10.3 PCM Interface ...................................................................................................................................... 48
10.3.1 PCM Interface Master/Slave .................................................................................................. 48
10.3.2 Long Frame Sync ................................................................................................................... 49
10.3.3 Short Frame Sync .................................................................................................................. 49
10.3.4 Multi-slot Operation ................................................................................................................ 50
10.3.5 GCI Interface .......................................................................................................................... 50
10.3.6 Slots and Sample Formats ..................................................................................................... 51
10.3.7 Additional Features ................................................................................................................ 51
10.3.8 PCM Timing Information ........................................................................................................ 52
10.3.9 PCM_CLK and PCM_SYNC Generation ................................................................................ 55
10.3.10 PCM Configuration ................................................................................................................. 55
10.4 Digital Audio Interface (I²S) .................................................................................................................. 57
11 Power Control and Regulation ...................................................................................................................... 62
11.1 Power Sequencing ............................................................................................................................... 62
11.2 External Voltage Source ...................................................................................................................... 63
11.3 Switch-mode Regulator ....................................................................................................................... 63
11.4 High-voltage Linear Regulator ............................................................................................................. 63
11.5 Low-voltage Linear Regulator .............................................................................................................. 63
11.6 Low-voltage Audio Linear Regulator .................................................................................................... 64
11.7 Voltage Regulator Enable Pins ............................................................................................................ 64
11.8 Battery Charger ................................................................................................................................... 64
11.9 LED Drivers ......................................................................................................................................... 65
11.10Reset, RST# ........................................................................................................................................ 66
11.10.1 Digital Pin States on Reset .................................................................................................... 67

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 Contents

11.10.2 Status after Reset .................................................................................................................. 67

12 Example Application Schematic ................................................................................................................... 68
13 Electrical Characteristics .............................................................................................................................. 69
13.1 Absolute Maximum Ratings ................................................................................................................. 69
13.2 Recommended Operating Conditions .................................................................................................. 69
13.3 Input/Output Terminal Characteristics ................................................................................................. 70
13.3.1 High-voltage Linear Regulator ............................................................................................... 70
13.3.2 Low-voltage Linear Regulator ................................................................................................ 71
13.3.3 Low-voltage Linear Audio Regulator ...................................................................................... 72
13.3.4 Reset ...................................................................................................................................... 73
13.3.5 Regulator Enable ................................................................................................................... 73

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

13.3.6 Switch-mode Regulator .......................................................................................................... 74
13.3.7 Battery Charger ...................................................................................................................... 75
13.3.8 Digital Terminals .................................................................................................................... 76
13.3.9 LED Driver Pads .................................................................................................................... 77
13.3.10 USB ........................................................................................................................................ 77
13.3.11 Auxiliary ADC ......................................................................................................................... 78
13.3.12 Auxiliary DAC ......................................................................................................................... 78
13.3.13 Clocks .................................................................................................................................... 79
13.3.14 Stereo Codec: Analogue to Digital Converter ........................................................................ 80
13.3.15 Stereo Codec: Digital to Analogue Converter ........................................................................ 81
13.4 ESD Precautions ................................................................................................................................. 81
14 Power Consumption ..................................................................................................................................... 82
14.1 Kalimba DSP and Codec Typical Average Current Consumption ....................................................... 84
14.2 Typical Peak Current at 20°C .............................................................................................................. 84
14.3 Conditions ............................................................................................................................................ 84
15 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 85
15.1 RoHS Statement .................................................................................................................................. 85
15.1.1 List of Restricted Materials ..................................................................................................... 85
16 CSR Synergy and Bluetooth Software Stack ................................................................................................ 86
16.1 BlueCore HCI Stack ............................................................................................................................ 86
16.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ......................................... 86
16.1.2 Key Features of the HCI Stack: Extra Functionality ............................................................... 88
16.2 Stand-alone BlueCore5‑Multimedia Flash (16Mb) and Kalimba DSP Applications ............................. 89
16.3 Host-Side Software .............................................................................................................................. 89
16.4 eXtension ............................................................................................................................................. 89
17 Ordering Information ..................................................................................................................................... 90
18 Tape and Reel Information ........................................................................................................................... 91
18.1 Tape Orientation .................................................................................................................................. 91
18.2 Tape Dimensions ................................................................................................................................. 91
18.3 Reel Information .................................................................................................................................. 92
18.4 Moisture Sensitivity Level .................................................................................................................... 92
19 Document References .................................................................................................................................. 93
Terms and Definitions ............................................................................................................................................ 94

List of Figures
Figure 2.1 Functional Block Diagram ............................................................................................................... 10
Figure 3.1 Device Pinout .................................................................................................................................. 11
Figure 3.2 120-ball LFBGA Package Dimensions ............................................................................................ 17
Figure 4.1 Simplified Circuit RF_N and RF_P .................................................................................................. 19
Figure 4.2 Internal Power Ramping .................................................................................................................. 20
Figure 4.3 BDR and EDR Packet Structure ..................................................................................................... 22

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 Contents

Figure 5.1 Clock Architecture ........................................................................................................................... 23

Figure 5.2 TCXO Clock Accuracy .................................................................................................................... 25
Figure 5.3 Crystal Driver Circuit ....................................................................................................................... 25
Figure 5.4 Crystal Equivalent Circuit ................................................................................................................ 25
Figure 6.1 Example TCXO Enable OR Function .............................................................................................. 29
Figure 7.1 Kalimba DSP Interface to Internal Functions .................................................................................. 31
Figure 9.1 Universal Asynchronous Receiver .................................................................................................. 33
Figure 9.2 Break Signal .................................................................................................................................... 34
Figure 9.3 UART Bypass Architecture ............................................................................................................. 35
Figure 9.4 Example EEPROM Connection ...................................................................................................... 37
Figure 10.1 Audio Interface ................................................................................................................................ 38

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Figure 10.2 Stereo Codec Audio Input and Output Stages ................................................................................ 39
Figure 10.3 ADC Analogue Amplifier Block Diagram ......................................................................................... 41
Figure 10.4 Microphone Biasing ......................................................................................................................... 42
Figure 10.5 Differential Input .............................................................................................................................. 46
Figure 10.6 Single-ended Input .......................................................................................................................... 46
Figure 10.7 Speaker Output ............................................................................................................................... 46
Figure 10.8 PCM Interface Master ..................................................................................................................... 49
Figure 10.9 PCM Interface Slave ....................................................................................................................... 49
Figure 10.10 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 49
Figure 10.11 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 50
Figure 10.12 Multi-slot Operation with Two Slots and 8-bit Companded Samples .............................................. 50
Figure 10.13 GCI Interface ................................................................................................................................... 50
Figure 10.14 16-Bit Slot Length and Sample Formats ......................................................................................... 51
Figure 10.15 PCM Master Timing Long Frame Sync ........................................................................................... 53
Figure 10.16 PCM Master Timing Short Frame Sync .......................................................................................... 53
Figure 10.17 PCM Slave Timing Long Frame Sync ............................................................................................. 54
Figure 10.18 PCM Slave Timing Short Frame Sync ............................................................................................ 55
Figure 10.19 Digital Audio Interface Modes ......................................................................................................... 59
Figure 10.20 Digital Audio Interface Slave Timing ............................................................................................... 60
Figure 10.21 Digital Audio Interface Master Timing ............................................................................................. 61
Figure 11.1 Voltage Regulator Configuration ..................................................................................................... 62
Figure 11.2 LED Equivalent Circuit .................................................................................................................... 66
Figure 12.1 Example Application Schematic ...................................................................................................... 68
Figure 16.1 BlueCore HCI Stack ........................................................................................................................ 86
Figure 16.2 Stand-alone BlueCore5‑Multimedia Flash (16Mb) and Kalimba DSP Applications ........................ 89
Figure 18.1 BlueCore5‑Multimedia Flash (16Mb) Tape Orientation ................................................................... 91
Figure 18.2 Tape Dimensions ............................................................................................................................ 91
Figure 18.3 Reel Dimensions ............................................................................................................................. 92

List of Tables
Table 4.1 TXRX_PIO_CONTROL Values ........................................................................................................ 21
Table 4.2 Data Rate Schemes ......................................................................................................................... 22
Table 5.1 PS Key Values for CDMA/3G Phone TCXO .................................................................................... 23
Table 5.2 External Clock Specifications ........................................................................................................... 24
Table 5.3 Crystal Specification ......................................................................................................................... 26
Table 8.1 Internal Flash Device Specifications ................................................................................................ 32
Table 9.1 Possible UART Settings ................................................................................................................... 33
Table 9.2 Standard Baud Rates ....................................................................................................................... 34
Table 9.3 Instruction Cycle for a SPI Transaction ............................................................................................ 36
Table 10.1 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 38
Table 10.2 ADC Digital Gain Rate Selection ...................................................................................................... 40

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 Contents

Table 10.3 DAC Digital Gain Rate Selection ...................................................................................................... 42

Table 10.4 DAC Analogue Gain Rate Selection ................................................................................................. 42
Table 10.5 Voltage Output Steps ....................................................................................................................... 44
Table 10.6 Current Output Steps ....................................................................................................................... 45
Table 10.7 PCM Master Timing .......................................................................................................................... 52
Table 10.8 PCM Slave Timing ............................................................................................................................ 54
Table 10.9 PSKEY_PCM_LOW_JITTER_CONFIG Description ......................................................................... 56
Table 10.10 PSKEY_PCM_CONFIG32 Description ............................................................................................. 56
Table 10.11 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 57
Table 10.12 PSKEY_DIGITAL_AUDIO_CONFIG ................................................................................................. 58
Table 10.13 Digital Audio Interface Slave Timing ................................................................................................ 60

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Table 10.14 Digital Audio Interface Master Timing .............................................................................................. 61
Table 11.1 BlueCore5‑Multimedia Flash (16Mb) Voltage Regulator Enable Pins .............................................. 64
Table 11.2 Pin States on Reset .......................................................................................................................... 67

List of Equations
Equation 4.1 Output Voltage with Load Current I ................................................................................................. 20
Equation 4.2 Output Voltage with No Load Current ............................................................................................. 20
Equation 5.1 Load Capacitance ........................................................................................................................... 26
Equation 5.2 Trim Capacitance ............................................................................................................................ 26
Equation 5.3 Frequency Trim ............................................................................................................................... 26
Equation 5.4 Pullability ......................................................................................................................................... 27
Equation 5.5 Transconductance Required for Oscillation .................................................................................... 27
Equation 5.6 Equivalent Negative Resistance ..................................................................................................... 27
Equation 9.1 Baud Rate ....................................................................................................................................... 34
Equation 10.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 48
Equation 10.2 IIR Filter plus DC Blocking Transfer Function, HDC(z) .................................................................... 48
Equation 10.3 PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock ........................... 55
Equation 10.4 PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 55
Equation 11.1 LED Current .................................................................................................................................... 66
Equation 11.2 LED PAD Voltage ............................................................................................................................ 66

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 Device Details

1 Device Details

Radio Kalimba DSP

■ Common TX/RX terminal simplifies external ■ Very low power Kalimba DSP coprocessor,
matching; eliminates external antenna switch 64MIPS, 24-bit fixed point core
■ BIST minimises production test time ■ SBC decode takes approximately 4mW power
■ Bluetooth v2.1 + EDR specification compliant consumption while streaming music
■ Single-cycle MAC; 24 x 24-bit multiply and 56-bit
Transmitter accumulator

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ 5.5dBm RF transmit power with level control from ■ 32-bit instruction word, dual 24-bit data memory
on-chip 6-bit DAC over a dynamic range >30dB ■ 6K x 32-bit program RAM, 16K x 24-bit + 12K x 24-
■ Class 2 and Class 3 support without the need for an bit data RAM
external power amplifier or TX/RX switch ■ 64-word x 32-bit program memory cache when
executing from internal flash
Receiver
Stereo Audio Codec
■ Receiver sensitivity of -91dBm
■ Integrated channel filters ■ 16-bit internal stereo codec
■ Digital demodulator for improved sensitivity and co- ■ Dual ADC and DAC for stereo audio
channel rejection ■ Integrated amplifiers for driving 16Ω speakers; no
■ Real-time digitised RSSI available on HCI interface need for external components
■ Fast AGC for enhanced dynamic range ■ Support for single-ended speaker termination and
line output
Synthesiser ■ Integrated low-noise microphone bias
■ ADC sample rates are 8, 11.025, 16, 22.05, 32 and
■ Fully integrated synthesiser requires no external
44.1kHz
VCO, varactor diode, resonator or loop filter
■ DAC sample rates are 8, 11.025, 12, 16, 22.05, 24,
■ Compatible with crystals 16MHz to 26MHz or an
32, 44.1 and 48kHz
external clock 12MHz to 52MHz
■ Accepts 14.40, 15.36, 16.2, 16.8, 19.2, 19.44, Auxiliary Features
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic ■ User space on processor for customer applications
level signals ■ Crystal oscillator with built-in digital trimming
■ Power management includes digital shutdown and
Baseband and Software wake-up commands with an integrated low-power
oscillator for ultra-low power Park/Sniff/Hold mode
■ 16Mb internal flash
■ Clock request output to control external clock
■ 48KB internal RAM, allows full-speed data transfer,
mixed voice/data and full piconet support
■ On-chip regulators: 1.5V output from 1.8V to 2.7V
input and 1.8V output from 2.7V to 4.5V input
■ Logic for forward error correction, header error
control, access code correlation, CRC,
■ On-chip high-efficiency switch-mode regulator;
demodulation, encryption bit stream generation, 1.8V output from 2.7V to 4.4V input
whitening and transmit pulse shaping ■ Power-on-reset cell detects low supply voltage
■ Transcoders for A-law, µ-law and linear voice from ■ 10-bit ADC and 8-bit DAC available to applications
host and A-law, µ-law and CVSD voice over air ■ On-chip charger for lithium ion/polymer batteries

Physical Interfaces Bluetooth Stack

■ SPI with clock speeds up to 64MHz in master mode, CSR's Bluetooth Protocol Stack runs on the on-chip
requires firmware support, and 32MHz in slave MCU in a variety of configurations:
mode ■ Standard HCI, UART or USB
■ I²C master compatible interface ■ Audio codec and echo-noise suppression or
■ UART interface with programmable data rate up to customer-specific algorithms running on the DSP
3Mbits/s with an optional bypass mode
■ USB v2.0 interface Package Option
■ Bidirectional serial programmable audio interface ■ LFBGA 120-ball, 7 x 7 x 1.3mm, 0.5mm pitch
supporting PCM, I²S and SPDIF formats
■ 2 LED drivers with faders

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 Functional Block Diagram

2 Functional Block Diagram

UART_CTS
UART_RTS
VDD_USB

SPI_MOSI
SPI_MISO
UART_RX
UART_TX

SPI_CS#
SPI_CLK
USB_DN
USB_DP
PIO[8]
PIO[7]
PIO[6]
I2C Bus available on any PIO
pins, default configuration shown

SDA
SCL
SPI
I2C Interface USB UART
Interface

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Serial Interfaces

Bluetooth Modem

Baseband

Memory Management Unit

Basic Rate
Modem PCM_CLK

PCM /I2S
Interface
RF_N Bluetooth PCM_SYNC
RF_P v2.1 Radio
Enhanced PCM_OUT
Rate Modem PCM_IN
System RAM

VDD_CORE Radio Control

SPDIF
Audio Interfaces
VSS_RADIO
Microcontroller DSP
VSS_ANA
Interrupt Interrupt
VDD_LO Controller Controller SPKR_A_N
VSS_LO SPKR_A_P
SPKR_B_N
LO_REF Timers MCU Timers Kalimba DSP

Stereo Audio
SPKR_B_P

Interface
MIC_BIAS
XTAL_OUT MIC_A_N
Clock
MIC_A_P
XTAL_IN Generation
MIC_B_N
MIC_B_P
AUX Data Memory Data Memory Program AU_REF_DCPL
AUX_DAC DM1 DM2 Memory PM
DAC

Power Control and Regulation

VDD_CHG IN
VDD_PADS
Battery Charger
OUT
VSS_DIG

BAT_P
VDD_SMP_CORE SENSE
Programmable I/O Internal Flash Memory Interface
Switch Mode
LX SUBS
Regulator
BAT_N EN
LED Driver AIO GPIO Flash
VREGENABLE_H RST#
VREGIN_H IN EN
TEST_EN
High Voltage
Linear Regulator
VREGOUT_H OUT SENSE

VREGENABLE_L
VREGIN_L IN EN
Low Voltage
Linear Regulator
VDD_ANA OUT SENSE

VDD_RADIO
VREGIN_AUDIO IN EN
Audio Low
Voltage Regulator
VDD_AUDIO OUT SENSE

G-TW-0001454.2.4
VSS_AUDIO
LED[0]

LED[1]

AIO[0]
AIO[1]

VSS_PIO
VDD_PIO
PIO[5:0]
PIO[15:9]

VDD_MEM
Figure 2.1: Functional Block Diagram

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 Package Information

3 Package Information
3.1 Pinout Diagram
Top View

1 2 3 4 5 6 7 8 9 10 11 12 13

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

D D1 D2 D3 D11 D12 D13

E E1 E2 E3 E11 E12 E13

F F1 F2 F3 F11 F12 F13

G G1 G2 G3 G11 G12 G13

H H1 H2 H3 H11 H12 H13

J J1 J2 J3 J11 J12 J13

K K1 K2 K3 K11 K12 K13

L L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13

M M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13

G-TW-0001457.2.2

N N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

Figure 3.1: Device Pinout

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 Package Information

3.2 Device Terminal Functions

Radio Ball Pad Type Supply Domain Description

Transmitter output/switched
RF_P H1
receiver input
RF VDD_RADIO
RF_N J1 Complement of RF_P

AUX_DAC H3 Analogue VDD_PIO Voltage DAC

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Synthesiser and
Ball Pad Type Supply Domain Description
Oscillator

XTAL_IN N1 For crystal or external clock input

XTAL_OUT N2 Drive for crystal

Analogue VDD_ANA
Reference voltage to decouple the
LO_REF N5
synthesiser

UART Ball Pad Type Supply Domain Description

Bidirectional CMOS
UART_TX L13 output, tristate, with UART data output
weak internal pull-up

CMOS input with

UART_RX M12 weak internal pull- UART data input
down
VDD_USB
Bidirectional CMOS
UART_RTS M11 output, tristate, with UART request to send, active low
weak internal pull-up

CMOS input with

UART_CTS M13 weak internal pull- UART clear to send, active low
down

USB Ball Pad Type Supply Domain Description

USB data plus with selectable

USB_DP N13
internal 1.5kΩ pull-up resistor
Bidirectional VDD_USB
USB_DN N12 USB data minus

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 Package Information

PCM Interface Ball Pad Type Supply Domain Description

CMOS output,
PCM_OUT F11 tristate, with weak Synchronous data output
internal pull-down

CMOS input, with

PCM_IN F13 weak internal pull- Synchronous data input
down
VDD_PADS
Bidirectional with

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

PCM_SYNC G11 weak internal pull- Synchronous data sync
down

Bidirectional with
PCM_CLK H11 weak internal pull- Synchronous data clock
down

SPI Interface Ball Pad Type Supply Domain Description

CMOS output,
SPI_MISO E12 tristate, with weak SPI data output
internal pull-down

CMOS input, with

SPI_MOSI F12 weak internal pull- SPI data input
down VDD_PADS

Input with weak

SPI_CS# E13 Chip select for SPI, active low
internal pull-up

Input with weak

SPI_CLK E11 SPI clock
internal pull-down

PIO Port Ball Pad Type Supply Domain Description

Programmable input/output line

PIO[0]/RXEN E3
(external RXEN)
Bidirectional with
Programmable input/output line
PIO[1]/TXEN F3 programmable
VDD_PIO (external TXEN)
strength internal pull-
up/down
PIO[2] E2 Programmable input/output line

PIO[3] D3 Programmable input/output line

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 Package Information

PIO Port Ball Pad Type Supply Domain Description

PIO[4] H12

PIO[5] J11

PIO[6] M8

PIO[7] H13

PIO[8] J12

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Bidirectional with
PIO[9] L12
programmable
VDD_PADS Programmable input/output line
strength internal pull-
PIO[10] L10
up/down
PIO[11] M10

PIO[12] K12

PIO[13] M9

PIO[14] L9

PIO[15] N9

AIO[0] N6
Analogue programmable input/
Bidirectional VDD_ANA
output line
AIO[1] M5

Test and Debug Ball Pad Type Supply Domain Description

Reset if low. Input debounced so

CMOS input with
RST# G13 VDD_PADS must be low for >5ms to cause a
weak internal pull-up
reset

CMOS input with

For test purposes only (leave
TEST_EN G12 strong internal pull- VDD_PADS
unconnected)
down

Codec Ball Pad Type Supply Domain Description

MIC_A_P B2 Microphone input positive, left

Analogue VDD_AUDIO
MIC_A_N B1 Microphone input negative, left

MIC_B_P A2 Microphone input positve, right

Analogue VDD_AUDIO
MIC_B_N A1 Microphone input negative, right

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 Package Information

Codec Ball Pad Type Supply Domain Description

SPKR_A_P D1 Speaker output positive, left

Analogue VDD_AUDIO
SPKR_A_N D2 Speaker output negative, left

SPKR_B_P A3 Speaker output positive, right

Analogue VDD_AUDIO
SPKR_B_N B3 Speaker output negative, right

MIC_BIAS A5 Analogue VDD_AUDIO Microphone bias

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Decoupling of audio reference (for
AU_REF_DCPL C1 Analogue VDD_AUDIO
high-quality audio)

LED Drivers Ball Pad Type Supply Domain Description

LED[1] C8 LED driver

Open drain output See Section 11.9
LED[0] D11 LED driver

Power Supplies and

Ball Pad Type Description
Control

Take high to enable both low-

VREGENABLE_L M3 Analogue voltage regulator and audio low-
voltage regulator

Take high to enable high-voltage

VREGENABLE_H C7 Analogue linear regulator and switch-mode
regulator

Low-voltage linear regulator input

VREGIN_L M2 Regulator input
for non-audio core circuitry

Audio low-voltage linear regulator

VREGIN_AUDIO A4 Regulator input
input

VREGIN_H B12, C12 Regulator input High-voltage linear regulator input

VREGOUT_H D12, D13 Supply High-voltage linear regulator output

Switch-mode power Switch-mode power regulator

LX A11, B11
regulator output output

Positive supply for UART and USB

VDD_USB N10 VDD
ports

Positive supply for PIO and AUX

VDD_PIO E1 VDD
DAC

Positive supply for all other digital

VDD_PADS K13 VDD
input/output ports

Positive supply for internal digital

VDD_CORE C13, J13 VDD
circuitry, 1.5V

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 Package Information

Power Supplies and

Ball Pad Type Description
Control

VDD/Low-voltage
VDD_RADIO K1 Positive supply for RF circuitry, 1.5V
regulator sense

Positive supply for local oscillator

VDD_LO L1 VDD
circuitry, 1.5V

Positive supply output for analogue

VDD/Low-voltage
VDD_ANA M1 circuitry and 1.5V regulated output
regulator output

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

(from low-voltage regulator)

VDD_AUDIO B4 VDD Positive supply for audio, 1.5V

Lithium ion/polymer battery positive

BAT_P A12, A13 Battery terminal +ve terminal. Battery charger output and
input to switch-mode regulator.

Lithium ion/polymer battery charger

VDD_CHG B8, B9, C9 Charger input
input

Positive supply for switch mode

VDD_SMP_CORE B13 VDD
control circuitry

Positive supply for internal Flash

VDD_MEM A8, N11 VDD
memory

G3, C6, N7, A9, A10, C11, Ground connection for internal
VSS_DIG VSS
K11, L11 digital circuitry

VSS_RADIO F2, G2, H2, J2 VSS Ground connections for RF circuitry

Ground connections for local

VSS_LO L2, L3 VSS
oscillator

Ground connections for analogue

VSS_ANA N3, N4 VSS
circuitry

VSS_AUDIO C2, C3, C4 VSS Ground connection for audio

Lithium ion/polymer battery

negative terminal. Ground
BAT_N B10, C10 Battery terminal -ve
connection for switch-mode
regulator.

K2, J3, K3, L4, M4, B5, C5, Connection to internal die substrate.
SUBS L5, A6, B6, L6, M6, A7, B7, VSS Connect to lowest possible
L7, M7, L8, N8 potential.

Unconnected Terminals Ball Description

NC F1, G1 Leave unconnected

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 Package Information

3.3 Package Dimensions

Top View Bottom View
1 2 3 4 5 6 7 8 10 11 12 13 13 12 11 10 8 7 6 5 4 3 2 1

A A
B B
C C
D D
E E

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

F F
G G
H H
J J
K K
L L
M M
N N

0.1 Z 3
A3
A2 A
A1
Scale = 1mm

0.08 Z Z 2 SEATING PLANE

Description 120-Ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA)

Size 7 x 7 x 1.3mm

Pitch 0.5mm

Package Ball Land Solder mask defined. Solder mask aperture 275μm Ø

Dimension Minimum Typical Maximum Notes

A - - 1.30 1 Dimension b is measured at the maximum

A1 0.16 - 0.26 solder ball diameter parallel to datum
plane Z
A2 - 0.21 -
A3 - 0.80 - 2 Datum Z is defined by the spherical crowns
b 0.27 - 0.37 of the solder balls

D - 7 -
3 Parallelism measurement shall exclude any
E - 7 - effect of mark on top surface of package
e - 0.50 -
D1 - 6.00 - Top-side polarity mark. The dimensions of
4 the square polarity mark are 0.5 x 0.5mm.
E1 - 6.00 -
F 0.450 0.500 0.550 Bottom-side polarity mark. The dimensions of
5
G 0.450 0.500 0.550 the triangular polarity mark are 0.30 x 0.30 x
0.42mm.
H 0.450 0.500 0.550
J 0.450 0.500 0.550
PX - 0.350 -
PY - 0.350 -
SD - 0 -
SE - 0 -
X - 1.10 -
Y - 0.70 -

JEDEC MO-225

Unit mm

Figure 3.2: 120-ball LFBGA Package Dimensions

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 Package Information

3.4 PCB Design and Assembly Considerations

This section lists recommendations to achieve maximum board-level reliability of the 7 x 7 x 1.3mm LFBGA 120-ball
package:
■ NSMD lands, i.e. lands smaller than the solder mask aperture, are preferred because of the greater
accuracy of the metal definition process compared to the solder mask process. With solder mask defined
pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which
can cause stress concentration and act as a point for crack initiation.
■ Ideally, via-in-pad technology should be used to achieve truly NSMD lands. Where this is not possible, a
maximum of one trace connected to each land is preferred and this trace should be as thin as possible –
taking into consideration its current carrying and the RF requirements.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ 35µm thick (1oz) copper lands are recommended rather than 17µm thick (0.5oz). This results in a greater
standoff which has been proven to provide greater reliability during thermal cycling.
■ Land diameter should be the same as that on the package to achieve optimum reliability.
■ Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder
in the joint, increasing its reliability.
■ Where a nickel gold plating finish is used, the gold thickness should be kept below 0.5µm to prevent brittle
gold/tin intermetallics forming in the solder.

3.5 Typical Solder Reflow Profile

See Typical Solder Reflow Profile for Lead-free Devices for information.

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 Bluetooth Modem

4 Bluetooth Modem
4.1 RF Ports
4.1.1 RF_N and RF_P
RF_N and RF_P form a complementary balanced pair and are available for both transmit and receive. On transmit
their outputs are combined using an external balun into the single-ended output required for the antenna. Similarly,
on receive their input signals are combined internally.
Both terminals present similar complex impedances that may require matching networks between them and the
balun. Viewed from the chip, the outputs can each be modelled as an ideal current source in parallel with a lossy

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

capacitor. An equivalent series inductance can represent the package parasitics.

_
PA RF_N
+ RF Switch

RF_P
RF Switch

+
LNA_

G-TW-0003349.2.2

Figure 4.1: Simplified Circuit RF_N and RF_P

RF_N and RF_P require an external DC bias. The DC level must be set at VDD_RADIO.

4.2 RF Receiver
The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and
W‑CDMA cellular phone transmitters without being desensitised. The use of a digital FSK discriminator means that
no discriminator tank is needed and its excellent performance in the presence of noise allows
BlueCore5‑Multimedia Flash (16Mb) to exceed the Bluetooth requirements for co-channel and adjacent channel
rejection.
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed
to the EDR modem.

4.2.1 Low Noise Amplifier

The LNA operates in differential mode and takes its input from the shared RF port.

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 Bluetooth Modem

4.2.2 RSSI Analogue to Digital Converter

The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.

4.3 RF Transmitter
4.3.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

4.3.2 Power Amplifier
The internal PA has a maximum output power that allows BlueCore5‑Multimedia Flash (16Mb) to be used in Class
2 and Class 3 radios without an external RF PA.

4.3.3 Transmit RF Power Control for Class 1 Applications (TX_PWR)

An 8-bit voltage DAC, AUX_DAC, controls the amplification level of the external PA for Class 1 operation. The
DAC output is derived from the on-chip band gap and is virtually independent of temperature and supply voltage.
Equation 4.1 and Equation 4.2 show the the output voltage:

VDAC = MIN (( 3.7V × EXT_PA_GAIN

255
− 0.008 × I ), PIOSupply − 0.008 × I )
Equation 4.1: Output Voltage with Load Current I
or

VDAC = MIN (( 3.7V × EXT_PA_GAIN

255 ), PIOSupply )
Equation 4.2: Output Voltage with No Load Current
Note:

PIOSupply = VDD_PIO
BlueCore5‑Multimedia Flash (16Mb) enables the external PA only when transmitting. Before transmitting, the chip
normally ramps up the power to the internal PA, then it ramps it down again afterwards. However, if a suitable external
PA is used, it may be possible to ramp the power externally by driving the TX_PWR pin on the PA from AUX_DAC.

TX Power

tcarrier
G-TW-0000185.3.3

Modulation

Figure 4.2: Internal Power Ramping

The PS Key PSKEY_TX_GAINRAMP, is used to control the delay, in units of μs, between the end of the transmit
power ramp and the start of modulation.
PS Key TXRX_PIO_CONTROL controls external RF components such as a switch, an external PA or an external
LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this purpose, as Table 4.1 shows.

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 Bluetooth Modem

TXRX_PIO_CONTROL Value PIO and AUX_DAC Use

PIO[0], PIO[1] and AUX_DAC not used to control RF. Power ramping is
0
internal.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC not used.
1
Power ramping is internal.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
2
gain of external PA. Power ramping is external.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

PIO[0] is low during RX, PIO[1] is low during TX. AUX_DAC used to set gain
3
of external PA. Power ramping is external.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
4
gain of external PA. Power ramping is internal.

Table 4.1: TXRX_PIO_CONTROL Values

4.4 Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening
can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time
across the guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification.

4.5 Baseband
4.5.1 Burst Mode Controller
During transmission the BMC constructs a packet from header information previously loaded into memory-mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,
the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer
in RAM. This architecture minimises the intervention required by the processor during transmission and reception.

4.5.2 Physical Layer Hardware Engine

Dedicated logic performs the following:
■ Forward error correction
■ Header error control
■ Cyclic redundancy check
■ Encryption
■ Data whitening
■ Access code correlation
■ Audio transcoding
Firmware performs the following voice data translations and operations:
■ A-law/µ-law/linear voice data (from host)
■ A-law/µ-law/CVSD (over the air)
■ Voice interpolation for lost packets
■ Rate mismatch correction
The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR specification including AFH
and eSCO.

4.6 Basic Rate Modem

The basic rate modem satisfies the basic data rate requirements of the Bluetooth v2.1 + EDR specification. The
basic rate was the standard data rate available on the Bluetooth v1.2 specification and below, it is based on
GFSK modulation scheme.
Including the basic rate modem allows BlueCore5‑Multimedia Flash (16Mb) compatibility with earlier Bluetooth
products.

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 Bluetooth Modem

The basic rate modem uses the RF ports, receiver, transmitter and synthesiser, alongside the baseband components
described in Section 4.5.

4.7 Enhanced Data Rate Modem

The EDR modem satisfies the requirements of the Bluetooth v2.1 + EDR specification. EDR has been introduced
to provide 2x and 3x data rates with minimal disruption to higher layers of the Bluetooth stack.
BlueCore5‑Multimedia Flash (16Mb) supports both the basic and enhanced data rates and is compliant with the
Bluetooth v2.1 + EDR specification.
At the baseband level, EDR uses the same 1.6kHz slot rate and the 1MHz symbol rate defined for the basic data
rate. EDR differs in that each symbol in the payload portion of a packet represents 2 or 3 bits. This is achieved using
2 new distinct modulation schemes. Table 4.2 and Figure 4.3 summarise these. Link Establishment and Management

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

are unchanged and still use GFSK for both the header and payload portions of these packets.
The enhanced data rate modem uses the RF ports, receiver, transmitter and synthesiser, with the baseband
components described in Section 4.5.

Data Rate Scheme Bits Per Symbol Modulation

Basic Rate 1 GFSK

EDR 2 π/4 DQPSK

EDR 3 8DPSK (optional)

Table 4.2: Data Rate Schemes

Basic Rate
Access Code Header Payload

Enhanced Data Rate

G-TW-0000244.2.3
Access Code Header Guard Sync Payload Trailer

/4 DQPSK or 8DPSK

Figure 4.3: BDR and EDR Packet Structure

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 Clock Generation

5 Clock Generation
BlueCore5‑Multimedia Flash (16Mb) requires a Bluetooth reference clock frequency of 12MHz to 52MHz from either
an externally connected crystal or from an external TCXO source.
All BlueCore5‑Multimedia Flash (16Mb) internal digital clocks are generated using a phase locked loop, which is
locked to the frequency of either the external 12MHz to 52MHz reference clock source or an internally generated
watchdog clock frequency of 1kHz.
The Bluetooth operation determines the use of the watchdog clock in low-power modes.

5.1 Clock Architecture

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Bluetooth
Reference Clock
Radio

G-TW-0000189.3.3
Auxiliary Digital
PLL Circuitry

Figure 5.1: Clock Architecture

5.2 Input Frequencies and PS Key Settings

BlueCore5‑Multimedia Flash (16Mb) should be configured to operate with the chosen reference frequency. Do this
by setting the PS Key PSKEY_ANA_FREQ for all frequencies with an integer multiple of 250kHz. The input frequency
default setting in BlueCore5‑Multimedia Flash (16Mb) is 26MHz depending on the software build. Full details are in
the software release note for the specific build from www.csrsupport.com.
The following CDMA/3G phone TCXO frequencies are also catered for: 14.40, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68,
19.8 and 38.4MHz. The value of the PS Key is a multiple of 1kHz, so 38.4MHz is selected by using a PS Key value
of 38400.

Reference Crystal Frequency (MHz) PSKEY_ANA_FREQ (kHz)

14.40 14400

15.36 15360

16.20 16200

16.80 16800

19.20 19200

19.44 19440

19.68 19680

19.80 19800

38.40 38400

n x 0.25 n x 250

26.00 (default) 26000

Table 5.1: PS Key Values for CDMA/3G Phone TCXO

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 Clock Generation

5.3 External Reference Clock

5.3.1 Input: XTAL_IN
The external reference clock is applied to the BlueCore5‑Multimedia Flash (16Mb) XTAL_IN input.
BlueCore5‑Multimedia Flash (16Mb) is configured to accept the external reference clock at XTAL_IN by connecting
XTAL_OUT to ground.
The external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled to XTAL_IN
without the need for additional components. A digital level reference clock gives superior noise immunity, as the high
slew rate clock edges have lower voltage to phase conversion. If peaks of the reference clock are either below
VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor (approximately 33pF) connected
to XTAL_IN.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

The external reference clock signal should meet the specifications in Table 5.2.

Min Typ Max Unit

Frequency(a) 12 26 52 MHz

Duty cycle 20:80 50:50 80:20 -

Edge jitter (at zero crossing) - - 15 ps rms

AC coupled sinusoid 0.4 - VDD_ANA(b) V pk-pk

VIL - VSS_ANA(c) - V
Signal level
DC coupled
digital VDD_ANA(b)
VIH - (c) - V

Table 5.2: External Clock Specifications

(a) The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
(b) VDD_ANA is 1.50V nominal
(c) If driven via a DC blocking capacitor max amplitude is reduced to 750mV pk-pk for non 50:50 duty cycle

5.3.2 XTAL_IN Impedance in External Mode

The impedance of XTAL_IN does not change significantly between operating modes, typically 10fF. When
transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason CSR
recommends that a buffered clock input is used.

5.3.3 Clock Start-up Delay

BlueCore5‑Multimedia Flash (16Mb) hardware incorporates an automatic 5ms delay after the assertion of the system
clock request signal before running firmware, see Figure 5.2. This is suitable for most applications using an external
clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable
after this period. Under these conditions, BlueCore5‑Multimedia Flash (16Mb) firmware provides a software function
that extends the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value
is set in milliseconds from 1ms to 31ms. Zero is the default entry for 5ms delay.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueCore5‑Multimedia Flash (16Mb) as low as possible.
BlueCore5‑Multimedia Flash (16Mb) consumes about 2mA of current for the duration of
PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.

5.3.4 Clock Timing Accuracy

As Figure 5.2 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins
to run. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth v2.1 +
EDR specification. Radio activity may occur after 6ms after the firmware starts. Therefore, at this point the timing
accuracy of the external clock source must be within ±20ppm.

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 Clock Generation

CLK_REQ

Firmware Activity PSKEY_CLOCK_STARTUP_DELAY

Firmware Activity

Clock Accuracy 1000ppm 250ppm 20ppm

G-TW-0000190.3.2
ms After Firmware 0 2 6

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Radio Activity

Figure 5.2: TCXO Clock Accuracy

5.4 Crystal Oscillator: XTAL_IN and XTAL_OUT

BlueCore5‑Multimedia Flash (16Mb) contains a crystal driver circuit. This operates with an external crystal and
capacitors to form a Pierce oscillator. Figure 5.3 shows the external crystal is connected to pins XTAL_IN,
XTAL_OUT.

gm
-

C trim Cint
XTAL_OUT
XTAL_IN

G-TW-0000191.4.2
Ct2 C t1

Figure 5.3: Crystal Driver Circuit

Figure 5.4 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.

Cm Lm Rm
G-TW-0000245.4.4

CO

Figure 5.4: Crystal Equivalent Circuit

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 Clock Generation

The resonant frequency may be trimmed with the crystal load capacitance. BlueCore5‑Multimedia Flash (16Mb)
contains variable internal capacitors to provide a fine trim.

Parameter Min Typ Max Unit

Frequency 16 26 26 MHz

Initial Tolerance - ±25 - ppm

Pullability - ±20 - ppm/pF

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Table 5.3: Crystal Specification
The BlueCore5‑Multimedia Flash (16Mb) driver circuit is a transconductance amplifier. A voltage at XTAL_IN
generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum
performance.

5.4.1 Load Capacitance

For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals.
BlueCore5‑Multimedia Flash (16Mb) provides some of this load with the capacitors Ctrim and Cint. The remainder
should be from the external capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise
performance. This maximises the signal swing and slew rate at XTAL_IN (to which all on-chip clocks are referred).
Crystal load capacitance, Cl is calculated using Equation 5.1:

(Ct2 + Ctrim) Ct1

Cl = Cint +
Ct2 + Ctrim + Ct1

Equation 5.1: Load Capacitance

Note:

Ctrim = 3.4pF nominal (mid-range setting)

Cint = 1.5pF

Cint does not include the crystal internal self capacitance; it is the driver self capacitance.

5.4.2 Frequency Trim

BlueCore5‑Multimedia Flash (16Mb) enables frequency adjustments to be made. This feature is typically used to
remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the
crystal load capacitance with an on-chip trim capacitor, Ctrim. The value of Ctrim is set by a 6-bit word in
PSKEY_ANA_FTRIM. Its value is calculated as follows:
Ctrim = 125fF × PSKEY_ANA_FTRIM

Equation 5.2: Trim Capacitance

The Ctrim capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the
combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which
varies in steps of typically 125fF for each least significant bit increment of PSKEY_ANA_FTRIM.
Equation 5.3 describes the frequency trim.

( )
Δ(Fx) Ct1
= pullability × 0.110 × (ppm/LSB)
Fx Ct1 + Ct2 + Ctrim

Equation 5.3: Frequency Trim

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 Clock Generation

Note:

Fx = crystal frequency

Pullability is a crystal parameter with units of ppm/pF

Total trim range is 0 to 63
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 5.4.
∂ (FX ) FX Cm
= •
∂ (CI ) 2(CI + C0 )2

Equation 5.4: Pullability

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Note:

C0 = Crystal self capacitance (shunt capacitance)

Cm = Crystal motional capacitance (series branch capacitance in crystal model), see Figure 5.4

It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to
pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with
ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is
required.

5.4.3 Transconductance Driver Model

The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to
one terminal generates a voltage at the other. The transconductance amplifier in BlueCore5‑Multimedia Flash
(16Mb) uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit
oscillates if the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude,
the product should be greater than three. The transconductance required for oscillation is defined by the relationship
shown in Equation 5.5.

(2πFx)2 Rm ((C0 + Cint)(Ct1 + Ct2 + Ctrim) + Ct1 (Ct2 + Ctrim))

gm > 3
Ct1 (Ct2 + Ctrim)

Equation 5.5: Transconductance Required for Oscillation

BlueCore5‑Multimedia Flash (16Mb) guarantees a transconductance value of at least 2mA/V at maximum drive level.
Note:

More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher
capacitance loading
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is
determined by the crystal driver transconductance.

5.4.4 Negative Resistance Model

An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The
driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the
negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the
BlueCore5‑Multimedia Flash (16Mb) crystal driver circuit is based on a transimpedance amplifier, it is possible to
calculate an equivalent negative resistance for it using the formula in Equation 5.6.
Ct1(Ct2 + Ctrim)
Rneg >
gm(2πFx)2(C0 + Cint)((Ct1 + Ct2 + Ctrim) + Ct1(Ct2 + Ctrim))2

Equation 5.6: Equivalent Negative Resistance

Equation 5.6 shows the negative resistance of the BlueCore5‑Multimedia Flash (16Mb) driver as a function of its
drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series
with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the
oscillator.

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 Clock Generation

5.4.5 Crystal PS Key Settings

The BlueCore5‑Multimedia Flash (16Mb) firmware automatically controls the drive level on the crystal circuit to
achieve optimum input swing. PSKEY_XTAL_TARGET_AMPLITUDE is used by the firmware to servo the required
amplitude of crystal oscillation. Refer to the software build release note for a detailed description.
Configure the BlueCore5‑Multimedia Flash (16Mb) to operate with the chosen reference frequency.

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 Bluetooth Stack Microcontroller

6 Bluetooth Stack Microcontroller

A 16-bit RISC MCU is used for low power consumption and efficient use of memory.
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and
host interfaces.

6.1 TCXO Enable OR Function

An OR function exists for clock enable signals from a host controller and BlueCore5‑Multimedia Flash (16Mb) where
either device can turn on the clock without having to wake up the other device, see Figure 6.1. PIO[3] can be used
as the host clock enable input and PIO[2] can be used as the OR output with the TCXO enable signal from

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

BlueCore5‑Multimedia Flash (16Mb).
Note:

To turn on the clock, the clock enable signal on PIO[3] must be high.

VDD
GSM System
TCXO
CLK IN

CLK REQ OUT

Enable

BlueCore System
CLK REQ IN / PIO [3]

CLK REQ OUT / PIO [2]

G-TW-0000196.3.3
CLK IN

Figure 6.1: Example TCXO Enable OR Function

On reset and up to the time the PIO has been configured, PIO[2] is tristate. Therefore, the developer must ensure
that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that
the TCXO is oscillating at start up.

6.2 Programmable I/O Ports, PIO and AIO

18 lines of programmable bidirectional I/O are provided.
Note:

PIO[15:4] are powered from VDD_PADS and PIO[3:0] are powered from VDD_PIO. AIO[1:0] are powered from
VDD_ANA.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. Using
PSKEY_CLOCK_REQUEST_ENABLE, this terminal can be configured to be low when BlueCore5‑Multimedia Flash
(16Mb) is in deep sleep and high when a clock is required.

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 Bluetooth Stack Microcontroller

Note:

CSR cannot guarantee that the PIO assignments remain as described. Refer to the relevant software release
note for the implementation of these PIO lines, as they are firmware build-specific.
BlueCore5‑Multimedia Flash (16Mb) has 2 general-purpose analogue interface pins, AIO[1:0], used to access
internal circuitry and control signals. Auxiliary functions available on the analogue interface include a 10-bit ADC
and a 8-bit DAC. Signals selectable on this interface include the band gap reference voltage and a variety of clock
signals: 64, 48, 32, 24, 16, 12, 8, 6 and 2MHz (outputted from AIO[0] only) and the XTAL and XTAL/2 clock frequency
(outputted from AIO[0] and AIO[1]). When used with analogue signals the voltage range is constrained by the
analogue supply voltage. When configured to drive out digital level signals (clocks) generated from within the
analogue part of the device, the output voltage level is determined by VDD_ANA.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

6.3 WLAN Coexistence Interface
Dedicated hardware is provided to implement a variety of WLAN coexistence schemes. Channel skipping AFH,
priority signalling, channel signalling and host passing of channel instructions are all supported. The features are
configured in firmware.
For more information see Bluetooth and IEEE 802.11 b/g Co-existence Solutions Overview.

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 Kalimba DSP

7 Kalimba DSP
The Kalimba DSP is an open platform Kalimba DSP allowing signal processing functions to be performed on over-
air data or codec data in order to enhance audio applications. Figure 7.1 shows the Kalimba DSP interfaces to other
functional blocks within BlueCore5‑Multimedia Flash (16Mb).

Kalimba DSP Core

MCU Register Interface (including Debug)

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Memory
Management Unit
DSP MMU Port
Data Memory Address
Interface Generators

Registers
Instruction Decode ALU
DSP, MCU and Memory Window Control
Program Flow DEBUG

Clock Select PIO

PIO In/Out
DSP Program Control

Programmable Clock = 64MHz Internal Control Registers

IRQ to Subsystem

MMU Interface

Interrupt Controller
IRQ from Subsystem

Timer 1µs Timer Clock

DSP RAMs MCU Window

Flash Window
DM2 DSP Data Memory 2 Interface (DM2)

DM1 DSP Data Memory 1 Interface (DM1)

G-TW-0001399.6.2
PM DSP Program Memory Interface (PM)

Figure 7.1: Kalimba DSP Interface to Internal Functions

The key features of the DSP include:
■ 64MIPS performance, 24-bit fixed point DSP core
■ Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate
■ 32-bit instruction word
■ Separate program memory and dual data memory, allowing an ALU operation and up to two memory
accesses in a single cycle
■ Zero overhead looping
■ Zero overhead circular buffer indexing
■ Single cycle barrel shifter with up to 56-bit input and 24-bit output
■ Multiple cycle divide (performed in the background)
■ Bit reversed addressing
■ Orthogonal instruction set
■ Low overhead interrupt

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 Memory Interface and Management

8 Memory Interface and Management

8.1 Memory Management Unit
The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the
host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and
is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.

8.2 System RAM

48KB of on-chip RAM supports the RISC MCU and is shared between the ring buffers used to hold voice/data for
each active connection and the general-purpose memory required by the Bluetooth stack.

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8.3 Kalimba DSP RAM
Additional on-chip RAM is provided to support the Kalimba DSP:
■ 16K x 24-bit for data memory 1 (DM1)
■ 12K x 24-bit for data memory 2 (DM2)
■ 6K x 32-bit for program memory (PM)
Note:

The Kalimba DSP can also execute directly from internal flash, using a 64-instruction on-chip cache.

8.4 Internal Flash Memory (16Mb)

16Mb of internal flash memory is available on the BlueCore5‑Multimedia Flash (16Mb). The internal flash memory
is provided for system firmware and the Kalimba DSP coprocessor code implementation.
The internal flash memory provides 16Mb of internal code and data storage. This storage is used to store
BlueCore5‑Multimedia Flash (16Mb) settings and program code, and Kalimba DSP coprocessor code and data.

8.4.1 Flash Specification

The flash device used with BlueCore5‑Multimedia Flash (16Mb) meets the following criteria:

Parameter Value

Data width 16-bit

Capacity 16Mb

Access time 70ns

Table 8.1: Internal Flash Device Specifications

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 Serial Interfaces

9 Serial Interfaces
9.1 UART Interface
BlueCore5‑Multimedia Flash (16Mb) has a standard UART serial interface that provides a simple mechanism for
communicating with other serial devices using the RS232 protocol.

UART_TX

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UART_RX

UART_RTS

G-TW-0000198.2.3
UART_CTS

Figure 9.1: Universal Asynchronous Receiver

Figure 9.1 shows the 4 signals that implement the UART function. When BlueCore5‑Multimedia Flash (16Mb) is
connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. The remaining
2 signals, UART_CTS and UART_RTS, can implement RS232 hardware flow control where both are active low
indicators.
UART configuration parameters, such as baud rate and packet format, are set using BlueCore5‑Multimedia Flash
(16Mb) firmware.
Note:

To communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter
card is required for the PC.

Parameter Possible Values

1200 baud (≤2%Error)

Baud rate Minimum
9600 baud (≤1%Error)

Maximum 4Mbaud (≤1%Error)

Flow control RTS/CTS or None

Parity None, Odd or Even

Number of stop bits 1 or 2

Bits per byte 8

Table 9.1: Possible UART Settings

The UART interface can reset BlueCore5‑Multimedia Flash (16Mb) on reception of a break signal. A break is
identified by a continuous logic low (0V) on the UART_RX terminal, as Figure 9.2 shows. If tBRK is longer than the
value, defined by PSKEY_HOSTIO_UART_RESET_TIMEOUT, a reset occurs. This feature allows a host to initialise
the system to a known state. Also, BlueCore5‑Multimedia Flash (16Mb) can emit a break character that may be used
to wake the host.

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 Serial Interfaces

tBRK
UART_TX

G-TW-0000250.3.2

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Figure 9.2: Break Signal
Note:

The DFU boot loader must be loaded into the flash device before the UART or USB interfaces can be used.
This initial flash programming can be done via the SPI.
Table 9.2 shows a list of commonly used baud rates and their associated values for the PSKEY_UART_BAUDRATE.
There is no requirement to use these standard values. Any baud rate within the supported range can be set in the
PS Key according to the formula in Equation 9.1.
PSKEY_UART_BAUDRATE
Baud Rate =
0.004096
Equation 9.1: Baud Rate

Persistent Store Value

Baud Rate Error
Hex Dec

1200 0x0005 5 1.73%

2400 0x000a 10 1.73%

4800 0x0014 20 1.73%

9600 0x0027 39 -0.82%

19200 0x004f 79 0.45%

38400 0x009d 157 -0.18%

57600 0x00ec 236 0.03%

76800 0x013b 315 0.14%

115200 0x01d8 472 0.03%

230400 0x03b0 944 0.03%

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 Serial Interfaces

Persistent Store Value

Baud Rate Error
Hex Dec

460800 0x075f 1887 -0.02%

921600 0x0ebf 3775 0.00%

1382400 0x161e 5662 -0.01%

1843200 0x1d7e 7550 0.00%

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

2764800 0x2c3d 11325 0.00%

3686400 0x3afb 15099 0.00%

Table 9.2: Standard Baud Rates

9.1.1 UART Configuration While Reset is Active

The UART interface is tristate while BlueCore5‑Multimedia Flash (16Mb) is being held in reset. This allows the user
to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tristate when BlueCore5‑Multimedia Flash (16Mb) reset is de-asserted and the firmware begins to run.

9.1.2 UART Bypass Mode

Host Processor UART Bypass Another Device

RST#
UART_TX PIO4
4
RXD TX
UART_RTS PIO5
CTS RTS
UART_CTS PIO6
RTS CTS
UART_RX PIO7
TXD RX

UART

G-TW-0000201.3.3
Test Interface

Figure 9.3: UART Bypass Architecture

Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on BlueCore5‑Multimedia Flash
(16Mb) can be used. The default state of BlueCore5‑Multimedia Flash (16Mb) after reset is de-asserted; this is for
the host UART bus to be connected to the BlueCore5‑Multimedia Flash (16Mb) UART, thereby allowing
communication to BlueCore5‑Multimedia Flash (16Mb) via the UART. All UART bypass mode connections are
implemented using CMOS technology and have signalling levels of 0V and VDD_PADS.
To apply the UART bypass mode, a BCCMD command is issued to BlueCore5‑Multimedia Flash (16Mb). Upon this
issue, it switches the bypass to PIO[7:4] as Figure 9.3 shows. When the bypass mode has been invoked,
BlueCore5‑Multimedia Flash (16Mb) enters the deep sleep state indefinitely.
To re-establish communication with BlueCore5‑Multimedia Flash (16Mb), the chip must be reset so that the default
configuration takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is
invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
Note:

When in bypass mode, the UART signal levels on the PIO are at VDD_PADS level and when not bypassed, i.e.
when using the normal UART pins, the levels are at VDD_USB levels.

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 Serial Interfaces

9.1.3 Current Consumption in UART Bypass Mode

The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby
mode.

9.2 USB Interface

BlueCore5‑Multimedia Flash (16Mb) has a full-speed (12Mbps) USB interface for communicating with other
compatible digital devices. The USB interface on the BlueCore5‑Multimedia Flash (16Mb) acts as a USB peripheral,
responding to requests from a master host controller.
BlueCore5‑Multimedia Flash (16Mb) supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0
Specification), available from http://www.usb.org. For more information on how to integrate the USB interface on

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

BlueCore5‑Multimedia Flash (16Mb) see the Bluetooth and USB Design Considerations Application Note.
As well as describing USB basics and architecture, the application note describes:
■ Power distribution for high and low bus-powered configurations
■ Power distribution for self-powered configuration, which includes USB VBUS monitoring
■ USB enumeration
■ Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of
ferrite beads
■ USB suspend modes and Bluetooth low-power modes:
■ Global suspend
■ Selective suspend, includes remote wake
■ Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
■ Suspend mode current draw
■ PIO status in suspend mode
■ Resume, detach and wake PIOs
■ Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend
modes and USB VBUS voltage consideration
■ USB termination when interface is not in use
■ Internal modules, certification and non-specification compliant operation

9.3 Programming and Debug Interface

Important Note:

The SPI is used to program and configure (PS Keys), and debug the BlueCore5‑Multimedia Flash (16Mb). It is
required in production. Ensure the 4 SPI signals are brought out to either test points or a header.
CSR provides development and production tools to communicate over the SPI from a PC, although a level
translator circuit is often required. All are available from CSR.
BlueCore5‑Multimedia Flash (16Mb) uses a 16-bit data and 16-bit address programming and debug interface.
Transactions can occur when the internal processor is running or is stopped.
Data may be written or read one word at a time, or the auto-increment feature is available for block access.

9.3.1 Instruction Cycle

The BlueCore5‑Multimedia Flash (16Mb) is the slave and receives commands on SPI_MOSI and outputs data on
SPI_MISO. Table 9.3 shows the instruction cycle for a SPI transaction.

1 Reset the SPI interface Hold SPI_CS# high for two SPI_CLK cycles

2 Write the command word Take SPI_CS# low and clock in the 8-bit command

3 Write the address Clock in the 16-bit address word

4 Write or read data words Clock in or out 16-bit data word(s)

5 Termination Take SPI_CS# high

Table 9.3: Instruction Cycle for a SPI Transaction

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 Serial Interfaces

With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueCore5‑Multimedia Flash (16Mb) on the rising edge of the clock line SPI_CLK. When reading,
BlueCore5‑Multimedia Flash (16Mb) replies to the master on SPI_MISO with the data changing on the falling edge
of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this
BlueCore5‑Multimedia Flash (16Mb) offers increased data transfer efficiency via an auto increment operation. To
invoke auto increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock
cycles for each extra word to be written or read.

9.3.2 Multi-slave Operation

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

BlueCore5‑Multimedia Flash (16Mb) should not be connected in a multi-slave arrangement by simple parallel
connection of slave MISO lines. When BlueCore5‑Multimedia Flash (16Mb) is deselected (SPI_CS# = 1), the
SPI_MISO line does not float. Instead, BlueCore5‑Multimedia Flash (16Mb) outputs 0 if the processor is running or
1 if it is stopped.

9.4 I²C Interface

9.4.1 Software I²C Interface
PIO[8:6] can be used to form a master I²C interface. The interface is formed using software to drive these lines.
Therefore it is suited only to relatively slow functions such as driving a dot matrix LCD, keyboard scanner or
EEPROM.

EEPROM Supply

Decoupling
Capacitor

8 VCC A0 1

G-TW-0000207.5.3
7 2
PIO[8] WP A1
6 3
PIO[6] SCL A2
5 4
PIO[7] SDA GND
Serial EEPROM
(24AA32)

Figure 9.4: Example EEPROM Connection

9.4.2 Bit-serialiser Interface

In addition to the software I²C interface outlined in Section 9.4.1, the BlueCore5‑Multimedia Flash (16Mb) includes
a configurable hardware bit-serialiser interface. Any 3 PIOs can be used as a serial master interface by configuring
the hardware bit-serialiser. In the I²C master mode, the hardware bit-serialiser supports address, direction and
ACK handling, but does not support multi-master I²C bus systems. I²C slave mode is also not supported.
Note:

The I²C interface can be directly controlled by the MCU or the Kalimba DSP.
Suitable firmware is required to support the hardware bit-serialiser interface.
I²C and SPI are supported.

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 Audio Interface

10 Audio Interface
The audio interface circuit consists of:
■ Stereo audio codec
■ Dual audio inputs and outputs
■ A configurable PCM, I²S or SPDIF interface
Figure 10.1 shows the functional blocks of the interface. The codec supports stereo playback and recording of audio
signals at multiple sample rates with a resolution of 16-bit. The ADC and the DAC of the codec each contain 2
independent channels. Any ADC or DAC channel can be run at its own independent sample rate.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Stereo Codec

PCM PCM Interface

Digital
MMU Voice Port Voice Port
Audio
Memory
Management
Unit

G-TW-0000252.3.2
Left DAC
Stereo Right DAC
Audio
MCU Register Registers Codec Left ADC
Interface Driver Right ADC

Figure 10.1: Audio Interface

The interface for the digital audio bus shares the same pins as the PCM codec interface described in Section 10.3
which means each of the audio buses are mutually exclusive in their usage. Table 10.1 lists these alternative
functions.

PCM Interface SPDIF Interface I²S Interface

PCM_OUT SPDIF_OUT SD_OUT

PCM_IN SPDIF_IN SD_IN

PCM_SYNC - WS

PCM_CLK - SCK

Table 10.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface

10.1 Audio Input and Output

The audio input circuitry consists:
■ 2 independent channels programmed for either microphone or line input
■ Each channel is independently configurable to be either single-ended or fully differential
■ Each channel has an analogue and digital programmable gain stage for optimisation of different
microphones
The audio output circuitry consists of a dual differential class A-B output stage.

10.2 Stereo Audio Codec Interface

The main features of the interface are:
■ Stereo and mono analogue input for voice band and audio band
■ Stereo and mono analogue output for voice band and audio band
■ Support for stereo digital audio bus standards such as I²S
■ Support for IEC-60958 standard stereo digital audio bus standards, e.g. SPDIF and AES3/EBU
■ Support for PCM interfaces including PCM master codecs that require an external system clock

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Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right
channel for audio input and output. With respect to software and any registers, channel 0 or channel A represents
the left channel and channel 1 or channel B represents the right channel for both input and output.

10.2.1 Stereo Audio Codec Block Diagram

MIC_A_P
Input
Amplifier ∑∆ - ADC

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

MIC_A_N

LP Filter

SPKR_A_P
Output
Amplifier ∑∆ - DAC
SPKR_A_N

Digital
Circuitry

MIC_B_P
Input
Amplifier ∑∆ - ADC
MIC_B_N

LP Filter

G-TW-0000209.2.2
SPKR_B_P
Output
Amplifier ∑∆ - DAC
SPKR_B_N

Figure 10.2: Stereo Codec Audio Input and Output Stages

The stereo audio codec uses a fully differential architecture in the analogue signal path, which results in low noise-
sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a single
power-supply of 1.5V and uses a minimum of external components.

10.2.2 Stereo Codec Set-up

The configuration and control of the ADC is through VM functions described in appropriate SDK documentation. This
section is an overview of the parameters that can be set up using the VM functions.
The Kalimba DSP can communicate its codec requirements to the MCU, and therefore also to the VM, by exchange
of messages. The messages used between the Kalimba DSP and the embedded MCU are based on interrupts:
■ 1 interrupt between the MCU and Kalimba DSP
■ 1 interrupt between the Kalimba DSP and the MCU
Message content is transmitted using shared memory. There are VM and DSP library functions to send and receive
messages; refer to appropriate SDK documentation for further details.

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10.2.3 ADC
The ADC consists of:
■ 2 second-order Sigma-Delta converters allowing 2 separate channels that are identical in functionality, as
Figure 10.2 shows.
■ 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

10.2.4 ADC Sample Rate Selection

Each ADC supports the following sample rates:
■ 8kHz
■ 11.025kHz

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ 16kHz
■ 22.050kHz
■ 24kHz
■ 32kHz
■ 44.1kHz

10.2.5 ADC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain
settings summarised in Table 10.2. There is also a high resolution digital gain mode that allows the gain to be
changed in 1/32dB steps. Contact CSR for more information.

ADC Digital Gain Setting ADC Digital Gain Setting

Gain Selection Value Gain Selection Value
(dB) (dB)

0 0 8 -24

1 3.5 9 -20.5

2 6 10 -18

3 9.5 11 -14.5

4 12 12 -12

5 15.5 13 -8.5

6 18 14 -6

7 21.5 15 -2.5

Table 10.2: ADC Digital Gain Rate Selection

10.2.6 ADC Analogue Gain

Figure 10.3 shows the equivalent block diagram for the ADC analogue amplifier. It is a two-stage amplifier:
■ The first stage amplifier has a 24dB gain for the microphone.
■ The second stage has a programmable gain with 7 individual 3dB steps. By combining the 24dB gain
selection of the microphone input with the 7 individual 3dB gain steps, the overall range of the analogue
amplifier is approximately -3dB to 42dB in 3dB steps. The VM function controls all the gain control of the
ADC.

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Bypass or 24dB gain

-3dB to 18dB gain

P P
N N

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G-TW-0001400.4.2
Line Mode / Mic Mode Gain 0:7

Switches shown for line mode

Microphone mode input impedance = 6kΩ
Line mode input impedance = 6kΩ to 30kΩ

Figure 10.3: ADC Analogue Amplifier Block Diagram

10.2.7 DAC
The DAC consists of:
■ 2 second-order Sigma-Delta converters allowing 2 separate channels that are identical in functionality, as
Figure 10.2 shows.
■ 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

10.2.8 DAC Sample Rate Selection

Each DAC supports the following samples rates:
■ 8kHz
■ 11.025kHz
■ 12kHz
■ 16kHz
■ 22.050kHz
■ 24kHz
■ 32kHz
■ 44.1kHz
■ 48kHz

10.2.9 DAC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings,
summarised in Table 10.3. There is also a high resolution digital gain mode that allows the gain to be changed in
1/32dB steps. Contact CSR for more information.
The overall gain control of the DAC is controlled by VM function. Its setting is a combined function of the digital and
analogue amplifier settings.

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Digital Gain Selection DAC Digital Gain Setting Digital Gain Selection DAC Digital Gain Setting
Value (dB) Value (dB)

0 0 8 -24

1 3.5 9 -20.5

2 6 10 -18

3 9.5 11 -14.5

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4 12 12 -12

5 15.5 13 -8.5

6 18 14 -6

7 21.5 15 -2.5

Table 10.3: DAC Digital Gain Rate Selection

10.2.10 DAC Analogue Gain

As Table 10.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB
steps.
The VM function controls the overall gain control of the DAC. Its setting is a combined function of the digital and
analogue amplifier settings.

Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain
Value Setting (dB) Value Setting (dB)

7 3 3 -9

6 0 2 -12

5 -3 1 -15

4 -6 0 -18

Table 10.4: DAC Analogue Gain Rate Selection

10.2.11 Microphone Input

Figure 10.4 shows recommended biasing for each microphone. The microphone bias, MIC_BIAS, derives its power
from the BAT_P and requires a 1µF capacitor on its output.

Microphone Bias

R2
C1 MIC_A_P
C3
Input
R1 Amplifier
C2 MIC_A_N
G-TW-0000213.3.2

C4
+ MIC1

Figure 10.4: Microphone Biasing

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Note:

Figure 10.4 shows a single channel only.

The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS
maintains regulation within the limits 0.200mA to 1.230mA. If the microphone sits below these limits, then the
microphone output must be pre-loaded with a large value resistor to ground.
The audio input is intended for use in the range from 1μA at 94dB SPL to about 10μA at 94dB SPL. With biasing
resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV.
The input impedance at MIC_A_N, MIC_A_P, MIC_B_N and MIC_B_P is typically 6.0kΩ.
C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

R1 sets the microphone load impedance and is normally in the range of 1kΩ to 2kΩ.
R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be
selected as required. R2 may be connected to a convenient supply, in which case the bias network is permanently
enabled, or to the MIC_BIAS output (which is ground referenced and provides good rejection of the supply), which
may be configured to provide bias only when the microphone is required.
Table 10.5 shows the 4-bit programmable output voltage that the microphone bias provides, and Table 10.6 shows
the 4-bit programmable output current.
The characteristics of the microphone bias include:
■ Power supply:
■ BlueCore5‑Multimedia Flash (16Mb) microphone supply is BAT_P
■ Minimum input voltage = Output voltage + drop-out voltage
■ Maximum input voltage is 4.4V
■ Typically the microphone bias is between 2V and 2.5V, or as specified by the microphone vendor
■ Drop-out voltage:
■ 300mV minimum
■ Guaranteed for configuration of voltage or current output shown in Table 10.5 and Table 10.6
■ Output voltage:
■ 4-bit programmable from 1.7V to 3.6V
■ Tolerance 90% to 110%
■ Output current:
■ 4-bit programmable from 200µA to 1.230mA
■ Maximum current guaranteed to be >1mA
■ Load capacitance:
■ Unconditionally stable for 1µF ± 20% and 2.2µF ± 20% pure C

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Output Step VOL_SET[3:0] Min Typ Max Units

0 0000 - 1.71 - V

1 0001 - 1.76 - V

2 0010 - 1.82 - V

3 0011 - 1.87 - V

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

4 0100 - 1.95 - V

5 0101 - 2.02 - V

6 0110 - 2.10 - V

7 0111 - 2.18 - V

8 1000 - 2.32 - V

9 1001 - 2.43 - V

10 1010 - 2.56 - V

11 1011 - 2.69 - V

12 1100 - 2.90 - V

13 1101 - 3.08 - V

14 1110 - 3.33 - V

15 1111 - 3.57 - V

Table 10.5: Voltage Output Steps

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Output Step CUR_SET[3:0] Typ Units

0 0000 0.200 mA

1 0001 0.280 mA

2 0010 0.340 mA

3 0011 0.420 mA

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

4 0100 0.480 mA

5 0101 0.530 mA

6 0110 0.610 mA

7 0111 0.670 mA

8 1000 0.750 mA

9 1001 0.810 mA

10 1010 0.860 mA

11 1011 0.950 mA

12 1100 1.000 mA

13 1101 1.090 mA

14 1110 1.140 mA

15 1111 1.230 mA

Table 10.6: Current Output Steps

Note:

For BAT_P, the PSRR at 100Hz to 22kHz, with >300mV supply headroom, decoupling capacitor of 1.1μF, is
typically 58.9dB and worst case 53.4dB.
For VDD_AUDIO, the PSRR at 100Hz to 22kHz, decoupling capacitor of 1.1μF, is typically 88dB and worst case
60dB.

10.2.12 Line Input

If the input analogue gain is set to less than 24dB, BlueCore5‑Multimedia Flash (16Mb) automatically selects line
input mode. In line input mode the first stage of the amplifier is automatically disabled, providing additional power
saving. In line input mode the input impedance varies from 6kΩ to 30kΩ, depending on the volume setting. Figure
10.5 and Figure 10.6 show 2 circuits for line input operation and show connections for either differential or single-
ended inputs.

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C1
MIC_A_P

G-TW-0001449.4.2
C2
MIC_A_N

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Figure 10.5: Differential Input

C1
MIC_A_P

G-TW-0001450.4.2
C2
MIC_A_N

Figure 10.6: Single-ended Input

Note:

In Figure 10.5 and Figure 10.6 show only single channels.

10.2.13 Output Stage

The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling
frequency to bit stream, which is fed into the analogue output circuitry.
The output stage circuit comprises a DAC with gain setting and class AB output stage amplifier. The output is
available as a differential signal between SPKR_A_N and SPKR_A_P for the left channel, as Figure 10.7 shows,
and between SPKR_B_N and SPKR_B_P for the right channel.
The output stage is capable of driving a speaker directly when its impedance is at least 8Ω and an external regulator
is used, but this will be at a reduced output swing.

SPKR_A_P
G-TW-0001451.3.2

SPKR_A_N

Figure 10.7: Speaker Output

Note:

Figure 10.7 shows a single channel only.

A 3-bit programmable resistive divider controls the analogue gain of the output stage, which sets the gain in steps
of approximately 3dB.

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10.2.14 Mono Operation

Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono
channel for audio in and audio out. In mono operation the right channel is the auxiliary mono channel that may be
used in dual mono channel operation.
In single channel mono operation, disable the other channel to reduce power consumption.
Important Note:

For mono operation this data sheet uses the left channel for standard mono operation for audio input and output
and with respect to software and any registers, channel 0 or channel A represents the standard mono channel
for audio input and output. In mono operation the second channel which is the right channel, channel 1 or channel
B can be used as a second mono channel if required and this channel is referred to as the auxiliary mono

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

channel for audio input and output.

10.2.15 Side Tone

In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the
microphone signal to the earpiece. The BlueCore5‑Multimedia Flash (16Mb) codec contains side tone circuitry to
do this. The side tone hardware is configured through the following PS Keys:
■ PSKEY_SIDE_TONE_ENABLE
■ PSKEY_SIDE_TONE_GAIN
■ PSKEY_SIDE_TONE_AFTER_ADC
■ PSKEY_SIDE_TONE_AFTER_DAC

10.2.16 Integrated Digital Filter

BlueCore5‑Multimedia Flash (16Mb) has a programmable digital filter integrated into the ADC channel of the
codec. The filter is a 2 stage, second order IIR and is used for functions such as custom wind noise rejection. The
filter also has optional DC blocking.
The filter has 10 configuration words used as follows:
■ 1 for gain value
■ 8 for coefficient values
■ 1 for enabling and disabling the DC blocking
The gain and coefficients are all 12-bit 2's complement signed integer with the format XX.XXXXXXXXXX

Note:

The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.

For example:

01.1111111111 = most positive number, close to 2

01.0000000000 = 1

00.0000000000 = 0

11.0000000000 = -1

10.0000000000 = -2, most negative number

Equation 10.1 shows the equation for the IIR filter. Equation 10.2 shows the equation for when the DC blocking is
enabled.
The filter can be configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in
the order shown below:

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0 : Gain

1 : b01

2 : b02

3 : a01

4 : a02

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

5 : b11

6 : b12

7 : a11

8 : a12

9 : DC Block (1 = enable, 0 = disable)

(1 +b −1 −2 ) (1 +b −1 −2 )
01 z + b02 z 11 z + b12 z
Filter, H(z) = Gain × ×
(1 +a −1 −2 ) (1 +a −1 −2 )
z +a z z +a z
01 02 11 12

Equation 10.1: IIR Filter Transfer Function, H(z)

Filter with DC Blocking, HDC (z) = H(z) × ( 1 − z−1 )

Equation 10.2: IIR Filter plus DC Blocking Transfer Function, H DC(z)

10.3 PCM Interface

The audio PCM interface supports continuous transmission and reception of PCM encoded audio data over
Bluetooth.
PCM is a standard method used to digitise audio, particularly voice, for transmission over digital communication
channels. Through its PCM interface, BlueCore5‑Multimedia Flash (16Mb) has hardware support for continual
transmission and reception of PCM data, so reducing processor overhead. BlueCore5‑Multimedia Flash (16Mb)
offers a bidirectional digital audio interface that routes directly into the baseband layer of the on-chip firmware. It
does not pass through the HCI protocol layer.
Hardware on BlueCore5‑Multimedia Flash (16Mb) allows the data to be sent to and received from a SCO connection.
Up to 3 SCO connections can be supported by the PCM interface at any one time.
BlueCore5‑Multimedia Flash (16Mb) can operate as the PCM interface master generating PCM_SYNC and
PCM_CLK or as a PCM interface slave accepting externally generated PCM_SYNC and PCM_CLK.
BlueCore5‑Multimedia Flash (16Mb) is compatible with various clock formats, including Long Frame Sync, Short
Frame Sync and GCI timing environments.
It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats, and can receive and transmit on
any selection of 3 of the first 4 slots following PCM_SYNC. The PCM configuration options are enabled by setting
the PS Key PSKEY_PCM_CONFIG32.

10.3.1 PCM Interface Master/Slave

When configured as the master of the PCM interface, BlueCore5‑Multimedia Flash (16Mb) generates PCM_CLK
and PCM_SYNC.

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PCM_OUT

PCM_IN

PCM_CLK 128/256/512/1536/2400kHz

PCM_SYNC 8/48kHz

Figure 10.8: PCM Interface Master

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

PCM
_OUT

PCM
_IN

PCM
_CLK Upto2400kHz

PCM
_ SYNC 8/48kHz

Figure 10.9: PCM Interface Slave

10.3.2 Long Frame Sync

Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples.
In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
BlueCore5‑Multimedia Flash (16Mb) is configured as PCM master, generating PCM_SYNC and PCM_CLK, then
PCM_SYNC is 8-bits long. When BlueCore5‑Multimedia Flash (16Mb) is configured as PCM Slave, PCM_SYNC
may be from one cycle PCM_CLK to half the PCM_SYNC rate.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8

PCM_IN Undefined 1 2 3 4 5 6 7 8 Undefined

Figure 10.10: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore5‑Multimedia Flash (16Mb) samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT
on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the
LSB position or on the rising edge.

10.3.3 Short Frame Sync

In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always
one clock cycle long.

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PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Figure 10.11: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore5‑Multimedia Flash (16Mb) samples PCM_IN on the falling edge of PCM_CLK
and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge
of PCM_CLK in the LSB position or on the rising edge.

10.3.4 Multi-slot Operation

More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO
connections can be carried over any of the first four slots.
LONG_PCM_SYNC

Or

SHORT_PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care

Figure 10.12: Multi-slot Operation with Two Slots and 8-bit Companded Samples

10.3.5 GCI Interface

BlueCore5‑Multimedia Flash (16Mb) is compatible with the GCI, a standard synchronous 2B+D ISDN timing
interface. The 2 64kbps B channels can be accessed when this mode is configured.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Do Not Do Not
PCM_IN Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Care

B1 Channel B2 Channel

Figure 10.13: GCI Interface

The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.

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10.3.6 Slots and Sample Formats

BlueCore5‑Multimedia Flash (16Mb) can receive and transmit on any selection of the first 4 slots following each sync
pulse. Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit
sample formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.
BlueCore5‑Multimedia Flash (16Mb) supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
The sample rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8
unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio
attenuation compatible with some Motorola codecs.
Sign
Extension

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
8-Bit
Sample
A 16-bit slot with 8-bit companded sample and sign extension selected.

8-Bit
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.

Sign
Extension
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
13-Bit
Sample
A 16-bit slot with 13-bit linear sample and sign extension selected.

13-Bit
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.

Figure 10.14: 16-Bit Slot Length and Sample Formats

10.3.7 Additional Features

BlueCore5‑Multimedia Flash (16Mb) has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC
may also be forced to 0 while keeping PCM_CLK running which some codecs use to control power down.

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10.3.8 PCM Timing Information

Symbol Parameter Min Typ Max Unit

128
4MHz DDS generation.
Selection of frequency
- 256 - kHz
is programmable. See
Table 10.10.
512
fmclk PCM_CLK frequency
48MHz DDS

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

generation. Selection
of frequency is
2.9 - - kHz
programmable. See
Table 10.9 and Section
10.3.9.

- PCM_SYNC frequency for SCO connection - 8 - kHz

tmclkh (a) PCM_CLK high 4MHz DDS generation 980 - - ns

tmclkl (a) PCM_CLK low 4MHz DDS generation 730 - - ns

48MHz DDS
- PCM_CLK jitter - - 21 ns pk-pk
generation

Delay time from PCM_CLK high to PCM_SYNC

tdmclksynch - - 20 ns
high

Delay time from PCM_CLK high to valid

tdmclkpout - - 20 ns
PCM_OUT

Delay time from PCM_CLK low to PCM_SYNC

tdmclklsyncl - - 20 ns
low (Long Frame Sync only)

Delay time from PCM_CLK high to PCM_SYNC

tdmclkhsyncl - - 20 ns
low

Delay time from PCM_CLK low to PCM_OUT

tdmclklpoutz - - 20 ns
high impedance

Delay time from PCM_CLK high to PCM_OUT

tdmclkhpoutz - - 20 ns
high impedance

tsupinclkl Set-up time for PCM_IN valid to PCM_CLK low 30 - - ns

thpinclkl Hold time for PCM_CLK low to PCM_IN invalid 10 - - ns

Table 10.7: PCM Master Timing

(a) Assumes normal system clock operation. Figures will vary during low-power modes, when system clock speeds are reduced.

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t dmclklsyncl

t dmclksynch t dmclkhsyncl

PCM_SYNC

fmlk

tmclkh tmclkl

PCM_CLK

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

t dmclklpoutz

t dmclkpout tr ,t f t dmclkhpoutz

PCM_OUT MSB (LSB) LSB (MSB)

t supinclkl t hpinclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 10.15: PCM Master Timing Long Frame Sync

t dmclksynch t dmclkhsyncl

PCM_SYNC

fmlk

tmclkh tmclkl

PCM_CLK

t dmclklpoutz

t dmclkpout tr ,t f t dmclkhpoutz

PCM_OUT MSB (LSB) LSB (MSB)

t supinclkl t hpinclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 10.16: PCM Master Timing Short Frame Sync

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Symbol Parameter Min Typ Max Unit

fsclk PCM clock frequency (Slave mode: input) 64 - (a) kHz

fsclk PCM clock frequency (GCI mode) 128 - (b) kHz

tsclkl PCM_CLK low time 80 - - ns

tsclkh PCM_CLK high time 80 - - ns

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

thsclksynch Hold time from PCM_CLK low to PCM_SYNC high 20 - - ns

tsusclksynch Set-up time for PCM_SYNC high to PCM_CLK low 20 - - ns

Delay time from PCM_SYNC or PCM_CLK,

tdpout whichever is later, to valid PCM_OUT data (Long - - 20 ns
Frame Sync only)

tdsclkhpout Delay time from CLK high to PCM_OUT valid data - - 20 ns

Delay time from PCM_SYNC or PCM_CLK low,

tdpoutz whichever is later, to PCM_OUT data line high - - 20 ns
impedance

tsupinsclkl Set-up time for PCM_IN valid to CLK low 20 - - ns

thpinsclkl Hold time for PCM_CLK low to PCM_IN invalid 20 - - ns

Table 10.8: PCM Slave Timing

(a) Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
(b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

fsclk

tsclkh ttsclkl

PCM_CLK

t hsclksynch t susclksynch

PCM_SYNC

t dpoutz

tdpout t dsclkhpout tr ,t f t dpoutz

PCM_OUT MSB (LSB) LSB (MSB)

t supinsclkl t hpinsclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 10.17: PCM Slave Timing Long Frame Sync

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 Audio Interface

fsclk

tsclkh ttsclkl

PCM_CLK

t susclksynch t hsclksynch

PCM_SYNC

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

t dpoutz
t dpoutz
t dsclkhpout tr ,t f

PCM_OUT MSB (LSB) LSB (MSB)

t supinsclkl t hpinsclkl

PCM_IN MSB (LSB) LSB (MSB)

Figure 10.18: PCM Slave Timing Short Frame Sync

10.3.9 PCM_CLK and PCM_SYNC Generation

BlueCore5‑Multimedia Flash (16Mb) has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:
■ Generating these signals by DDS from BlueCore5‑Multimedia Flash (16Mb) internal 4MHz clock. Using
this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
■ Generating these signals by DDS from an internal 48MHz clock (which allows a greater range of frequencies
to be generated with low jitter but consumes more power). To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by
LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
Equation 10.3 describes PCM_CLK frequency when being generated using the internal 48MHz clock:

CNT_RATE
f= ×24MHz
CNT_LIMIT

Equation 10.3: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 10.4:
PCM _ CLK
f=
SYNC _ LIMIT x 8

Equation 10.4: PCM_SYNC Frequency Relative to PCM_CLK

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to
0x08080177.

10.3.10 PCM Configuration

The PCM configuration is set using the PS Keys, PSKEY_PCM_CONFIG32 described in Table 10.10 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 10.9. The default for PSKEY_PCM_CONFIG32 is 0x00800000,
i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating
256kHz PCM_CLK from 4MHz internal clock with no tristate of PCM_OUT.

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 Audio Interface

Name Bit Position Description

CNT_LIMIT [12:0] Sets PCM_CLK counter limit

CNT_RATE [23:16] Sets PCM_CLK count rate

SYNC_LIMIT [31:24] Sets PCM_SYNC division relative to PCM_CLK

Table 10.9: PSKEY_PCM_LOW_JITTER_CONFIG Description

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Name Bit Position Description

- 0 Set to 0.

0 = master mode with internal generation of PCM_CLK and

PCM_SYNC.
SLAVE_MODE_EN 1
1 = slave mode requiring externally generated PCM_CLK
and PCM_SYNC.

0 = long frame sync (rising edge indicates start of frame).

SHORT_SYNC_EN 2
1 = short frame sync (falling edge indicates start of frame).

- 3 Set to 0.

0 = padding of 8 or 13-bit voice sample into a 16-bit slot by

inserting extra LSBs. When padding is selected with 13-bit
SIGN_EXTEND_EN 4 voice sample, the 3 padding bits are the audio gain setting;
with 8-bit sample the 8 padding bits are zeroes.
1 = sign-extension.

0 = MSB first of transmit and receive voice samples.

LSB_FIRST_EN 5
1 = LSB first of transmit and receive voice samples.

0 = drive PCM_OUT continuously.

TX_TRISTATE_EN 6 1 = tristate PCM_OUT immediately after falling edge of
PCM_CLK in the last bit of an active slot, assuming the
next slot is not active.

0 = tristate PCM_OUT immediately after falling edge of

PCM_CLK in last bit of an active slot, assuming the next
TX_TRISTATE_RISING_EDGE_EN 7 slot is also not active.
1 = tristate PCM_OUT after rising edge of PCM_CLK.

0 = enable PCM_SYNC output when master.

SYNC_SUPPRESS_EN 8 1 = suppress PCM_SYNC while keeping PCM_CLK
running. Some codecs use this to enter a low power state.

GCI_MODE_EN 9 1 = enable GCI mode.

MUTE_EN 10 1 = force PCM_OUT to 0.

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 Audio Interface

Name Bit Position Description

0 = set PCM_CLK and PCM_SYNC generation via DDS

from internal 4MHz clock.
48M_PCM_CLK_GEN_EN 11
1 = set PCM_CLK and PCM_SYNC generation via DDS
from internal 48MHz clock.

0 = set PCM_SYNC length to 8 PCM_CLK cycles.

1 = set length to 16 PCM_CLK cycles.
LONG_LENGTH_SYNC_EN 12
Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

- [20:16] Set to 0b00000.

Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz

MASTER_CLK_RATE [22:21] PCM_CLK frequency when master and
48M_PCM_CLK_GEN_EN (bit 11) is low.

ACTIVE_SLOT [26:23] Default is 0001. Ignored by firmware.

Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit

SAMPLE_FORMAT [28:27] sample with 16-cycle slot duration or 8 (0b11) bit sample
with 8-cycle slot duration.

Table 10.10: PSKEY_PCM_CONFIG32 Description

10.4 Digital Audio Interface (I²S)

The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table
10.11 lists these alternative functions. Figure 10.19 shows the timing diagram.

PCM Interface I2S Interface

PCM_OUT SD_OUT

PCM_IN SD_IN

PCM_SYNC WS

PCM_CLK SCK

Table 10.11: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
Table 10.12 describes the values for the PS Key PSKEY_DIGITAL_AUDIO_CONFIG that is used to set-up the digital
audio interface. For example, to configure an I2S interface with 16-bit SD data set
PSKEY_DIGITAL_AUDIO_CONFIG to 0x0406.

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 Audio Interface

Bit Mask Name Description

0: left justified
D[0] 0x0001 CONFIG_JUSTIFY_FORMAT
1: right justified.

For left justified formats:

■ 0: is MSB of SD data occurs in the first
D[1] 0x0002 CONFIG_LEFT_JUSTIFY_DELAY SCLK period following WS transition
■ 1: is MSB of SD data occurs in the
second SCLK period.

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0: SD data is left channel when WS is high.
D[2] 0x0004 CONFIG_CHANNEL_POLARITY
1: SD data is right channel.

0: 17-bit SD data is rounded down to 16bits.

1: the audio attenuation defined in
D[3] 0x0008 CONFIG_AUDIO_ATTEN_EN CONFIG_AUDIO_ATTEN is applied over 24
bits with saturated rounding. Requires
CONFIG_16_BIT_CROP_EN to be 0.

D[7:4] 0x00f0 CONFIG_AUDIO_ATTEN Attenuation in 6dB steps.

Resolution of data on SD_IN:

■ 00: 16-bit
■ 01: 20-bit
D[9:8] 0x0300 CONFIG_JUSTIFY_RESOLUTION ■ 10: 24-bit
■ 11: reserved
This is required for right justified format and
with left justified LSB first.

0: 17-bit SD_IN data is rounded down to

16bits.
D[10] 0x0400 CONFIG_16_BIT_CROP_EN
1: only the most significant 16bits of data are
received.

Table 10.12: PSKEY_DIGITAL_AUDIO_CONFIG

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 Audio Interface

WS Left Channel Right Channel

SCK

SD_IN/OUT MSB LSB MSB LSB

Left-Justified Mode

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WS Left Channel Right Channel

SCK

SD_IN/OUT MSB LSB MSB LSB

Right-Justified Mode

WS Left Channel Right Channel

SCK

SD_IN/OUT MSB LSB MSB LSB

I2S Mode

Figure 10.19: Digital Audio Interface Modes

The internal representation of audio samples within BlueCore5‑Multimedia Flash (16Mb) is 16-bit and data on
SD_OUT is limited to 16-bit per channel.

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 Audio Interface

Symbol Parameter Min Typ Max Unit

- SCK Frequency - - 6.2 MHz

- WS Frequency - - 96 kHz

tch SCK high time 80 - - ns

tcl SCK low time 80 - - ns

topd SCK to SD_OUT delay - - 20 ns

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

tssu WS to SCK set-up time 20 - - ns

tsh WS to SCK hold time 20 - - ns

tisu SD_IN to SCK set-up time 20 - - ns

tih SD_IN to SCK hold time 20 - - ns

Table 10.13: Digital Audio Interface Slave Timing

WS(Input)

tssu tsh

tch tcl

SCK(Input)

topd

SD_OUT

tisu t ih

SD_IN

Figure 10.20: Digital Audio Interface Slave Timing

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 Audio Interface

Symbol Parameter Min Typ Max Unit

- SCK Frequency - - 6.2 MHz

- WS Frequency - - 96 kHz

topd SCK to SD_OUT delay - - 20 ns

tspd SCK to WS delay - - 20 ns

tisu SD_IN to SCK set-up time 20 - - ns

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

tih SD_IN to SCK hold time 10 - - ns

Table 10.14: Digital Audio Interface Master Timing

WS(Output)

t spd

SCK(Output)

topd

SD_OUT

t isu t ih

SD_IN

Figure 10.21: Digital Audio Interface Master Timing

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 Power Control and Regulation

11 Power Control and Regulation

BlueCore5‑Multimedia Flash (16Mb) contains 4 regulators:
■ A switch-mode regulator for generating the 1.8V supply rail.
■ 2 low-voltage regulators, running in parallel to supply the 1.5V core supplies from a 1.8V supply rail.
Various configurations for power control and regulation with the BlueCore5‑Multimedia Flash (16Mb) are available:
■ A high-voltage rail running the switch-mode regulator and the low-voltage regulators in series, as Figure
11.1 shows
■ BlueCore5‑Multimedia Flash (16Mb) powered directly from an external 1.8V supply rail, by-passing the
switch-mode regulator

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ An external 1.5V rail omitting all regulators
■ A 1.8V linear voltage regulator

1.8V Supply Rail

VREGIN_L

IN OUT VDD_ANA
Low-voltage
VREGENABLE_L Linear Regulator VDD_RADIO
EN SENSE

EN OUT VDD_AUDIO
Audio Low-
voltage Regulator
IN SENSE
VREGIN_AUDIO
VDD_CHG
IN
Battery Charger
OUT
L1
BAT_P LX
LX
BAT_N Switch-mode
Regulator VDD_SMP_CORE C1
EN SENSE

G-TW0001423.4.2

VREGENABLE_H VREGOUT_H
EN OUT
High-voltage
VREGIN_H Linear Regulator
IN SENSE

Figure 11.1: Voltage Regulator Configuration

11.1 Power Sequencing

The 1.50V supply rails are VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO. CSR recommends
that these supply rails are all powered at the same time.
The digital I/O supply rails are VDD_PADS, VDD_PIO and VDD_USB.
The sequence of powering the 1.50V supply rails relative to the digital I/O supply rails is not important. If the digital
I/O supply rails are powered before the 1.50V supply rails, all digital I/Os will have a weak pull-down irrespective of
the reset state.
VDD_ANA, VDD_AUDIO, VDD_LO and VDD_RADIO can connect directly to a 1.50V supply.

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 Power Control and Regulation

A simple RC filter is recommended for VDD_CORE to reduce transients fed back onto the power supply rails.
The digital I/O supply rails are connected either together or independently to an appropriate voltage rail. Decoupling
of the digital I/O supply rails is recommended.

11.2 External Voltage Source

If any of the supply rails for BlueCore5‑Multimedia Flash (16Mb) are supplied from an external voltage source, rather
than one of the internal voltage regulators, CSR recommends that VDD_AUDIO, VDD_LO and VDD_RADIO should
have less than 10mV rms noise levels between 0 and 10MHz. Also avoid single tone frequencies.
The transient response of any external regulator used should match or be better than the internal regulator available
on BlueCore5‑Multimedia Flash (16Mb). For more information, refer to regulator characteristics in Section 13. It is

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

essential that the power rail recovers quickly at the start of a packet, where the power consumption jumps to high
levels.

11.3 Switch-mode Regulator

CSR recommends the on-chip switch-mode regulator to power the 1.8V supply rail.
An external LC filter circuit of a low-resistance series inductor, L1 (22µH), followed by a low ESR shunt capacitor,
C1 (4.7µF), is required between the LX terminal and the 1.8V supply rail. A connection between the 1.8V supply rail
and the VDD_SMP_CORE pin is required.
A 2.2µF decoupling capacitor is required between BAT_P and BAT_N.
To maintain high-efficiency power conversion and low supply ripple, it is essential that the series resistance of tracks
between the BAT_P and BAT_N terminals, the filter and decoupling components, and the external voltage source
are minimised.
The switch-mode regulator is enabled by either:
■ VREGENABLE_H pin
■ BlueCore5‑Multimedia Flash (16Mb) device firmware
■ BlueCore5‑Multimedia Flash (16Mb) battery charger
The switch-mode regulator switches into a low-power pulse skipping mode when the device is sent into deep sleep
mode, or in reset.
When the switch-mode regulator is not required the terminals BAT_P and LX must be grounded or left unconnected.

11.4 High-voltage Linear Regulator

A high-voltage linear regulator with a 1.8V output is available. This regulator should not be used to power external
circuitry, prior to using this regulator contact CSR.
A smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω resistor to ground, should be connected to the
output of the high-voltage linear regulator, VREGOUT_H. Alternatively use a 2.2µF capacitor with an ESR of at least
2Ω.
The high-voltage linear regulator is enabled by either:
■ VREGENABLE_H pin
■ BlueCore5‑Multimedia Flash (16Mb) device firmware
■ BlueCore5‑Multimedia Flash (16Mb) battery charger
The regulator is switched into a low-power mode when the device is in deep sleep mode, or in reset.
When the high-voltage linear regulator is not used the terminals VREGIN_H and VREGOUT_H must be left
unconnected, or tied to ground.

11.5 Low-voltage Linear Regulator

The low-voltage linear regulator is available to power a 1.5V supply rail. Its output is connected internally to
VDD_ANA, and can be connected externally to the other 1.5V power inputs.
If the low-voltage linear regulator is used, connect a smoothing circuit using a low ESR 2.2µF capacitor and a
2.2Ω resistor to ground to the output of the low-voltage linear regulator, VDD_ANA. Alternatively use a 2.2µF
capacitor with an ESR of at least 2Ω.

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 Power Control and Regulation

The low-voltage linear regulator is enabled by either:

■ VREGENABLE_L pin
■ BlueCore5‑Multimedia Flash (16Mb) device firmware
■ BlueCore5‑Multimedia Flash (16Mb) battery charger
The low-voltage linear regulator switches into a low power mode when the device is in deep sleep mode, or in reset.
When the low-voltage linear regulator is not used, either leave the terminal VREGIN_L unconnected, or tie it to
VDD_ANA.

11.6 Low-voltage Audio Linear Regulator

The low-voltage audio linear regulator is available to power a 1.5V audio supply rail. Its output is connected internally

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

to VDD_AUDIO, and can be connected externally to the other 1.5V audio power inputs.
If the low-voltage audio linear regulator is used, connect a smoothing circuit using a low ESR 2.2µF capacitor and
a 2.2Ω resistor to ground to the output of the low-voltage audio linear regulator, VDD_AUDIO. Alternatively use a
2.2µF capacitor with an ESR of at least 2Ω.
The low-voltage audio linear regulator is enabled by either:
■ VREGENABLE_L pin
■ BlueCore5‑Multimedia Flash (16Mb) device firmware
The low-voltage audio linear regulator switches into a low-power mode when no audio cells are enabled, or when
the chip is in reset.
When this regulator is not used, either leave the terminal VREGIN_AUDIO unconnected or tie it to VDD_AUDIO.

11.7 Voltage Regulator Enable Pins

The voltage regulator enable pins, VREGENABLE_H and VREGENABLE_L, are used to enable the
BlueCore5‑Multimedia Flash (16Mb) device if the on-chip regulators are being used. Table 11.1 shows the enable
pin responsible for each voltage regulator.

Enable Pin Regulator

VREGENABLE_H High-voltage Linear Regulator and Switch-mode Regulator

VREGENABLE_L Low-voltage Linear Regulator and Low-voltage Audio Linear Regulator

Table 11.1: BlueCore5‑Multimedia Flash (16Mb) Voltage Regulator Enable Pins

The voltage regulator enable pins are active high, with weak pull-downs.
BlueCore5‑Multimedia Flash (16Mb) boots-up when the voltage regulator enable pins are pulled high, enabling the
appropriate regulators. The firmware then latches the regulators on and the voltage regulator enable pins may then
be released.
The status of the VREGENABLE_H pin is available to firmware through an internal connection. VREGENABLE_H
also works as an input line.

11.8 Battery Charger

The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer
batteries only. It shares a connection to the battery terminal, BAT_P, with the switch-mode regulator. However it may
be used in conjunction with either of the high-voltage regulators on the device.
The constant current level can be varied to allow charging of different capacity batteries.
The charger enters various states of operation as it charges a battery, as listed below. A full operational description
is in BlueCore5 Charger Description and Calibration Procedure Application Note:

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 Power Control and Regulation

■ Off : entered when charger disconnected.

■ Trickle charge: entered when battery is below 2.9V. The battery is charged at a nominal 4.5mA. This mode
is for the safe charge of deeply discharged cells.
■ Fast charge constant current: entered when battery is above 2.9V. The charger enters the main fast charge
mode. This mode charges the battery at the selected constant current, Ichgset.
■ Fast charge constant voltage: entered when battery has reached a selected voltage, Vfloat. The charger
switches mode to maintain the cell voltage at the Vfloat voltage by adjusting the charge current.
■ Standby: this is the state when the battery is fully charged and no charging takes place. The battery voltage
is continuously monitored and if it drops by more than 150mV below the Vfloat voltage the charger will re-
enter the fast charge constant current mode to keep the battery fully charged.
When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

operates and an LED connected to the terminal LED[0] illuminates. By default, until the firmware is running, the
LED pulses at a low-duty cycle to minimise current consumption.
The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect, using an
internal status bit, when the charger is powered. Therefore when the charger supply is not connected to VDD_CHG,
the terminal must be left open-circuit. When not connected, the VDD_CHG pin must be allowed to float and not pulled
to a power rail. When the battery charger is not enabled this pin may float to a low undefined voltage. Any DC
connection increases current consumption of the device. Capacitive components may be connected such as diodes,
FETs and ESD protection.
The battery charger is designed to operate with a permanently connected battery. If the application enables the
charger input to be connected while the battery is disconnected, then the BAT_P pin voltage may become unstable.
This in turn may cause damage to the internal switch-mode regulator. Connecting a 470µF capacitor to BAT_P limits
these oscillations which prevents damage.

11.9 LED Drivers

BlueCore5‑Multimedia Flash (16Mb) includes 2 pads dedicated to driving LED indicators. Both terminals can be
controlled by firmware, while LED[0] can also be set by the battery charger.
The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current limiting resistor.
CSR recommends that the LED pad, LED[0] or LED[1] pins, operate with a pad voltage below 0.5V. In this case,
the pad is like a resistor, RON. The resistance together with the external series resistor sets the current, ILED, in the
LED. The current is also dependent on the external voltage, VDD, as Figure 11.2 shows.

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 Power Control and Regulation

VDD

LED Forward Voltage, VF

ILED

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RLED Resistor Voltage Drop, VR
LED[0] or LED[1]

Pad Voltage, VPAD; RON = 20Ω

G-TW-0000255.3.2
Figure 11.2: LED Equivalent Circuit
From Figure 11.2 it is possible to derive Equation 11.1 to calculate ILED. If a known value of current is required through
the LED to give a specific luminous intensity, then the value of RLED can be calculated.
VDD − V
F
ILED =
R +R
LED ON

Equation 11.1: LED Current

For the LED[0] or LED[1] pad to act as resistance, the external series resistor, RLED, needs to be such that the
voltage drop across it, VR, keeps VPAD below 0.5V. Equation 11.2 also applies.

VDD = VF + VR + VPAD

Equation 11.2: LED PAD Voltage

Note:

The LED current will add to the overall application current, so conservative selection of the LEDs will preserve
power consumption.

11.10 Reset, RST#

BlueCore5‑Multimedia Flash (16Mb) can be reset from several sources:
■ RST# pin
■ Power-on reset
■ UART break character
■ Software configured watchdog timer
The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset
is performed between 1.5ms and 4.0ms following RST# being active. CSR recommends applying RST# for a period
greater than 5ms.
The power-on reset occurs when the VDD_CORE supply falls below typically 1.25V and is released when
VDD_CORE rises above typically 1.30V. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs
are set to tristate. Following a reset, BlueCore5‑Multimedia Flash (16Mb) assumes the maximum XTAL_IN

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 Power Control and Regulation

frequency, which ensures that the internal clocks run at a safe (low) frequency until BlueCore5‑Multimedia Flash
(16Mb) is configured for the actual XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in
BlueCore5‑Multimedia Flash (16Mb) free runs, again at a safe frequency.

11.10.1 Digital Pin States on Reset

Table 11.2 shows the pin states of BlueCore5‑Multimedia Flash (16Mb) on reset. PU and PD default to weak values
unless specified otherwise.

No Core Voltage
Pin Name / Group I/O Type Full Chip Reset
Reset

USB_DP Digital bidirectional N/A N/A

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

USB_DN Digital bidirectional N/A N/A

UART_RX Digital input with PD PD PD

UART_CTS Digital input with PD PD PD

UART_TX Digital bidirectional with PU PU PU

UART_RTS Digital bidirectional with PU PU PU

SPI_MOSI Digital input with PD PD PD

SPI_CLK Digital input with PD PD PD

SPI_CS# Digital input with PU PU PU

SPI_MISO Digital tristate output with PD PD PD

PCM_IN Digital input with PD PD PD

PCM_CLK Digital bidirectional with PD PD PD

PCM_SYNC Digital bidirectional with PD PD PD

PCM_OUT Digital tristate output with PD PD PD

RST# Digital input with PU PU PU

TEST_EN Digital input with PD PD PD

Digital bidirectional with PU/

PIO[15:0] PD PD
PD

Table 11.2: Pin States on Reset

11.10.2 Status after Reset

The status of BlueCore5‑Multimedia Flash (16Mb) after a reset is:
■ Warm reset: data rate and RAM data remain available
■ Cold reset: data rate and RAM data not available

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 Example Application Schematic

12 Example Application Schematic

3V3
3V3 to be supplied externally 3V3
SD CARD CONNECTOR

5
1
3
7
C1 J1
100n

Regulator enable pin to Host

RN1 JAE SG5S009V1A1

Clock request in from Host

Clock request out to Host
47k 4
Supply Volts
12

(Venable, high ≥ 0.95V)

11
Card Insert Detect NO SW Pin1
Protection Detect NO SW Pin2

6
4
2
8
9
Data Line[Bit2]
8
Data Line[Bit1]
7
Data Line[Bit0]
2
Command/Response
5
VDD_PIO is between 1V8 and 3V3 typically VDD_USB is between 1V8 and 3V3 typically 10
Clock
depending on host interface signal voltage on clock request lines. depending on host interface signal voltage on UART. R1 13
Protection Detect NO SW Pin1
Card Insert Detect NO SW Pin2
Any voltage above 1.8V is to be supplied externally. Any voltage above 1.8V is to be supplied externally. 10k 1
Card Detect/Data Line[Bit3]
3
R2 Ground

CASE
CASE
6
Ground
10k
VDD_PIO VDD_USB

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

R3 R4
470k 470k R5

14
15
TP1

CLOCK_REQ_OUT
3V3 0R

CLOCK_REQ_IN
1V5 1V5 1V8 1V5_AUDIO 1V8 1V5 1V8 1V8
TP2
TP3
1V5 1V8 3V3 3V3 3V3
R6 L1

C2 2R2 C3 R7 C4 R8 C5 S1 S2 S3
22u
L2 15p 10n 2R2 10n 2R2 C6 PLAY REV FF
10n
15n 4u7
TP14

LX
C7 C8 C9
2u2 2u2 2u2

M10
U1

K13

N10

D12
D13

K12

H12
N11

A11
C13

B13

B12
C12
B11

L10

L12
J13

M3

M1

M2

M9

J11
K1

A4

D3

N9
C7
B4
A8
C10

E2
L1

E1

E3

L9
F3
BC5-MM Flash
15p

VDD_RADIO

VDD_AUDIO
VDD_LO

VDD_CORE
VDD_CORE

VDD_PIO

VREGIN_AUDIO

VDD_SMP_CORE
VDD_PADS

VDD_USB

VREGENABLE_H
VREGOUT_H
VREGOUT_H

VREGIN_H
VREGIN_H

PIO[2]

PIO[3]

PIO[10]

PIO[13]

PIO[14]

PIO[15]

PIO[12]
LX
LX

PIO[9]

PIO[5]

PIO[4]
RXEN/PIO[0]

TXEN/PIO[1]
VREGIN_L
VREGENABLE_L
VDD_MEM

PIO[11]
VDD_MEM

VDD_ANA
Printed Antenna T1
ANT1 DBF81F104
J12
PIO[8]
2 6 RF_P H1 H13
DC BAL RF_P PIO[7]
M8
PIO[6]
1
UNBAL
3 4 RF_N J1 Switch-mode
NC BAL RF_N
GND
GND
GND

Linear Linear

Enable
regulator Linear D11
LED0
regulator Enable regulator (input on regulator
for audio for core BAT_P)
5
8
7

G1 C8
N/C 1.5V regulators 1.8V regulators LED1
F1
N/C
E11 SPI_CLK
SPI_CLK TP4
E12 SPI_MISO
SPI_MISO TP5
H3 F12 SPI_MOSI
AUX_DAC SPI_MOSI TP6
E13 SPI_CSB
SPI_CS# TP7
L13 UART_TX
UART_TX
M12 UART_RX
UART_RX
M11 UART_RTS UART interface to Host
UART_RTS
N13 M13 UART_CTS
USB_DP UART_CTS
N12
USB_DN
F13 SD_IN
PCM_IN
F11 SD_OUT
PCM_OUT
PCM_CLK
H11 SCK I²S interface to Host
B8 G11 WS
VDD_CHG PCM_SYNC
B9
VDD_CHG
C9
VDD_CHG

N1 EXT_CLOCK
XTAL_IN Main clock from Host
TP8 VBAT
A12
BAT_P
A13
BAT_P
C11
2u2
N2
XTAL_OUT

BT1
Phone main Li+ cell

G13 RST#

AU_REF_DCPL
RST# RST# pin to Host
VSS_AUDIO
VSS_RADIO
VSS_RADIO
VSS_RADIO
VSS_RADIO

VSS_AUDI O
VSS_AUDI O

SPKR_A_N
SPKR_A_P
SPKR_B_N
SPKR_B_P

MIC_BIAS
VSS_ANA
VSS_ANA

MIC_A_N

MIC_A_P

MIC_B_N

MIC_B_P

TEST_EN
VSS_DIG

VSS_DIG
VSS_DIG
VSS_DIG
VSS_DIG
VSS_DIG

VSS_DIG
VSS_DIG
VSS_LO
VSS_LO

LO_REF
TP9
BAT_N
BAT_N

AIO[0]
AIO[1]
SUBS

SUBS

SUBS

SUBS

SUBS
SUBS
SUBS

SUBS
SUBS
SUBS

SUBS
SUBS

SUBS
SUBS
SUBS

SUBS

SUBS
SUBS
G3
F2
G2
H2
J2
N3
N4
L2
L3

C6
N7

B10
C10

K2
J3
K3
L4
M4
B5
C5
L5
A6
B6
L6
M6
A7
B7
L7
M7
L8
N8

C2
C3
C4

AUDIO_DCPL C1

A3

B3

D1

D2

B1

B2

A1

A2

A5

M5

N6

N5

G12
A10
C11
K11
L11
A9

C12
C13 22n

C14 1u
47n

MIC_BIAS
C15 C16 C17 C18
SP1 1u 1u 1u 1u

TP10 TP11 R9

R10 2k2
CONNECT ALL AT STAR POINT TO
2k2
16/32 Ohms C19 C20

SP2
15p 15p

L3 L4

G-TW-0000759.3.2
15nH 15nH

TP12 TP13
16/32 Ohms

MIC1 MIC2

Figure 12.1: Example Application Schematic

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 Electrical Characteristics

13 Electrical Characteristics
13.1 Absolute Maximum Ratings
Rating Min Max Unit

Storage Temperature -40 105 °C

Core Supply VDD_ANA, VDD_AUDIO, VDD_CORE,

-0.4 1.65 V
Voltage VDD_LO and VDD_RADIO

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

VDD_PADS, VDD_PIO and VDD_USB -0.4 3.6 V
I/O Voltage
VDD_MEM -0.4 1.95 V

VREGIN_L -0.4 2.7 V

VREGIN_AUDIO -0.4 2.7 V

VREGIN_H, VREGENABLE_H and

-0.4 4.9 V
VREGENABLE_L
Supply Voltage
BAT_P -0.4 4.4 V

LED[1:0] -0.4 4.4 V

VDD_CHG -0.4 6.5 V

Other Terminal Voltages VSS - 0.4 VDD + 0.4 V

13.2 Recommended Operating Conditions

Operating Condition Min Typ Max Unit

Operating Temperature Range(a) -40 20 85 °C

VDD_ANA,
Core Supply VDD_AUDIO,
1.42 1.50 1.57 V
Voltage VDD_CORE, VDD_LO
and VDD_RADIO

VDD_PADS, VDD_PIO
1.70 3.30 3.60 V
I/O Supply and VDD_USB
Voltage
VDD_MEM 1.70 1.80 1.95 V

(a) For radio performance over temperature, see BlueCore5‑Multimedia Flash (16Mb) Performance Specification.

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 Electrical Characteristics

13.3 Input/Output Terminal Characteristics

Note:
For all I/O terminal characteristics:
■ VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO at 1.50V unless shown otherwise.
■ VDD_PADS, VDD_PIO and VDD_USB at 3.30V unless shown otherwise.
■ Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.

13.3.1 High-voltage Linear Regulator

Normal Operation Min Typ Max Unit

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Input voltage 2.7 - 5.5(a) V

Output voltage (Iload = 100mA / VREGIN_H = 3.0V) 1.70 1.80 1.95 V

Temperature coefficient -300 0 300 ppm/°C

Output noise(b) (c) - - 1 mV rms

Load regulation (100µA < Iload < 200mA ), ΔVout - - 5 mV

Settling time(b) (d) - - 50 μs

Output current - - 200 mA

Minimum load current 5 - - µA

Drop-out voltage ( Iload = 200mA) - - 900 mV

Quiescent current (excluding load, Iload < 1mA) 30 50 60 μA

Low-power Mode (e)

Quiescent current (excluding load, Iload < 100μA) 11 15 21 μA

(a) Short-term operation up to 5.5V is permissible without damage and without the output voltage rising sufficiently to damage the rest of the
device, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.9V. 5.5V can only be tolerated
for short periods.
(b) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(c) Frequency range 100Hz to 100kHz.
(d) 10mA to 200mA pulsed load.
(e) The regulator is in low power mode when the chip is in deep sleep mode, or in reset.

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 Electrical Characteristics

13.3.2 Low-voltage Linear Regulator

Normal Operation Min Typ Max Unit

Input voltage 1.70 1.80 1.95 V

Output voltage (Iload = 70mA / VREGIN_L = 1.7V) 1.42 1.50 1.57 V

Temperature coefficient -300 0 300 ppm/°C

Output noise(a) (b) - - 1 mV rms

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Load regulation (100µA < Iload < 90mA ), ΔVout - - 5 mV

Load regulation (100µA < Iload < 115mA ), ΔVout - - 25 mV

Settling time(a) (c) - - 50 μs

Output current - - 115 mA

Minimum load current 5 - 100 µA

Quiescent current (excluding load, Iload < 1mA) 50 90 150 μA

Low-power Mode (d)

Quiescent current (excluding load, Iload < 100μA) 5 8 15 μA

(a) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors
(b) Frequency range 100Hz to 100kHz
(c) 1mA to 115mA pulsed load
(d) The regulator is in low power mode when the chip is in deep sleep mode, or in reset

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 Electrical Characteristics

13.3.3 Low-voltage Linear Audio Regulator

Normal Operation Min Typ Max Unit

Input voltage 1.70 1.80 1.95 V

Output voltage (Iload = 70mA / VREGIN_AUDIO = 1.7V) 1.42 1.50 1.57 V

Temperature coefficient -300 0 300 ppm/°C

Output noise(a) (b) - - 1 mV rms

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Load regulation (100µA < Iload < 70mA ), ΔVout - - 5 mV

Settling time(a) (c) - - 50 μs

Output current - - 70 mA

Minimum load current 5 - 100 µA

Quiescent current (excluding load, Iload < 1mA) 25 30 50 μA

Low-power Mode (d)

Quiescent current (excluding load, Iload < 100μA) 5 8 15 μA

(a) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors
(b) Frequency range 100Hz to 100kHz
(c) 1mA to 70mA pulsed load
(d) The regulator is in low power mode when the chip is in deep sleep mode, or in reset

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 Electrical Characteristics

13.3.4 Reset

Power-on Reset Min Typ Max Unit

VDD_CORE falling threshold 1.13 1.25 1.30 V

VDD_CORE rising threshold 1.20 1.30 1.35 V

Hysteresis 0.05 0.10 0.15 V

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

13.3.5 Regulator Enable

Switching Threshold Min Typ Max Unit

VREGENABLE_H

Rising threshold 0.50 - 0.95 V

Falling threshold 0.35 - 0.80 V

Hysteresis 0.14 - 0.28 V

VREGENABLE_L

Rising threshold 0.50 - 0.95 V

Falling threshold 0.35 - 0.80 V

Hysteresis 0.14 - 0.28 V

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 Electrical Characteristics

13.3.6 Switch-mode Regulator

Switch-mode Regulator Min Typ Max Unit

Input voltage 2.5 - 4.4 V

Output voltage (Iload = 70mA) 1.70 1.80 1.90 V

Temperature coefficient -250 - 250 ppm/°C

Normal Operation

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Output ripple - - 10 mV rms

Transient settling time(a) - - 50 μs

Maximum load current 200 - - mA

Conversion efficiency (Iload = 70mA) - 90 - %

Switching frequency(b) - 1.333 - MHz

Start-up current limit(c) 30 50 80 mA

Low-power Mode (d)

Output ripple - - 1 mV rms

Transient settling time(e) - - 700 μs

Maximum load current 5 - - mA

Minimum load current 1 - - µA

Conversion efficiency (Iload = 1mA ) - 80 - %

Switching frequency(f) 50 - 150 kHz

(a) For step changes in load of 30 to 80mA and 80 to 30mA

(b) Locked to crystal frequency
(c) Current is limited on start-up to prevent excessive stored energy in the filter inductor
(d) The regulator is in low power mode when the chip is in deep sleep mode, or in reset
(e) 100μA to 1mA pulsed load
(f) Defines minimum period between pulses. Pulses are skipped at low current loads

Note:
The external inductor used with the switch-mode regulator must have an ESR in the range 0.3Ω to 0.7Ω:
■ Low ESR < 0.3Ω causes instability.
■ High ESR > 0.7Ω derates the maximum current.

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 Electrical Characteristics

13.3.7 Battery Charger

Battery Charger Min Typ Max Unit

Input voltage 4.5 - 6.5 V

Charging Mode (BAT_P rising to 4.2V) Min Typ Max Unit

Supply current(a) - 4.5 6 mA

Battery trickle charge current(b) - 4 - mA

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Headroom(e) > 0.7V - 140 - mA
Maximum battery fast charge
current (I-CTRL = 15)(c) (d)
Headroom = 0.3V - 120 - mA

Headroom > 0.7V - 40 - mA

Minimum battery fast charge
current (I-CTRL = 0)(c) (d)
Headroom = 0.3V - 35 - mA

Fast charge step size

Spread ±17% - 6.3 - mA
(I-CTRL = 0 to 15)

Trickle charge voltage threshold - 2.9 - V

Float voltage (with correct trim value set), VFLOAT (f) 4.17 4.2 4.23 V

Float voltage trim step size(f) - 50 - mV

Battery charge termination current, % of fast charge

5 10 20 %
current

(a) Current into VDD_CHG does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) BAT_P < trickle charge voltage threshold
(c) Charge current can be set in 16 equally spaced steps
(d) Trickle charge threshold < BAT_P < Float voltage
(e) Where headroom = VDD_CHG - BAT_P
(f) Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery charger by
firmware during boot-up sequence

Standby Mode (BAT_P falling from 4.2V) Min Typ Max Unit

Supply current(a) - 1.5 2 mA

Battery current - -5 - µA

Battery recharge hysteresis(b) 100 - 200 mV

(a) Current into VDD_CHG; does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) Hysteresis of (VFLOAT - BAT_P) for charging to restart

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 Electrical Characteristics

Shutdown Mode (VDD_CHG too low or disabled by

Min Typ Max Unit
firmware)

Supply current - 1.5 2 mA

Battery current -1 - 0 µA

VDD_CHG rising - 3.90 - V

VDD_CHG under-voltage
threshold
VDD_CHG falling - 3.70 - V

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

VDD_CHG rising - 0.22 - V
VDD_CHG - BAT_P lockout
threshold
VDD_CHG falling - 0.17 - V

13.3.8 Digital Terminals

Supply Voltage Levels Min Typ Max Unit

VDDPRE Pre-driver supply voltage 1.4 1.5 1.6 V

Full spec. 3.0 3.3 3.6 V

VDD I/O supply
voltage (post-driver)
Reduced spec. 1.7 - 3.0 V

Input Voltage Levels Min Typ Max Unit

VIL input logic level low -0.3 - 0.25 x VDD V

VIH input logic level high 0.625 x VDD - VDD + 0.3 V

VSCHMITT Schmitt voltage 0.25 x VDD - 0.625 x VDD V

Output Voltage Levels Min Typ Max Unit

VOL output logic level low, lOL = 4.0mA 0 - 0.125 V

VOH output logic level high, lOH = -4.0mA 0.75 x VDD - VDD V

Input and Tristate Currents Min Typ Max Unit

Ii input leakage current at Vin = VDD or 0V -100 0 100 nA

Ioz tristate output leakage current at Vo = VDD or 0V -100 0 100 nA

With strong pull-up -100 -40 -10 μA

With strong pull-down 10 40 100 μA

With weak pull-up -5 -1.0 -0.2 μA

With weak pull-down -0.2 1.0 5.0 μA

CI input capacitance 1.0 - 5.0 pF

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 Electrical Characteristics

Resistive Strength Min Typ Max Unit

Rpuw weak pull-up strength at VDD - 0.2V 0.5 - 2 MΩ

Rpdw weak pull-down strength at 0.2V 0.5 - 2 MΩ

Rpus strong pull-up strength at VDD - 0.2V 10 - 50 kΩ

Rpds strong pull-down strength at 0.2V 10 - 50 kΩ

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

13.3.9 LED Driver Pads

LED Driver Pads Min Typ Max Unit

Off current - 1 2 µA

On resistance VPAD < 0.5V - 20 33 Ω

On resistance, pad enabled

VPAD < 0.5V - 20 50 Ω
by battery charger

13.3.10 USB

Min Typ Max Unit

VDD_USB for correct USB operation 3.1 - 3.6 V

Input Threshold

VIL input logic level low 0.3 x

- - V
VDD_USB

VIH input logic level high 0.7 x

- - V
VDD_USB

Input Leakage Current

VSS_DIG < VIN < VDD_USB(a) -1 1 5 µA

CI input capacitance 2.5 - 10.0 pF

Output Voltage Levels to Correctly Terminated USB Cable

VOL output logic level low 0.0 - 0.2 V

VOH output logic level high 2.8 - VDD_USB V

(a) Internal USB pull-up disabled

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 Electrical Characteristics

13.3.11 Auxiliary ADC

Auxiliary ADC Min Typ Max Unit

Resolution - - 10 Bits

Input voltage range(a) 0 - VDD_ANA V

INL -1 - 1 LSB
Accuracy
(Guaranteed monotonic)
DNL 0 - 1 LSB

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Offset -1 - 1 LSB

Gain error -0.8 - 0.8 %

Input bandwidth - 100 - kHz

Conversion time - 2.5 - µs

Samples/
Sample rate(b) - - 700
s

(a) LSB size = VDD_ANA/1023

(b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.

13.3.12 Auxiliary DAC

Auxiliary DAC Min Typ Max Unit

Resolution - - 8 Bits

Average output step size(a) 12.5 14.5 17.0 mV

Output Voltage monotonic(a)

Voltage range (IO = 0mA) VSS_DIG - VDD_PIO V

Current range -10.0 - 0.1 mA

Minimum output voltage (IO=100μA) 0.0 - 0.2 V

VDD_PIO -
Maximum output voltage (IO=10mA) - VDD_PIO V
0.3

High impedance leakage current -1 - 1 µA

Offset -220 - 120 mV

Integral non-linearity(a) -2 - 2 LSB

Settling time (50pF load) - - 10 µs

(a) Specified for an output voltage between 0.2V and VDD_PIO - 0.2V. Output is high impedance when chip is in deep sleep mode.

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 Electrical Characteristics

13.3.13 Clocks

Crystal Oscillator Min Typ Max Unit

Crystal frequency(a) 16 26 26 MHz

Digital trim range(b) 5.0 6.2 8.0 pF

Trim step size(b) - 0.1 - pF

Transconductance 2.0 - - mS

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Negative resistance(c) 870 1500 2400 Ω

External Clock Min Typ Max Unit

Input frequency(d) 12 26 52 MHz

Clock input level(e) 0.4 - VDD_ANA V pk-pk

Edge jitter (allowable jitter), at zero crossing - - 15 ps rms

XTAL_IN input impedance - ≥10 - kΩ

XTAL_IN input capacitance - ≤4 - pF

(a) Integer multiple of 250kHz

(b) Difference between the internal capacitance at minimum and maximum settings of the internal digital trim
(c) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
(d) Clock input can be any frequency from 12MHz to 52MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of 14.40, 15.36, 16.2, 16.8,
19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(e) Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA. A DC blocking
capacitor is required between the signal and XTAL_IN.

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 Electrical Characteristics

13.3.14 Stereo Codec: Analogue to Digital Converter

Analogue to Digital Converter

Parameter Conditions Min Typ Max Unit

Resolution - - - 16 Bits

Input Sample
- 8 - 44.1 kHz
Rate, Fsample

Fsample

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

8kHz - 79 - dB
fin = 1kHz
11.025kHz - 77 - dB
B/W = 20Hz→20kHz
Signal to Noise
A-Weighted 16kHz - 76 - dB
Ratio, SNR(a)
THD+N < 1%
150mVpk-pk input 22.050kHz - 76 - dB

32kHz - 75 - dB

44.1kHz - 75 - dB

Digital Gain Digital Gain Resolution = 1/32dB -24 - 21.5 dB

Analogue Gain Analogue Gain Resolution = 3dB - - 42 dB

Input full scale at maximum gain (differential) - 4 - mV rms

Input full scale at minimum gain (differential) - 800 - mV rms

3dB Bandwidth - 20 - kHz

Microphone mode input impedance - 6.0 - kΩ

THD+N (microphone input) @ 30mV rms input - 0.04 - %

(a) Improved SNR performance can be achieved at the expense of current consumption. See Optimising BlueCore5-Multimedia ADC
Performance Application Note for details.

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 Electrical Characteristics

13.3.15 Stereo Codec: Digital to Analogue Converter

Digital to Analogue Converter

Parameter Conditions Min Typ Max Unit

Resolution - - - 16 Bits

Output Sample
- 8 - 48 kHz
Rate, Fsample

Fsample

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

8kHz - 95 - dB

fin = 1kHz 11.025kHz - 95 - dB

B/W = 20Hz→20kHz
16kHz - 95 - dB
Signal to Noise A-Weighted
Ratio, SNR THD+N < 0.01%
22.050kHz - 95 - dB
0dBFS signal
Load = 100kΩ 32kHz - 95 - dB

44.1kHz - 95 - dB

48kHz - 95 - dB

Digital Gain Digital Gain Resolution = 1/32dB -24 - 21.5 dB

Analogue Gain Analogue Gain Resolution = 3dB 0 - -21 dB

Output voltage full-scale swing (differential)(a) - 750 - mV rms

Resistive 16(8) - O.C. Ω

Allowed Load
Capacitive - - 500 pF

THD+N 100kΩ load - - 0.01 %

THD+N 16Ω load - - 0.1 %

SNR (Load = 16Ω, 0dBFS input relative to digital silence) - 95 - dB

(a) Any combination of gain (digital and / or analogue) and input signal which results in the output signal level exceeding the minimum or maximum
signal level (analogue or digital) could result in distortion.

13.4 ESD Precautions

BlueCore5‑Multimedia Flash (16Mb) is classified as a:
■ JESD22-A114 class 1A (I/O) and class 2 (RF, Supplies, Audio I/O and USB I/O) product:
■ USB I/O includes the USB_DP and USB_DN pins.
■ Audio I/O includes the MIC_B_P, MIC_B_N, MIC_A_P, MIC_A_N, SPKR_B_N, SPKR_B_P,
AU_REF_DCPL, SPKR_A_N and SPKR_A_P pins.
■ JESD22-A115 class A product
Important Note:

Apply ESD static handling precautions during manufacturing.

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 Power Consumption

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

14 Power Consumption
Current

Role Connection Audio Packet Type Description VREGIN_L = 1.8V VDD_CHG = 3.6V Unit

16MHz 32MHz 16MHz 32MHz

Stand-by - Host connection 0.07 0.08 0.06 0.07 mA

Page Scan - Interval = 1280ms 0.46 0.47 0.31 0.32 mA

Inquiry scan = 1280ms

Inquiry and Page Scan - 0.92 0.88 0.51 0.54 mA
Page scan = 1280ms

Master ACL - No traffic 4.2 4.2 2.6 2.7 mA

Master ACL - File transfer TX 8.9 9.1 5.1 5.2 mA

Master ACL - Sniff = 40ms 1.8 1.8 1.1 1.1 mA

Master ACL - Sniff = 1280ms 0.21 0.20 0.15 0.14 mA

Master eSCO EV3 - 21 22 12 12 mA

Master eSCO EV3 Setting S1 23 23 13 13 mA

Master eSCO 2 EV3 Setting S2 22 22 12 12 mA

Master eSCO 2 EV3 Setting S3 16 17 9.0 9.1 mA

Master eSCO EV5 - 16 16 8.8 8.9 mA

Master SCO HV1 - 39 41 22 23 mA

Master SCO HV3 - 21 22 12 12 mA

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 Power Consumption

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Current

Role Connection Audio Packet Type Description VREGIN_L = 1.8V VDD_CHG = 3.6V Unit

16MHz 32MHz 16MHz 32MHz

Master SCO HV3 Sniff = 30ms 21 22 12 12 mA

Slave ACL - No Traffic 15 15 8.2 8.2 mA

Slave ACL - File transfer RX 20 18 10 9.44 mA

Slave ACL - Sniff = 40ms 1.5 1.6 0.96 1.0 mA

Slave ACL - Sniff = 1280ms 0.27 0.27 0.18 0.18 mA

Slave eSCO EV3 - 25 25 13 14 mA

Slave eSCO EV3 Setting S1 27 28 14 15 mA

Slave eSCO 2 EV3 Setting S2 26 26 14 15 mA

Slave eSCO 2 EV3 Setting S3 23 24 13 13 mA

Slave eSCO EV5 - 21 22 12 12 mA

Slave SCO HV1 - 39 41 22 23 mA

Slave SCO HV3 - 27 28 14 15 mA

Slave SCO HV3 Sniff = 30ms 21 21 11 12 mA

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 Power Consumption

14.1 Kalimba DSP and Codec Typical Average Current Consumption

DSP Average Unit

Minimum (NOP) 0.11 mA/MIPS

DSP core (including PM memory access)
Maximum (MAC) 0.32 mA/MIPS

DSP memory access (DM1 or DM2) 0.08 mA/MIPS

14.2 Typical Peak Current at 20°C

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Device Activity / State Typ Unit

Peak current during cold boot 45 mA

Master TX peak current 45 mA

Master RX peak current 45 mA

Slave TX peak current 45 mA

Slave RX peak current 45 mA

14.3 Conditions
■ Power consumption measurements based on BlueCore5-Multimedia Flash (8Mb).
■ Host interface = UART
■ Baud rate = 115200
■ Supply = 1.8V in to VREGIN_L and VREGIN_AUDIO
■ AFH switched OFF
■ No audio load
■ RF Output power = 0dBm
■ VM OFF
■ eSCO settings:
■ EV3 and EV5 = no retry
■ Setting S1 = optimised for power consumption
■ Firmware build ID = 4508

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 CSR Green Semiconductor Products and RoHS Compliance

15 CSR Green Semiconductor Products and RoHS Compliance

15.1 RoHS Statement
BlueCore5‑Multimedia Flash (16Mb) where explicitly stated in this Data Sheet meets the requirements of Directive
2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).

15.1.1 List of Restricted Materials

BlueCore5‑Multimedia Flash (16Mb) is compliant with RoHS in relation to the following substances:
■ Cadmium
■ Lead

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ Mercury
■ Hexavalent chromium
■ Polybrominated Biphenyl
■ Polybrominated Diphenyl Ether
In addition, the following substances are not intentionally added to BlueCore5‑Multimedia Flash (16Mb) devices:
■ Halogenated flame retardant
■ Antimony (Sb) and Compounds, including Antimony Trioxide flame retardant
■ Polybrominated Diphenyl and Biphenyl Oxides
■ Tetrabromobisphenol-A bis (2,3-dibromopropylether)
■ Asbestos or Asbestos compounds
■ Azo compounds
■ Organic tin compounds
■ Mirex
■ Polychlorinated napthelenes
■ Polychlorinated terphenyls
■ Polychlorinated biphenyls
■ Polychlorinated/Short chain chlorinated paraffins
■ Polyvinyl Chloride (PVC) and PVC blends
■ Formaldehyde
■ Arsenic and compounds (except as a semiconductor dopant)
■ Beryllium and its compounds
■ Ethylene Glycol Monomethyl Ether or its acetate
■ Ethylene Glycol Monoethyl Ether or its acetate
■ Halogenated dioxins and furans
■ Persistent Organic Pollutants (POP), including Perfluorooctane sulphonates
■ Red phosphorous
■ Ozone Depleting Chemicals (Class I and II): Chlorofluorocarbons (CFC) and Halons
■ Radioactive substances
For further information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products.

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 CSR Synergy and Bluetooth Software Stack

16 CSR Synergy and Bluetooth Software Stack

BlueCore5‑Multimedia Flash (16Mb) is supplied with Bluetooth v2.1 + EDR specification compliant stack firmware,
which runs on the internal RISC MCU. The stack firmware is compatible with CSR's póåÉêÖó» wireless Host Software
Platform, for more information see http://www.csr.com/synergy.
The BlueCore5‑Multimedia Flash (16Mb) software architecture allows Bluetooth processing and the application
program to be shared in different ways between the internal RISC MCU and an external host processor. The upper
layers of the Bluetooth stack, above the HCI, can be run either on-chip or on the host processor.

16.1 BlueCore HCI Stack

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Program memory
HCI

LM

LC

Bluetooth stack
48KB RAM
MCU

USB

Host I/O
Host
UART Radio

G-TW-0000236.3.2
PCM / SPDIF / I2S Digital audio
2
Microphone or speaker Analogue audio

Figure 16.1: BlueCore HCI Stack

Note:

Program Memory in Figure 16.1 is internal flash.

In the implementation shown in Figure 16.1 the internal MCU runs the Bluetooth stack up to the HCI. The Host
processor must provide all upper layers including the application.

16.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality

CSR supports the following Bluetooth v2.1 + EDR specification functionality:
■ Secure simple pairing
■ Sniff subrating
■ Encryption pause resume
■ Packet boundary flags
■ Encryption
■ Extended inquiry response

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 CSR Synergy and Bluetooth Software Stack

As well as the following mandatory functions of Bluetooth v2.0 + EDR specification:

■ AFH, including classifier
■ Faster connection: enhanced inquiry scan (immediate FHS response)
■ LMP improvements
■ Parameter ranges
And optional Bluetooth v2.0 + EDR specification functionality:
■ AFH as master and automatic channel classification
■ Fast connect: interlaced inquiry and page scan plus RSSI during inquiry
■ eSCO, eV3 + CRC, eV4, eV5
■ SCO handle

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ Synchronisation
The firmware was written against the Bluetooth v2.1 + EDR specification:
■ Bluetooth components:
■ Baseband including LC
■ LM
■ HCI
■ Standard UART HCI Transport Layers
■ All standard Bluetooth radio packet types
■ Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps
■ Operation with up to 7 active slaves (this is the maximum Bluetooth v2.1 + EDR specification allows)
■ Scatternet v2.5 operation
■ Maximum number of simultaneous active ACL connections: 7
■ Maximum number of simultaneous active SCO connections: 3 (BlueCore5‑Multimedia Flash (16Mb)
supports all combinations of active ACL and SCO channels for both master and slave operation, as
specified by the Bluetooth v2.1 + EDR specification)
■ Operation with up to 3 SCO links, routed to one or more slaves
■ All standard SCO voice coding, plus transparent SCO
■ Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan
■ All standard pairing, authentication, link key and encryption operations
■ Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold
■ Dynamic control of peers' transmit power via LMP
■ Master/slave switch
■ Broadcast
■ Channel quality driven data rate
■ All standard Bluetooth test modes

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 CSR Synergy and Bluetooth Software Stack

16.1.2 Key Features of the HCI Stack: Extra Functionality

The firmware extends the standard Bluetooth functionality with the following features:
■ Supports BCSP, a proprietary, reliable alternative to the standard Bluetooth UART Host Transport
■ Supports H4DS, a proprietary alternative to the standard Bluetooth UART Host Transport, supporting deep
sleep for low-power applications
■ Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BCCMD, provides:
■ Access to BlueCore5‑Multimedia Flash (16Mb) general-purpose PIO port
■ The negotiated effective encryption key length on established Bluetooth links
■ Access to the firmware random number generator

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

■ Controls to set the default and maximum transmit powers; these can help minimise interference
between overlapping, fixed-location piconets
■ Dynamic UART configuration
■ Bluetooth radio transmitter enable/disable. A simple command connects to a dedicated hardware
switch that determines whether the radio can transmit.
■ The firmware can read the voltage on a pair of BlueCore5‑Multimedia Flash (16Mb) external pins. This is
normally used to build a battery monitor.
■ A block of BCCMD commands provides access to the BlueCore5‑Multimedia Flash (16Mb) persistent store
configuration database. The database sets the BlueCore5‑Multimedia Flash (16Mb) Bluetooth address,
Class of Device, Bluetooth radio (transmit class) configuration, SCO routing, LM, etc.
■ A UART break condition can be used in three ways:
■ Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
■ Presenting a break condition at boot time can hold the IC in a low power state, preventing normal
initialisation while the condition exists
■ With BCSP, the firmware can be configured to send a break to the host before sending data. (This is
normally used to wake the host from a deep sleep state.)
■ A block of Bluetooth radio test or BIST commands allows direct control of the BlueCore5‑Multimedia Flash
(16Mb) radio. This aids the development of modules' radio designs, and can be used to support
Bluetooth qualification.
■ Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
■ SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed
over the PCM interface (at the same time as routing any remaining SCO channels over HCI).
Note:

Always refer to the Firmware Release Note for the specific functionality of a particular build.

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 CSR Synergy and Bluetooth Software Stack

16.2 Stand-alone BlueCore5‑Multimedia Flash (16Mb) and Kalimba DSP

Applications
Internal MCU Kalimba DSP

VM Application Software DSP Application

Program Memory
RFCOMM SDP

L2CAP
HCI

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

LM

LC DSP Control

Baseband
48KB RAM DM1 DM2 PM
MCU

USB

Host Host I/O

UART Radio

G-TW-0004759.1.1
PCM / SPDIF / I2S Digital Audio
2
Microphone or Speaker Analogue Audio

Figure 16.2: Stand-alone BlueCore5‑Multimedia Flash (16Mb) and Kalimba DSP Applications
Note:

Program memory in Figure 16.2 is internal flash.

In Figure 16.2, this version of the stack firmware requires no host processor (but can use a host processor for
debugging etc. as Figure 16.2 shows). The software layers for the application software run on the internal MCU in
a protected user software execution environment known as a VM and the DSP application code runs from the
DSP program memory RAM.
CSR provides a number of SDKs focused on end product use cases. These include Mono Headsets, Stereo
Headsets, Audio Adaptors, Car Kits. The SDKs include firmware components, applications and appropriate profile
support. For more information see www.csrsupport.com.

16.3 Host-Side Software

BlueCore5‑Multimedia Flash (16Mb) can be ordered with companion host-side software:
■ BlueCore5-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-
side stack together with IC hardware described in this document.
■ BlueCore5-Mobile includes software for a full host-side stack designed for modern ARM chip-based mobile
handsets together with IC hardware described in this document.

16.4 eXtension
A wide range of software options is available from 3rd parties through the CSR eXtension partner program, see
http://www.csr.com/eXtension.

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 Ordering Information

17 Ordering Information
Package
Interface Version Shipment Order Number
Type Size
Method

LFBGA 120-ball 7 x 7 x 1.3mm,

UART and USB Tape and reel BC57G687C‑GITM‑E4
(Pb free) 0.5mm pitch

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Note:

Minimum order quantity is 2kpcs taped and reeled.

Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your
local sales account manager or representative.
To contact a CSR representative, email [email protected] or go to www.csr.com/contacts

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 Tape and Reel Information

18 Tape and Reel Information

For tape and reel packing and labelling see IC Packing and Labelling Specification.

18.1 Tape Orientation

Figure 18.1 shows the BlueCore5‑Multimedia Flash (16Mb) packing tape orientation.

Circular Holes
Pin A1 Marker

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

A

A=B

G-TW-0002434.2.2
B

User Direction of Feed

Figure 18.1: BlueCore5‑Multimedia Flash (16Mb) Tape Orientation

18.2 Tape Dimensions

G-TW-0002798.2.2

Figure 18.2: Tape Dimensions

A0 B0 K0 Unit Notes

1. 10 sprocket hole pitch cumulative tolerance ±0.2

2. Camber in compliance with EIA 481
7.30 7.30 2.10 mm
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole

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 Tape and Reel Information

18.3 Reel Information

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

G-TW-0000386.3.2
Figure 18.3: Reel Dimensions

Package Tape A W2 W3
B C D Min N Min W1 Units
Type Width Max Max Min Max

7x7x
13.0 16.4
1.3mm 16 332 1.5 20.2 50 19.1 16.4 19.1 mm
(0.5/-0.2) (3.0/-0.2)
LFBGA

18.4 Moisture Sensitivity Level

BlueCore5‑Multimedia Flash (16Mb) is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-
STD-020.

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 Document References

19 Document References
Document Reference, Date

BlueCore5 Charger Description and Calibration

CS-113282-ANP
Procedure Application Note

BlueCore5‑Multimedia Flash (16Mb) Performance

CS-129296-SPP
Specification

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

Bluetooth and IEEE 802.11 b/g Co-existence Solutions
bcore-an-066P
Overview

Bluetooth and USB Design Considerations CS-101412-AN

Core Specification of the Bluetooth System v2.1 + EDR, 26 July 2007

Electrostatic Discharge (ESD) Sensitivity Testing

JESD22-A114
Human Body Model (HBM)

IC Packing and Labelling Specification CS-112584-SPP

Moisture / Reflow Sensitivity Classification for

IPC / JEDEC J-STD-020
Nonhermitic Solid State Surface Mount Devices

Optimising BlueCore5-Multimedia ADC Performance

CS-120059-AN
Application Note

Selection of I2C EEPROMS for Use with BlueCore bcore-an-008P

Test Suite Structure (TSS) and Test Purposes (TP)

RF.TS/2.1.E.0, 27 December 2006
System Specification 1.2/2.0/2.0 + EDR/ 2.1/2.1 + EDR

Typical Solder Reflow Profile for Lead-free Device CS-116434-ANP

Universal Serial Bus Specification v2.0, 27 April 2000

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 Terms and Definitions

Terms and Definitions

Term Definition
3G 3rd Generation of mobile communications technology
802.11™ WLAN specification defined by a working group within the IEEE
8DPSK 8-phase Differential Phase Shift Keying
π/4 DQPSK π/4 rotated Differential Quaternary Phase Shift Keying
µ-law Audio companding standard (G.711)

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

A-law Audio companding standard (G.711)
AC Alternating Current
ACK ACKnowledge
ACL Asynchronous Connection-oriented
ADC Analogue to Digital Converter
AFC Automatic Frequency Control
AFH Adaptive Frequency Hopping
AGC Automatic Gain Control
ALU Arithmetic logic unit
b Bit
B Byte
BCCMD BlueCore Command
BCSP BlueCore Serial Protocol
BGA Ball Grid Array
BIST Built-In Self-Test
BlueCore® Group term for CSR’s range of Bluetooth wireless technology ICs
Bluetooth® Set of technologies providing audio and data transfer over short-range radio connections
BMC Burst Mode Controller
CDMA Code Division Multiple Access
CFC Chlorofluorocarbon
CMOS Complementary Metal Oxide Semiconductor
codec Coder decoder
CRC Cyclic Redundancy Check
CSR Cambridge Silicon Radio
CTS Clear to Send
CVSD Continuous Variable Slope Delta Modulation
DAC Digital to Analogue Converter
dBm Decibels relative to 1mW
DC Direct Current
DDS Direct Digital Synthesis
DFU Device Firmware Upgrade
DNL Differential Non Linearity (ADC accuracy parameter)
DSP Digital Signal Processor
e.g. exempli gratia, for example
EDR Enhanced Data Rate
EEPROM Electrically Erasable Programmable Read Only Memory

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 Terms and Definitions

Term Definition
eSCO Extended SCO
ESD Electrostatic Discharge
ESR Equivalent Series Resistance
etc et cetera, and the rest, and so forth
FET Field Effect Transistor
FHS Frequency Hop Synchronisation
FSK Frequency Shift Keying
GCI General Circuit Interface

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

GFSK Gaussian Frequency Shift Keying
GSM Global System for Mobile communications
H4DS H4 Deep Sleep
HBM Human Body Model
HCI Host Controller Interface
I²C Inter-Integrated Circuit Interface
I²S Inter-Integrated Circuit Sound
i.e. Id est, that is
I/O Input/Output
IC Integrated Circuit
IEEE Institute of Electronic and Electrical Engineers
IF Intermediate Frequency
IIR Infinite Impulse Response (filter)
INL Integral Non Linearity (ADC accuracy parameter)
IQ In-Phase and Quadrature
ISDN Integrated Services Digital Network
JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology
Association)
Kalimba An open platform DSP co-processor, enabling support of enhanced audio applications, such
as echo and noise suppression, and file compression / decompression
LC An inductor (L) and capacitor (C) network
LC Link Controller
LCD Liquid-Crystal Display
LED Light-Emitting Diode
LM Link Manager
LMP Link Manager Protocol
LNA Low Noise Amplifier
LSB Least-Significant Bit (or Byte)
MAC Multiplier and ACcumulator
Mbps Megabits per second
MCU MicroController Unit
MIPS Million Instructions Per Second
MISO Master In Slave Out
MMU Memory Management Unit
MSB Most Significant Bit (or Byte)
N/A Not Applicable

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 Terms and Definitions

Term Definition
NSMD Non Solder Mask Defined
O.C. Open Circuit
PA Power Amplifier
PC Personal Computer
PCB Printed Circuit Board
PCM Pulse Code Modulation
PD Pull-down
PIO Programmable Input/Output

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

plc Public Limited Company
POP Persistent Organic Pollutants
ppm parts per million
PS Key Persistent Store Key
PSRR Power Supply Rejection Ratio
PU Pull-up
PVC Poly Vinyl Chloride
RAM Random Access Memory
RC Resistor Capacitor
RF Radio Frequency
RISC Reduced Instruction Set Computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/EC)
RSSI Received Signal Strength Indication
RTS Request To Send
RX Receive or Receiver
SBC Sub-band Coding
SCO Synchronous Connection-Oriented
SDK Software Development Kit
SIG (Bluetooth) Special Interest Group
SNR Signal-to-Noise Ratio
S/PDIF Sony/Philips Digital InterFace (also IEC 958 type II, part of IEC-60958). An interface designed
to transfer stereo digital audio signals between various devices and stereo components with
minimal loss.
SPI Serial Peripheral Interface
SPL Sound Pressure Level
TCXO Temperature Compensated crystal Oscillator
THD+N Total Harmonic Distortion and Noise
TP Test Purposes
TSS Test Suite Structure
TX Transmit or Transmitter
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus

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 Terms and Definitions

Term Definition
VCO Voltage Controlled Oscillator
VM Virtual Machine
VoIP Voice over Internet Protocol
W-CDMA Wideband Code Division Multiple Access
WCS Wireless Coexistence System
WLAN Wireless Local Area Network

_äìÉ`çêÉRJjìäíáãÉÇá~=cä~ëÜ=ENSjÄF Data Sheet

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