Embedded system designers must take into account many considerations when selecting a Flash

memory: which type of Flash architecture to use, whether to select a serial interface or a parallel
interface, does it need error correction code (ECC), and so on. If the processor or controller supports
only one type of interface, this limits the options so the memory may be easy to select. However, this
is often not the case. For example, some FPGAs support serial NOR Flash, parallel NOR Flash, and
NAND Flash memory to store configuration data. This same memory can be used to store user data,
which makes selecting the right memory to use more difficult. In this article series, the different
aspects of Flash memories will be discussed, beginning with the differences between NOR Flash
and NAND Flash.

Memory Architecture

Flash memories store information in memory cells made from floating gate transistors. The names of
the technologies explain the way the memory cells are organized. In NOR Flash, one end of each
memory cell is connected to the source line and the other end directly to a bit line resembling a NOR
Gate. In NAND Flash, several memory cells (typically eight cells) are connected in series similar to a

click for
larger image
Figure 1: NOR Flash (left) has an architecture resembling a NOR gate. Similarly, NAND Flash (right)
resembles a NAND gate. (Source: Cypress)

The NOR Flash architecture provides enough address lines to map the entire memory range. This
gives the advantage of random access and short read times, which makes it ideal for code
execution. Another advantage is 100% known good bits for the life of the part. Disadvantages
include larger cell size resulting in a higher cost per bit and slower write and erase speeds. For more
details on how NOR Flash can be used in embedded systems, see An Overview of Parallel NOR
Flash Memory.

NAND Flash, in contrast, has a much smaller cell size and much higher write and erase speeds
compared to NOR Flash. Disadvantages include the slower read speed and an I/O mapped type or
indirect interface, which is more complicated and does not allow random access. It is important to
note that code execution from NAND Flash is achieved by shadowing the contents to a RAM, which
is different than code execution directly from NOR Flash. Another major disadvantage is the
presence of bad blocks. NAND Flash typically have 98% good bits when shipped with additional bit
failure over the life of the part, thus requiring the need for error correcting code (ECC) functionality
within the device.

Memory Capacity

NAND Flash memories are available in much higher densities compared to NOR Flash owing
primarily to its lower cost per bit. NAND Flash memories typically comes in capacities of 1Gb to
16Gb. NOR Flash memories range in density from 64Mb to 2Gb. Because of its higher density,
NAND Flash is used mainly for data storage applications.

Erase, Read & Write

In both NOR and NAND Flash, the memory is organized into erase blocks. This architecture helps
maintain lower cost while maintaining performance. For example, a smaller block size enables faster
erase cycles. The downside of smaller blocks, however, is an increase in die area and memory cost.
Because of its lower cost per bit, NAND Flash can more cost-effectively support smaller erase
blocks compared to NOR Flash. The typical block size available today ranges from 8KB to 32KB for
NAND Flash and 64KB to 256KB for NOR Flash.

Erase operations in NAND Flash are straightforward while in NOR Flash, each byte needs to be
written with ‘0’ before it can be erased. This makes the erase operation for NOR Flash much slower
than for NAND Flash. For example, the S34ML04G2 Cypress NAND Flash requires 3.5ms to erase
a 128KB block while the S70GL02GT Cypress NOR Flash requires ~520ms to erase a similar
128KB sector. This is a difference of nearly 150 times.
 As mentioned earlier, NOR Flash memory has enough address and data lines to map the entire
memory region, similar to how SRAM operates. For example, a 2-Gbit (256MB) NOR Flash with a
16-bit data bus will have 27 address lines, enabling random read access to any memory location. In
NAND Flash, memory is accessed using a multiplexed address and data bus. Typical NAND Flash
memories use an 8-bit or 16-bit multiplexed address/data bus with additional signals such as Chip
Enable, Write Enable, Read Enable, Address Latch Enable, Command Latch Enable, and
Ready/Busy. The NAND Flash needs to provide a command (read, write or erase), followed by the
address and the data. These additional operations makes the random read for NAND Flash much
slower. For example, the S34ML04G2 NAND Flash requires 30µS compared to 120ns for
S70GL02GT NOR Flash. Thus the NAND is 250 times slower.

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Introduction All computer-based systems contain memory.

Memory is where information is stored while waiting to be operated on by the Central Processing Unit
(CPU) of the computer. There are two types of memory: volatile memory and nonvolatile memory.
Volatile memory retains its information only while power is applied to the memory device. The contents
of this memory type may be easily and quickly changed. Nonvolatile memory retains its information
even when no power is applied to the memory device. Although the information in most nonvolatile
memories may be changed, the process involved is much slower than for volatile memory.

Volatile Memory

Volatile memory loses its contents when the device loses power. Random Access Memory (RAM) is the
traditional name used for volatile memory. The name refers to the ability to access any location of the
memory quickly with no particular order of accesses needed. Static RAM (SRAM) and Dynamic RAM
(DRAM) are two examples of volatile memories that have this characteristic. SRAM typically uses six
transistors for each memory bit (cell) to retain data as long as power is being supplied. This makes each
memory cell relatively large and limits SRAM to use in lower density memories. SRAM can provide faster
access to data, use less standby power, and tends to be more expensive than DRAM. DRAM uses a single
transistor and a small capacitor for each bit of memory. Since capacitors do not hold a charge
indefinitely, DRAM cells must be frequently recharged (refreshed) to avoid losing the contents. These
smaller memory cells allow DRAM to be used for high density, low cost memories, but are typically
slower than SRAM.

Nonvolatile Memory

Nonvolatile memory is memory that retains its contents even if the power is lost. Nonvolatile memory
was originally called Read Only Memory (ROM) because its contents were loaded during the
manufacturing process and could be read, but never erased or reprogrammed. Over time, the ability to
erase and reprogram ROM was added in different ways and referred to as Electrically Programmable
ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), and Flash EEPROM, commonly
referred to simply as flash memory. ROM memory is programmed by the way it is manufactured and
stores permanent code and data that is generally used to initialize and operate a computer system.
EPROM can be electrically programmed one byte at a time but is not electrically erasable. It has to be
exposed to ultraviolet (UV) light for about twenty minutes in order to erase all bits in the memory array.
EPROM uses a single transistor for each data bit and can be used in relatively high density memories.
EEPROM is electrically erasable and programmable in-system, one byte at a time, but the memory cells
use more transistors and are larger than those in EPROMs, thus EEPROM has higher costs and lower
density (generally less than 1 Mb). Flash EEPROM memory can be electrically programmed a single byte
or word at a time, but a large group of bytes or words—called a block, sector, or page—are electrically
erased at the same time. Due to the erase operation being much faster than the prior EPROM or
EEPROM devices, these devices came to be called flash erase EEPROM, or simply flash memories. The
flash memory cell uses a single transistor to store one or more bits of information. Flash technology
combines the high density of EPROM with the electrical in-system erase and programmability of
EEPROMs. Flash memory has become the dominant type of nonvolatile memory in use.

Flash Memory Architectures

The two main architectures dominate the flash memory: they are NOR and NAND. NOR is typically used
for code storage and execution. NOR allows quick random access to any location in the memory array,
100% known good bits for the life of the part, and code execution directly from NOR Flash memory.
NAND is used for data storage. NAND flash requires a relatively long initial read access to the memory
array, 98% good bits when shipped with additional bit failure over the life of the part (ECC highly
recommended), program/ erase times are much faster than NOR and NAND cost less per bit than NOR.
Conclusion Cypress flash memory provides a compact, easy to use, nonvolatile code and data storage
solution for electronic products. Cypress provides a broad portfolio of flash memories to suit a wide
range of applications. The memory size, voltage, speed, and package, can be selected to suit the
application.

Basic Operation

There are three basic operations in a flash memory: read (a byte or a word), program (a byte or a word),
and erase (one or more sectors)

Read Cypress provides three types of read operations:

asynchronous read, asynchronous page read, and synchronous burst read. Asynchronous read is a read
not occurring at predetermined or regular intervals (not dependent on a clock). Typical read access time
is 55 to 120 ns. Figure 1 shows the timing diagram.

Asynchronous page read is an asynchronous read operation of several words, in which the first word of
the group takes a longer initial access time, and subsequent words in the group take less “page” access
time to be read. The page size of the page mode devices is either four words or eight words, with the
page being selected by the least significant two or three bits of address. Page mode interface provides
faster read access speed for random locations within a page. Initial access time is typically 70 to 120 ns.
Access time within a page is typically 25 ns. Figure 2 shows the page read timing diagram.

Synchronous burst read is a read occurring at regular intervals dependent on a clock edge. Burst mode
devices require three extra control pins to perform burst read. They are Clock, Load Burst Address
(LBA#) or Address Valid (ADV#), and Burst Address Advance (BAA#) or RDY. When the burst device first
powers up, it is enabled for asynchronous read operation. To enable synchronous burst read, the system
must issue the burst mode enable command sequence. The initial address of an access is loaded by the
clock edge when LBA# or AVD# is low. The first data word is available after the initial access time delay.
Sequential words are available on each following clock edge after the burst access time delay. Typical
initial access time is 50 to 70 ns. Burst accesses can continue with a 50- to 80-MHz clock. Depending on
the specific device, Cypress burst mode flash offers a number of read modes to interface with a wide
range of microprocessors. They are linear burst, interleaved burst, and continuous sequential burst. In
the linear and interleaved burst modes, the device delivers a stream of words from a 4, 8, 16, or 32 word
aligned

block. (For the S29CD family, the burst is 32-bit double words.) If the initial address is not at the
beginning of the block, the sequence of words following the initial access will wrap from the end to the
beginning of the block. In continuous sequential burst mode, the device reads sequentially through the
entire address range. Refer to a specific burst device datasheet for detailed information. Figure 3 shows
burst read mode.
Program

The unprogrammed state of a flash memory cell is a high signal level or logical one. Changing a flash
memory cell (or bit) to a low voltage level or zero is called programming. Programming on Cypress
Floating Gate flash is generally done one byte or word at a time. MirrorBit technology uses a write
buffer to program one byte to as many as 32 bytes. One key point to note is that programming only
changes ones to zeros. Programming is initiated by a series of write accesses that form a program
command. The required sequence of write accesses prevents unintended changes to stored data. 3.3
Erase

Erasure of a flash device is done through multiple write accesses that form an erase command. The
erase completion time is dependent upon the sector size and technology. The erase command sequence
initiates the embedded erase algorithm – an internal algorithm that automatically preprograms the
memory array (if it is not already programmed) before executing the erase operation simultaneously on
all bits of the sector. One key point to note is that chip or sector erasing only changes zeros to ones.
During erase, the device automatically times the erase pulse widths and verifies the proper cell margin.
A floating gate transistor (FGT) is a complementary metal-oxide semiconductor
(CMOS) technology capable of holding an electrical charge in a memory device that
is used to store data.

Floating gate transistors were first used in erasable programmable read-only memory
(EPROM) and later in electronically erasable programmable read only memory
(EEPROM). Flash memory is a type of EEPROM that is programmed and erased in
large blocks.

The flash chip's cells are arranged in a grid that has a transistor at each intersection.
Each transistor has two gates: one is known as a floating gate, and the other one is
called a control gate. The two gates are separated from each other by a thin dielectric
material generally referred to as the oxide layer. Because the floating gate is
electrically isolated by the oxide layer, any electrons placed on it are trapped there.
This is what makes flash memory nonvolatile.

How floating gate transistors work

Flash memory works by adding (charging) or removing (discharging) electrons

to and from a floating gate. A bit's 0 or 1 state depends upon whether or not
the floating gate is charged or uncharged. When electrons are present on the
floating gate, current can't flow through the transistor and the bit state is 0.
This is the normal state for a floating gate transistor, when a bit is
programmed. When electrons are removed from the floating gate, current is
allowed to flow and the bit state is 1.

Two options are used to add, or trap, electrons in the floating gate: Fowler-
Nordheim tunneling and channel hot electron injection (CHE).

Fowler-Nordheim tunneling requires a strong electric field between the

negatively charged source and the positively charged control gate to draw
electrons into the floating gate. The electrons move from the source through
the thin oxide layer to the floating gate, where they are trapped between the
oxide insulation layers.
Channel hot electron injection, also known as hot-carrier injection, uses a high
current in the channel to give electrons sufficient energy to "boil" out of the
channel and break through the tunnel oxide layer, changing the threshold
voltage of the floating gate. A positive charge on the control gate attracts the
electrons from the channel into the floating gate, where they become trapped.

The oxide layer that surrounds the floating gate keeps the electrons trapped,
whether or not the flash device has power, enabling persistent storage of data
bits.

Two mechanisms are also used to remove the electrons from the floating
gate. With EPROM technology, exposing the memory cell to ultraviolet light
causes the electrons to leak out of the floating gate. In EEPROM and flash
memory devices, Fowler-Nordheim tunneling removes electrons from the
floating gate. A strong negative charge on the control gate forces electrons
through the tunnel oxide layer into the channel, where the electrons are drawn
to the strong positive charge at the source and the drain.

Floating gate vs. charge trap

A floating gate and a charge trap are types of semiconductor technology

capable of holding an electrical charge in a flash memory device, but the
chemical composition of their storage layers differs and they add and remove
electrons in different ways.

Flash devices that use floating gate transistors in the memory cells store
electrons in an isolated polycrystalline silicon conductive layer. The charge of
the floating gate changes when electrons are programmed into it to create a
threshold voltage shift in the transistor.

Devices that use charge trap technology typically store electrons in a

nonconductive silicon nitride insulation layer. Forcing electrons into the nitride
layer also generates a threshold voltage shift, and the electrons are held
captive in the nonconductive material.

Flash devices that use charge trap technology tend to be less complicated to
manufacture than those that use floating gate transistors. Charge trap devices
generally require less power to program and fewer process steps, and they
are less prone to wear out because the programming operation puts less
stress on the oxide layer. However, manufacturers have faced challenges in
the mass production of NAND flash memory devices that use charge trap
technology. The method used to remove electrons from a charge trap can be
tricky, and data retention may be an issue in charge trap-based flash devices.

Advanced Micro Devices Inc. and Fujitsu Semiconductor Ltd. were pioneers in
the volume production of charge trap technology in NOR flash
memory devices. Spansion Inc. acquired Fujitsu Semiconductor's
microcontroller and analog business in 2013, and Cypress Semiconductor
Corp. subsequently merged with Spansion in 2015. Macronix uses charge
trap technology in the production of read-only memory (ROM) devices. NAND
flash memory manufacturers such as Samsung, SK Hynix and Toshiba use
charge trap technology in the manufacture of 3D NAND flash. Intel and Micron
continue to use floating gate transistors with their 3D NAND technology.