UNIT I:

Digital System Design

Automation

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 Unit Outline
● Design Concepts
● Design Process
● Abstraction Levels
● Introduction to FPGA
● Introduction to HDLs (VHDL and Verilog)

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Digital Concepts

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 Digital Hardware
● Standard Chips
● Programmable Logic Devices
● Custom-Designed Chips

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The Design
Process

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 Abstraction Levels
Level Components Representation
Behavioral Algorithms, FSMs Algorithmic representation of
system functions
System Processors, Interconnection of major
(architectural) memories, functional functional units
subsystems
Register Registers, adders, Data movement and
Transfer Level comparators, ALUs, transformation and required
(RTL/dataflow) counters, controllers, sequential control
bus
Gate (logic Logic gates, flip-flops Implementation of register
level) level components using gates
and flip-flops
Transistor Transistors, resistors, Implementation of gates and
(switch level) capacitors flip-flops using transistors,
capacitors, and resistors

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 Software Aspects of Digital
Design
● In computer-aided design (CAD), various software tools
improve the designer’s productivity and help to improve the
correctness and quality of designs.

● Software tools:
– Schematic entry
– HDLs
– HDL compilers, simulators, and synthesis tools
– Simulators
– Test benches
– Timing analyzers and verifiers

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 Design Methodology
● Uses HDL to describe the system being designed and the
testbench used to verify the design
● Uses a software compiler and simulator tool to simulate the
design to verify its functionality and timing
● Uses a software synthesis tool to create the logic described
● Uses a software place-and-route tool to map the synthesized
logic to the target PLD and to generate a timing model and a
configuration file (timing verification can also follow)
● Uses a PLD to physically implement the design
● Uses the information in configuration file to program the PLD

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 FPGA
● 1985: Xilinx (Ross Freeman) introduced a completely
new idea:
– User control and time to market of PLDs
– Densities and cost benefit of gate arrays

● Field Programmable Gate Arrays

● FPGAs are programmable semiconductor devices that

are based around a matrix of configurable logic blocks
(CLBs) or logic cells connected via programmable
interconnects.

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General FPGA Configuration

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 Two FPGA Types
● Two basic types:
– SRAM-based reprogrammable
– One Time Programmable (OTP)

● The two types differ in the implementation of the logic

cell and the mechanism used to make connections in
the device.

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 Two FPGA Types
SRAM-based OTP
Programmable

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 FPGAs vs. CPLDs
FPGAs CPLDs

● Fine-grain devices ● Coarse-grain devices

– Contains a lot (up to 100,000) of – Contains relatively few (a few
tiny blocks of logic with flip-flops
100's max) large blocks of
● RAM-based logic with flip-flops
● Have special routing resources to ● EEPROM-based
implement efficiently arithmetic
functions
● Faster input-to-output timings

– Binary counters, adders, – Better suited for

comparators, etc. microprocessor decoding logic
● Can contain large digital designs ● Can contain small designs only

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 FPGAs vs. Microcontrollers
FPGAs Microcontrollers

● Implement programmable ● Are based on a CPU

logic elements running in a architecture (executes a set of
parallel fashion instructions in a sequential
manner)
●
● More configurable
● Have on-chip peripherals that
also execute in parallel with
their CPU

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 HDLs
● A hardware description language (HDL) is similar to a
typical computer programming language except that an
HDL is used to describe hardware rather than a program to
be executed on a computer.

● Institute of Electrical and Electronics Engineers (IEEE)

standard HDLs:
– VHDL
– Verilog HDL

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 HDLs
● The complexity of ASIC and FPGA designs has meant an
increase in the number of specific tools and libraries of
macro and mega cells written in either VHDL or Verilog.

● As a result, it is important that designers know both VHDL

and Verilog and that EDA tools vendors provide tools that
provide an environment allowing both languages to be used
in unison.

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 HDLs
● VHDL (Very high speed integrated circuit Hardware Description
Language) became IEEE standard 1076 in 1987.

● The Verilog hardware description language has been used far

longer than VHDL and has been used extensively since it was
launched by Gateway in 1983.

● Cadence bought Gateway in 1989 and opened Verilog to the

public domain in 1990.

● Verilog became IEEE standard 1364 in December 1995.

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 VHDL and Verilog
in Comparison

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 Capability
● VHDL – like Pascal or Ada programming languages

● Verilog – like C programming language

● It is important to remember that both are Hardware

Description Languages and not programming languages

● For synthesis, only a subset of languages is used.

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 Capability
● Hardware structure can be modeled equally effectively in both VHDL
and Verilog.

● When modeling abstract hardware, the capability of VHDL can

sometimes only be achieved in Verilog when using the Programming
Language Interface (PLI).

● The choice of which to use is not therefore based solely on technical

capability but on:
– personal preferences
– EDA tool availability
– commercial, business and marketing issues

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 Capability
● The modeling constructs of VHDL and Verilog cover a
slightly different spectrum across the levels of behavioral
abstraction.

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 Compilation
● VHDL:
– Multiple design-units (entity/architecture pairs), that reside in
the same system file, may be separately compiled if so
desired.

– It is good design practice to keep each design unit in it's own

system file in which case separate compilation should not be
an issue.

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 Compilation
● Verilog:
– The Verilog language is still rooted in it's native interpretative
mode.

– Compilation is a means of speeding up simulation, but has not

changed the original nature of the language.

– The care must be taken with both the compilation order of code
written in a single file and the compilation order of multiple files.

– Simulation results can change by simply changing the order of

compilation.

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 Data Types
● VHDL:
– A multitude of language or user defined data types can be used.

– This may mean dedicated conversion functions are needed to

convert objects from one type to another.

– The choice of which data types to use should be considered

wisely, especially enumerated (abstract) data types.

– VHDL may be preferred because it allows a multitude of language

or user defined data types to be used.

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 Data Types
● Verilog:
– Compared to VHDL, Verilog data types a very simple, easy to use
and very much geared towards modeling hardware structure as
opposed to abstract hardware modeling.

– Unlike VHDL, all data types used in a Verilog model are defined by
the Verilog language and not by the user.

– There are net data types, for example wire, and a register data type
called reg.

– Verilog may be preferred because of its simplicity.

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 Design Reusability
● VHDL:
– Procedures and functions may be placed in a package so that
they are available to any design-unit that wishes to use them.

● Verilog:
– There is no concept of packages in Verilog.
– Functions and procedures used within a model must be defined in
the module.
– To make functions and procedures generally accessible from
different module statements the functions and procedures must
be placed in a separate system file and included using the
`include compiler directive.

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 Ease of Learning
● Starting with zero knowledge of either language, Verilog is
probably the easiest to grasp and understand.

● VHDL may seem less intuitive at first for two primary

reasons:
– First, it is very strongly typed; a feature that makes it robust
and powerful for the advanced user after a longer learning
phase.
– Second, there are many ways to model the same circuit,
specially those with large hierarchical structures

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 High Level Constructs
● VHDL:
– There are more constructs and features for high-level modeling
in VHDL than there are in Verilog.
– Abstract data types can be used along with the following
statements:
● package statements for model reuse,
● configuration statements for configuring design structure,
● generate statements for replicating structure,
● generic statements for generic models that can be
individually characterized, for example, bit width.
– All these language statements are useful in synthesizable
models.

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 High Level Constructs
● Verilog:
– Except for being able to parameterize models by overloading
parameter constants, there is no equivalent to the high-level
VHDL modeling statements in Verilog.

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 Libraries
● VHDL:
– A library is a store for compiled entities, architectures,
packages and configurations. Useful for managing multiple
design projects.

● Verilog:
– There is no concept of a library in Verilog. This is due to it's
origins as an interpretive language.

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 Low Level Constructs
● VHDL:
– Simple two input logical operators are built into the language:
NOT, AND, OR, NAND, NOR, XOR, and XNOR.

– Any timing must be separately specified using the after

clause.

– Separate constructs defined under the VITAL language must

be used to define the cell primitives of ASIC and FPGA
libraries.

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 Low Level Constructs
● Verilog:
– The Verilog language was originally developed with gate level
modeling in mind, and so has very good constructs for
modeling at this level and for modeling the cell primitives of
ASIC and FPGA libraries.

– Examples include User Defined Primitives (UDP), truth tables

and the specify block for specifying timing delays across a
module.

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 Managing Large Designs
● VHDL:
– Configuration, generate, generic and package statements all
help manage large design structures.

● Verilog:
– There are no statements in Verilog that help manage large
designs.

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 Operators
● The majority of operators are the same between the two
languages.

● Verilog does have very useful unary reduction operators

that are not in VHDL.

● A loop statement can be used in VHDL to perform the same

operation as a Verilog unary reduction operator.

● VHDL has the mod operator that is not found in Verilog.

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 Procedures and Tasks
● VHDL:
– Concurrent procedure calls are allowed.

● Verilog:
– Concurrent procedure calls are not allowed

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 Readability
● This is more a matter of coding style and experience than
language feature.
– VHDL is a concise and verbose language;
– Verilog is more like C because it's constructs are based
approximately 50% on C and 50% on Ada.

● For this reason an existing C programmer may prefer Verilog

over VHDL.

● Whatever HDL is used, when writing or reading an HDL model to

be synthesized, it is important to think about hardware intent.

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 Structural Replication
● VHDL:
– The generate statement replicates a number of instances of
the same design-unit or some sub part of a design, and
connects it appropriately.

● Verilog:
– There is no equivalent to the generate statement in Verilog.

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 Verboseness
● VHDL:
– Because VHDL is a very strongly typed language, models
must be coded precisely with defined and matching data
types.

– This may be considered an advantage or disadvantage.

– It does mean models are often more verbose, and the code
often longer, than it's Verilog equivalent.

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 Verboseness
● Verilog:
– Signals representing objects of different bits widths may be assigned to
each other.

– The signal representing the smaller number of bits is automatically padded

out to that of the larger number of bits, and is independent of whether it is
the assigned signal or not.

– Unused bits will be automatically optimized away during the synthesis

process.

– This has the advantage of not needing to model quite so explicitly as in

VHDL, but does mean unintended modeling errors will not be identified by
an analyzer.

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Summary

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Summary

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Summary

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Summary

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 References
● Douglas J. Smith, “VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in VHDL, Verilog and C”
● www.ue.pwr.wroc.pl/pld/pld_12.pdf
● www.asic-world.com
● http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.
pdf

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