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VHDL Class 2 Architecture

The architecture of a chip like the 8085 refers to its internal parts and working. It is where the logical gates and blocks are connected in a sequence to implement the chip's logic. Each architecture must be associated with an entity. The architecture defines the structure using a syntax that begins with ARCHITECTURE, specifies the entity it uses, contains statements between BEGIN and END, and ends with the architecture name. Common mistakes include not declaring the entity, mismatching names, missing BEGIN/END, missing semicolons, and ending with the entity name instead of the architecture name.

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krishna muddam
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38 views

VHDL Class 2 Architecture

The architecture of a chip like the 8085 refers to its internal parts and working. It is where the logical gates and blocks are connected in a sequence to implement the chip's logic. Each architecture must be associated with an entity. The architecture defines the structure using a syntax that begins with ARCHITECTURE, specifies the entity it uses, contains statements between BEGIN and END, and ends with the architecture name. Common mistakes include not declaring the entity, mismatching names, missing BEGIN/END, missing semicolons, and ending with the entity name instead of the architecture name.

Uploaded by

krishna muddam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ARCHITECTURE

What does it mean when we refer ARCHITECTURE of a chip, say 8085.


It means the actual internal parts & working of that specific chip.
That is why; we call this part of the code- Architecture.
• This is the part where we design the logic
• This is where we connect all the logical gates/blocks in a sequence to solve the
logical equations.
Each architecture has to be associated with an Entity.
As of now, we can consider Architecture as Skeleton and entity as skin.

Example of an architecture:

ARCHITECTURE struct OF my_or IS


BEGIN
z<= x or y;
END struct;

Syntax of ARCHITECTURE

ARCHITECTURE <name of architecture> OF <entity it uses> IS


BEGIN
Statement;
Statement;
. . . . . . .;
. . . . . . .;
END <name of Architecture>;
Common mistakes made in ARCHITECTURE
• Entity not declared- entity used must be pre-defined
• Mismatch of architecture name
• Begin- don’t forget to begin
• All sentences end with semi-colon
• End with Architecture name- most of guys confuse and end with entity name.
(That may work in older versions But not in all versions)

So when we write a program it should look like

ENTITY my_or IS
PORT(
x, y: IN std_logic;
z: OUT std_logic );
END my_or;

ARCHITECTURE struct OF my_or IS


BEGIN
z<= x or y;
END struct;
Examples:

Let us write the program for the example we gave in Entity

library ieee;
use ieee.std_logic_1164.all;
ENTITY my_block IS
PORT( a, b,c,d : IN std_logic;
out1,out2 : OUT std_logic );
END my_block;

ARCHITECTURE block OF my_block IS


BEGIN
out1<= a and b;
out2 <= c or d;
END block;
Let us make this little complex, to make declarations in Entity CLEAR

Let us assume that a and b are bit inputs and c and d are Boolean inputs.

So the corresponding outputs will be of the same type.

library ieee;
use ieee.std_logic_1164.all;
ENTITY my_block IS
PORT( a, b : IN bit ;
c, d : IN Boolean ;
out1 : OUT bit ;
out2 : OUT boolean );
END my_block;

ARCHITECTURE block OF my_block IS


BEGIN
out1<= a and b;
out2 <= c or d;
END block;

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