Govt.

College of Engineering & Technology, Bikaner

Course File
Session 2018-19

(Computer Architecture 5CS1A)

Semester: 5th

Faculty: Laxman Singh Khangarot

Department of Computer Science & Engineering

 INDEX
S.No. Content Page Number Remarks
1 Syllabus prescribed by RTU

2 Faculty Time Table

3 Course Plan

4 Text and Reference Books

5 Course Outcomes

6 Course Outcome-Program Outcome Mapping

7 Course Outcome-Program Specific Outcome Mapping

8 Course Coverage ( Unit Wise)

9 Assignments/Quizzes

10 Mid Term Papers

11 University papers

12 Mid Term Award Lists

COMPUTER ARCHITECTURE -5CS1A

 L T P C
3 0 0 3

Course type Core

Prerequisites COMPUTER ARCHITECTURE

Course Coordinator Laxman Singh Khangarot

Grading End Sem Exam (80%)

Mid Sem Exam (20%)
Assignments- 2

Class Timings Lecture: -Mon 8.30-9.20am, Tue 9:20-10:10am,

Wed 8:30-10:10am

Mid Term Exam Mid-Term 1st 13-Sep.-2018 (12 Marks)

Mid-Term 2nd due

Text and Reference Books

1. Computer Organization and Architecture - William Stallings (Pearson Education Asia)

2. Computer Organization and Architecture -John P. Hayes (McGraw -Hill)
3. Computer Organization -V. Carl. Hamacher (McGraw-Hill)

Course Outcomes
Upon successful completion of the course, the students will be able to:

CO1: Appreciate macro organization of any computing system

CO2: Design instruction set architectures and develop their micro architectures
CO3: Understand various digital arithmetic algorithms
CO4: Analyze various caching and memory system architectures
CO5: Understand instruction level parallelism

Mapping of Course Outcomes (COs) to Programme Outcomes (POs)

 COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3

CO2 3 3 3 3

CO3 3 2 3

CO4 2 3 2

CO5 3 3

1: Related 2: Moderately Related 3: Strongly Related

PSO1: Ability to use the concepts of computing to design various applications of engineering
PSO2: To apply mathematical and analytical skills for solving the complex and critical problems of computer science and
engineering
PSO3: Provide effective and efficient work strategies towards development of smart nation

Mapping of Course Outcomes (COs) to Programme Specific Outcomes (PSOs)

COs PSO1 PSO2 PSO3

CO1 Appreciate macro organization of any computing system 2

CO2 Design instruction set architectures and develop their micro 2 2

architectures
CO3 Understand various digital arithmetic algorithms 3 3

CO4 Analyze various caching and memory system architectures 3 3 3

CO5 Understand instruction level parallelism 3 3 3

1: Related 2: Moderately Related 3: Strongly Related

Course topics (as per syllabus and out of Syllabus (if any)), their objectives and duration (Plan)
 UNIT Objectives Target Duration Readings Lecture taken
on
POs (Hours) (DATE)

Introduction to Computer PO1, 6 1(1,2)

Architecture and Organization: PO2 2(1)
Von Neuman Architecture, Flynn
Classification.
Register Transfer and Micro
operations: Register transfer
language, Arithmetic Micro-
operations, Logic Micro-operations,
Shift Micro-operations, Bus and
memory transfers.
Computer Organization and
Design: Instruction cycle, computer
registers, common bus system,
computer instructions, addressing
modes, design of a basic computer

Central Processing Unit: General PO1, 6 1(3,4)

register organization, stack PO2,
organization, Instruction formats, Data PO3,
transfer and manipulation, program PO4
control. RISC, CISC characteristics.
Pipeline and Vector processing:
Pipeline structure, speedup, efficiency,
throughput and bottlenecks.
Arithmetic pipeline and Instruction
pipeline.

Computer Arithmetic: Adder, Ripple PO1, 5 1(5)

carry Adder, carry look Ahead Adder, PO2, 2(4,5)
Multiplication: Add and Shift, Array PO4
3(4)
multiplier and Booth Multiplier,
Division: restoring and Non-restoring
Techniques. Floating Point Arithmetic:
Floating point representation, Add,
Subtract, Multiplication, Division.
Memory Organization: RAM, ROM, PO1, 5 1(5,6)
Memory Hierarchy, Organization, PO2,
Associative memory, Cache memory, PO3,
and Virtual memory: Paging and
Segmentation.

Input-Output Organization: Input- PO1, 5 1(7,8,9)

Output Interface, Modes of Transfer, PO2, 3(8,9)
Priority Interrupt, DMA, IOP processor.

Documents to be included with course plan:

 Course reference notes (any handouts, written notes, ppts, links of web pages or documents)
 Mid-term Question paper and its solution
 Mid-term marks list
 Assignment Questions, its solution and marks
 Practical evaluation marks on each practical day (only for lab.) NA
 Internal viva marks with assessment type (lab file, internal viva marks, continuous evaluation marks, written
exam etc.) NA

*All the documents can be in written or printed form

 Govt. College of Engineering & Technology Bikaner
Computer Science Engineering
st
I -Mid Term, Sub: Computer Architecture (CSE-II) 13/09/2018
Time: 1 hr MM: 12

Attempt any one question from each (CO1, CO2, CO3).

CO1: (4 marks)
Q.1 Design a common BUS system for 5 registers each of 4-bits length (Register to BUS
connection only).
Q.2 Design a 4-bit arithmetic circuit, draw proper diagram and Function table.

CO2: (4 marks)
Q.3 Derive the speed up formula for a pipeline system of K stage. What will be the maximum
speedup possible?
Q.4 Explain Control word and differentiate RICS and CISC characteristics.

CO3: (4 marks)
Q.5 Explain Booth Multiplication algorithm and draw proper flowchart.
Q.6 How floating point number`s Addition and Subtraction done. Explain with flowchart.

______________________________________________________________________________________________________________________________

Solution

Ans.1:

A bus system can be constructed with three-state gates instead of multiplexers. A three-state
gate is a digital circuit that exhibits three states. Two of the states are signals equivalent to
logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-
impedance state behaves like an open circuit, which means that the output is disconnected
and does not have a logic significance. Three-state gates may perform any conventional logic,
such as AND or NAND. However, the one most commonly used in the design of a bus system
is the buffer gate.

The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer them into
the four-line common bus. When S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that form the bus. This causes the bus lines to receive
the content of register A since the outputs of this register are connected to the 0 data inputs
of the multiplexers. Similarly, register B is selected if S1S0 = 01, and so on. Table 4-2 shows
the register that is selected by the bus for each of the four possible binary value of the
selection lines.

Ans 2:
The arithmetic microoperations listed in Table 4-3 can be implemented in one composite
arithmetic circuit. The basic component of an arithmetic circuit is the parallel adder. By
controlling the data inputs to the adder, it is possible to obtain different types of arithmetic
operations.

When S1S0 = 00, the value of B is applied to the Y inputs of the adder. If Cin = O, the output D
= A + B . If Cin = 1, output D = A + B + l. Both cases perform the add microoperation with or
without adding the input carry. When S1S0 = 01, the complement of B is applied to the Y
inputs of the adder. If Cin = 1, then D = A + B + 1. This produces A pius the 2's complement
of B, which is equivalent to a subtraction of A - B. When Cm = 0, then D = A + B . This is
equivalent to a subtract with borrow, that is, A - B - 1. When S1S0 = 10, the inputs from B are
neglected, and instead, all O's are inserted into the Y inputs. The output becomes D = A + 0 +
Cm· This gives D = A when Cm = 0 and D = A + 1 when Cin = 1. In the first case we have a
direct transfer from input A to output D. In the second case, the value of A is incremented by
1. When S1So = 11, all 1' s are inserted into the Y inputs of the adder to produce the
decrement operation D = A - 1 when Cm = 0. This is because a number with all 1's is equal to
the 2's complement of 1 (the 2's complement of binary 0001 is 1111). Adding a number A to
the 2's complement of 1 produces F = A + 2's complement of 1 = A - 1. When Cin = 1, then D =
A - 1 + 1 = A, which causes a direct transfer from input A to output D. Note that the
microoperation D = A is generated twice, so there are only seven distinct microoperations in
the arithmetic circuit.

Ans 3:

Next consider a nonpipeline unit that performs the same operation and takes a time equal to
t. to complete each task. The total time required for n tasks is nt n. The speedup of a pipeline
processing over an equivalent nonpipeline processing is defined by the ratio.

As the number of tasks increases, n becomes much larger than k - 1, and k + n - 1 approaches
the value of n. Under this condition, the speedup becomes

If we assume that the time it takes to process a task is the same in the pipeline and non
pipeline circuits, we will have t, = kt,. Including this assumption, the speedup reduces to
Ans 4:
RISC Characteristics
The concept of RISC architecture involves an attempt to reduce execution time by simplifying
the instruction set of the computer. The major characteristics of a RISC processor are:
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed-length, easily decoded instruction format
6. Single-cycle instruction execution
7. Hardwired rather than microprogrammed control

CISC archltecture are:

1. A large number of instructions-typically from 100 to 250 instructions
2. Some instructions that perform specialized tasks and are used infrequently
3. A large variety of addressing modes-typically from 5 to 20 different modes
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory

Ans 5:

Booth algorithm gives a procedure for multiplying binary integers in signed-2's complement
representation. It operates on the fact that strings of O's in the multiplier require no addition
but just shifting, and a string of 1's in the multiplier from bit weight 2' to weight 2m can be
treated as 2'+1 - 2m. For example, the binary number 001 110 ( + 14) has a string of 1's from
23 to 21 (k = 3, m = 1). The number can be represented as 2k+ l - 2m = 24 - 21 = 16 -2 = 14.
Therefore, the multiplication M x 14, where M is the multiplicand and 14 the multiplier, can
be done as M x 24 - M X 21 • Thus the product can be obtained by shifting the binary
multiplicand M four times to the left and subtracting M shifted left once.

Ans 6:
Addition and Subtraction
During addition or subtraction, the two floating-point operands are in AC and BR . The sum or
difference is formed in the AC . The algorithm can be divided into four consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
A floating-point number that is zero cannot be normalized. If this number is used during the
computation, the result may also be zero. Instead of checking for zeros during the
normalization process we check for zeros at the beginning and terminate the process if
necessary. The alignment of the mantissas must be carried out prior to their operation. After
the mantissas are added or subtracted, the result may be unnormalized. The normalization
procedure ensures that the result is normalized prior to its transfer to memory.
ASSIGNMENTS
ASSIGNMENT 1
Q.1Explain Arithmetic micro-operations design a 4-bit arithmetic circuit with Diagram and Function table
Q.2Explain the architecture for General Register Organization with 7 registers and input & output along with
an ALU. Draw proper diagram.
Q.3Write shorts notes on-
(a) Flynn Classification (b) Von Newman Architecture
(c) Computer Registers

ASSIGNMENT 2
Q.1Explain Arithmetic Logic Shift Unit circuit with Diagram and Function table.
Q.2Explain the architecture for General Register Organization with 7 registers and input & output along with
an ALU. Explain control word and draw proper diagram.
Q.3Explain the concept of Pipeline and derived formula for Speedup for a k-stage pipeline.

ASSIGNMENT 3
Q.1Explain Arithmetic micro-operations design a 4-bit arithmetic circuit with Diagram and Function table
Q.2Explain the architecture for General Register Organization with 7 registers and input & output along with
an ALU. Draw proper diagram.
Q.3Write shorts notes on-

(a) Flynn Classification (b) Registers transfer language

ASSIGNMENT 4
Q.1Explain the Booth Multiplication algorithm for multiplication of 2`S complement data with proper flow
chart.
Q.2What is Virtual memory? Explain with suitable example.
Q.3Write shorts notes on-
(a) Carry Look ahead adder (b) ROM and RAM Chip
(c) Associative Memory (d) Pipelining Speedup