LTC3300-1

High Efficiency Bidirectional

Multicell Battery Balancer
FEATURES DESCRIPTION
n Bidirectional Synchronous Flyback Balancing The LTC®3300-1 is a fault-protected controller IC for
of Up to 6 Li-Ion or LiFePO4 Cells in Series transformer-based bidirectional active balancing of multi-
n Up to 10A Balancing Current (Set by Externals) cell battery stacks. All associated gate drive circuitry,
n Integrates Seamlessly with the LTC680x Family of precision current sensing, fault detection circuitry and a
Multicell Battery Stack Monitors robust serial interface with built-in watchdog timer are
n Bidirectional Architecture Minimizes Balancing integrated.
Time and Power Dissipation
n Up to 92% Charge Transfer Efficiency
Each LTC3300-1 can balance up to 6 series-connected bat-
n Stackable Architecture Enables >1000V Systems
tery cells with an input common mode voltage up to 36V.
n Uses Simple 2-Winding Transformers
Charge from any selected cell can be transferred at high
n 1MHz Daisy-Chainable Serial Interface with 4-Bit
efficiency to or from 12 or more adjacent cells. A unique
level-shifting SPI-compatible serial interface enables
CRC Packet Error Checking
n High Noise Margin Serial Communication
multiple LTC3300-1 devices to be connected in series,
n Numerous Fault Protection Features
without opto-couplers or isolators, allowing for balancing
n 48-Lead Exposed Pad QFN and LQFP Packages
of every cell in a long string of series-connected batteries.
When multiple LTC3300-1 devices are connected in series
APPLICATIONS they can operate simultaneously, permitting all cells in
the stack to be balanced concurrently and independently.
n Electric Vehicles/Plug-in HEVs
Fault protection features include readback capability, cy-
n High Power UPS/Grid Energy Storage Systems
n General Purpose Multicell Battery Stacks
clic redundancy check (CRC) error detection, maximum
on-time volt-second clamps, and overvoltage shutoffs.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.

TYPICAL APPLICATION
High Efficiency Bidirectional Balancing
NEXT CELL ABOVE

CHARGE
SUPPLY CHARGE
+
CELL 12 3
SERIAL
DATA OUT
Balancer Efficiency
(ICHARGE 1-6) RETURN LTC3300-1
TO LTC3300-1 100
(IDISCHARGE 1-6) ABOVE DC2064A DEMO BOARD
3 ICHARGE = IDISCHARGE = 2.5A
CHARGE TRANSFER EFFICIENCY (%)

+ VCELL = 3.6V
CELL 7 95
•
CHARGE IDISCHARGE
+ CHARGE
CELL 6
RETURN DISCHARGE
90
• 3

85

LTC3300-1
• 80
CHARGE ICHARGE
+ 6 8 10 12
CELL 1 NUMBER OF CELLS (SECONDARY SIDE)
SUPPLY SERIAL
• 3 DATA IN 33001 TA01b
FROM
LTC3300-1
BELOW

33001 TA01a

NEXT CELL BELOW

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LTC3300-1
ABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage (C6 to V–)..................................36V Voltage Between Pins

Input Voltage (Relative to V–) Cn to Cn-1*............................................... –0.3V to 6V
C1 ............................................................ –0.3V to 6V InP to Cn-1*........................................... –0.3V to 0.3V
I1P ........................................................ –0.3V to 0.3V BOOST+ to C6........................................... –0.3V to 6V
I1S, I2S, I3S, I4S, I5S, I6S..................... –0.3V to 0.3V CSBO to SCKO, CSBO to SDOI,
CSBI, SCKI, SDI........................................ –0.3V to 6V SCKO to SDOI........................................ –0.3V to 0.3V
CSBO, SCKO, SDOI................................. –0.3V to 36V SDO Current............................................................10mA
VREG, SDO................................................ –0.3V to 6V G1P, GnP, G1S, GnS, BOOST– Current................ ±200mA
RTONP, RTONS............–0.3V to Min[VREG + 0.3V, 6V] Operating Junction Temperature Range (Notes 2, 7)
TOS, VMODE, CTRL, LTC3300I-1......................................... –40°C to 125°C
BOOST, WDT............... –0.3V to Min[VREG + 0.3V, 6V] LTC3300H-1........................................ –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
*n = 2 to 6

PIN CONFIGURATION
TOP VIEW
TOP VIEW

BOOST–
BOOST+
BOOST
VMODE
41 BOOST–
40 BOOST+

CSBO
SCKO
SDOI
VREG
42 BOOST
46 VMODE

TOS

G6P
45 CSBO
44 SCKO

I6P
43 SDOI
48 VREG

C6
47 TOS

38 G6P
37 I6P
39 C6

48
47
46
45
44
43
42
41
40
39
38
37
G6S 1 36 C5
I6S 2 35 G5P G6S 1 36 C5
G5S 3 34 I5P I6S 2 35 G5P
G5S 3 34 I5P
I5S 4 33 C4
I5S 4 33 C4
G4S 5 32 G4P G4S 5 32 G4P
I4S 6 49 31 I4P I4S 6 49 31 I4P
G3S 7 V– 30 C3 G3S 7 V– 30 C3
I3S 8 29 G3P I3S 8 29 G3P
G2S 9 28 I3P G2S 9 28 I3P
I2S 10 27 C2 I2S 10 27 C2
G1S 11 26 G2P G1S 11 26 G2P
I1S 12 25 I2P
I1S 12 25 I2P
RTONS 13
RTONP 14
CTRL 15
CSBI 16
SCKI 17
SDI 18
SDO 19
WDT 20
V– 21
I1P 22
G1P 23
C1 24

RTONS 13
RTONP 14
CTRL 15
CSBI 16
SCKI 17
SDI 18
SDO 19
WDT 20
V– 21
I1P 22
G1P 23
C1 24

UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN LXE PACKAGE
TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W 48-LEAD (7mm × 7mm) PLASTIC LQFP
EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB TJMAX = 150°C, θJA = 20.46°C/W, θJC = 3.68°C/W
EXPOSED PAD (PIN 49) IS V–, MUST BE SOLDERED TO PCB

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 LTC3300-1
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3300IUK-1#PBF LTC3300IUK-1#TRPBF LTC3300UK-1 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C
LTC3300HUK-1#PBF LTC3300HUK-1#TRPBF LTC3300UK-1 48-Lead (7mm × 7mm) Plastic QFN –40°C to 150°C
LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3300ILXE-1#PBF LTC3300ILXE-1#PBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 125°C
LTC3300HLXE-1#PBF LTC3300HLXE-1#PBF LTC3300LXE-1 48-Lead (7mm × 7mm) Plastic eLQFP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Specifications
IQ_SD Supply Current When Not Measured at C1, C2, C3, C4, C5 0 1 µA
Balancing (Post Suspend or Pre Measured at C6 7 16 25 µA
First Execute) Measured at BOOST+ 0 10 µA
IQ_ACTIVE Supply Current When Balancing Balancing C1 Only (Note 4 for V–, C2, C6)
(Note 3) Measured at C1 250 375 µA
Measured at C2, C3, C4, C5 70 105 µA
Measured at C6 560 840 µA
Measured at BOOST+ 0 10 µA
Balancing C2 Only (Note 4 for C1, C3, C6)
Measured at C1 –105 –70 µA
Measured at C2 250 375 µA
Measured at C3, C4, C5 70 105 µA
Measured at C6 560 840 µA
Measured at BOOST+ 0 10 µA
Balancing C3 Only (Note 4 for C2, C4, C6)
Measured at C1, C4, C5 70 105 µA
Measured at C2 –105 –70 µA
Measured at C3 250 375 µA
Measured at C6 560 840 µA
Measured at BOOST+ 0 10 µA
Balancing C4 Only (Note 4 for C3, C5, C6)
Measured at C1, C2, C5 70 105 µA
Measured at C3 –105 –70 µA
Measured at C4 250 375 µA
Measured at C6 560 840 µA
Measured at BOOST+ 0 10 µA
Balancing C5 Only (Note 4 for C4, C6)
Measured at C1, C2, C3 70 105 µA
Measured at C4 –105 –70 µA
Measured at C5 250 375 µA
Measured at C6 560 840 µA
Measured at BOOST+ 0 10 µA
Balancing C6 Only (Note 4 for C5, C6, BOOST+)
Measured at C1, C2, C3, C4 70 105 µA
Measured at C5 –105 –70 µA
Measured at C6 740 1110 µA
Measured at BOOST+ (BOOST = V–) 60 90 µA
Measured at BOOST+ (BOOST = VREG) 0 10 µA
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LTC3300-1
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ_EXTRA Supply Current Extra Additional Current Measured at C6, VMODE = V– 3.75 mA
(Serial I/O in Current Mode) (CSBI Logic Low, SCKI and SDI Both Logic High;
Refer to IIL1, IIH1, IOH1, IOL1 Specs)
VCELL|MIN Minimum Cell Voltage (Rising) Cn to Cn – 1 Voltage to Balance Cn, n = 2 to 6 l 1.8 2 2.2 V
Required for Primary Gate Drive C1 Voltage to Balance C1 l 1.8 2 2.2 V
Cn + 1 to Cn Voltage to Balance Cn, n = 1 to 5 l 1.8 2 2.2 V
BOOST+ to C6 Voltage to Balance C6, BOOST = V– l 1.8 2 2.2 V
VCELL|MIN(HYST) VCELL|MIN Comparator Hysteresis 70 mV
VCELL|MAX Maximum Cell Voltage (Rising) C1, Cn to Cn – 1 Voltage to Balance Any Cell, l 4.7 5 5.3 V
Before Disabling Balancing n = 2 to 6
VCELL|MAX(HYST) VCELL|MAX Comparator Hysteresis 0.5 V
VCELL|RECONNECT Maximum Cell Voltage (Falling) to l 4.25 V
Re-Enable Balancing
VREG Regulator Pin Voltage 9V ≤ C6 ≤ 36V, 0mA ≤ ILOAD ≤ 20mA l 4.4 4.8 5.2 V
VREG|POR VREG Voltage (Rising) for 4.0 V
Power-On Reset
VREG|MIN Minimum VREG Voltage (Falling) VREG Voltage to Balance Cn, n = 1 to 6 l 3.8 V
for Secondary Gate Drive
IREG_SC Regulator Pin Short Circuit Current VREG = 0V 55 mA
Limit
VRTONP RTONP Servo Voltage RRTONP = 20kΩ l 1.158 1.2 1.242 V
VRTONS RTONS Servo Voltage RRTONS = 15kΩ l 1.158 1.2 1.242 V
IWDT_RISING WDT Pin Current, Balancing RTONS = 15kΩ, WDT = 0.5V l 72 80 88 µA
IWDT_FALLING WDT Pin Current as a Percentage RTONS = 15kΩ, WDT = 2V l 85 87.5 90 %
of IWDT_RISING, Secondary OV
VPEAK_P Primary Winding Peak Current I1P l 45 50 55 mV
Sense Voltage InP to Cn – 1, n = 2 to 6 l 45 50 55 mV
VPEAK_P Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l ±1.7 ±5 %
VPEAK_S Secondary Winding Peak Current I1S l 45 50 55 mV
Sense Voltage InS to Cn – 1, n = 2 to 6, CTRL = 0 Only l 45 50 55 mV
VPEAK_S Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l ±0.5 ±3 %
VZERO_P Primary Winding Zero Current I1P l –7 –2 3 mV
Sense Voltage (Note 5) InP to Cn – 1, n = 2 to 6 l –7 –2 3 mV
VZERO_P Matching (All 6) ±{[(Max – Min)/2]/(VPEAK_P|MIDRANGE)} • 100% l ±1.7 ±5 %
Normalized to Mid-Range VPEAK_P (Note 6)
VZERO_S Secondary Winding Zero Current I1S l –12 –7 –2 mV
Sense Voltage (Note 5) InS to Cn – 1, n = 2 to 6, CTRL = 0 Only l –12 –7 –2 mV
VZERO_S Matching (All 6) ±{[(Max – Min)/2]/(VPEAK_S|MIDRANGE)} • 100% l ±0.5 ±3 %
Normalized to Mid-Range VPEAK_S (Note 6)
RBOOST_L BOOST– Pin Pull-Down RON Measured at 100mA Into Pin, BOOST = VREG 2.5 Ω
RBOOST_H BOOST– Pin Pull-Up RON Measured at 100mA Out of Pin, BOOST = VREG 4 Ω
TSD Thermal Shutdown Threshold Rising Temperature 155 °C
(Note 7)
THYS Thermal Shutdown Hysteresis 10 °C
Timing Specifications
tr_P Primary Winding Gate Drive Rise G1P Through G6P, CGATE = 2500pF 35 70 ns
Time (10% to 90%)
tf_P Primary Winding Gate Drive Fall G1P Through G6P, CGATE = 2500pF 20 40 ns
Time (90% to 10%)
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 LTC3300-1
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tr_S Secondary Winding Gate Drive G1S, CGATE = 2500pF 30 60 ns
Rise Time (10% to 90%) G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF 30 60 ns
tf_S Secondary Winding Gate Drive Fall G1S, CGATE = 2500pF 20 40 ns
Time (90% to 10%) G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF 20 40 ns
tONP|MAX Primary Winding Switch Maximum RRTONP = 20kΩ (Measured at G1P-G6P) l 6 7.2 8.4 µs
On-Time
tONP|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l ±1 ±4 %
tONS|MAX Secondary Winding Switch RRTONS = 15kΩ (Measured at G1S-G6S) l 1 1.2 1.4 µs
Maximum On-Time
tONS|MAX Matching (All 6) ±[(Max – Min)/(Max + Min)] • 100% l ±1 ±4 %
tDLY_START Delayed Start Time After New/ 2 ms
Different Balance Command or
Recovery from Voltage/Temp Fault
Voltage Mode Timing Specifications
t1 SDI Valid to SCKI Rising Setup Write Operation l 10 ns
t2 SDI Valid from SCKI Rising Hold Write Operation l 250 ns
t3 SCKI Low l 400 ns
t4 SCKI High l 400 ns
t5 CSBI Pulse Width l 400 ns
t6 SCKI Rising to CSBI Rising l 100 ns
t7 CSBI Falling to SCKI Rising l 100 ns
t8 SCKI Falling to SDO Valid Read Operation l 250 ns
fCLK Clock Frequency l 1 MHz
tWD1 Watchdog Timer Timeout Period WDT Assertion Measured from Last Valid l 0.75 1.5 2.25 second
Command Byte
tWD2 Watchdog Timer Reset Time WDT Negation Measured from Last Valid l 1.5 5 µs
Command Byte
Current Mode Timing Specifications
tPD1 CSBI to CSBO Delay CCSBO = 150pF l 600 ns
tPD2 SCKI Rising to SCKO Delay CSCKO = 150pF l 300 ns
tPD3 SDI to SDOI Delay CSDOI = 150pF, Command Byte l 300 ns
tPD4 SCKI Falling to SDOI Valid CSDOI = 150pF, Write Balance Command l 300 ns
tPD5 SCKI Falling to SDI Valid CSDI = 150pF, Read Operation l 300 ns
tSCKO SCKO Pulse Width CSCKO = 150pF 100 ns
Voltage Mode Digital I/O Specifications
VIH Digital Input Voltage High Pins CSBI, SCKI, SDI; VMODE = VREG l VREG – 0.5 V
Pins CTRL, BOOST, VMODE, TOS l VREG – 0.5 V
Pin WDT l 2 V
VIL Digital Input Voltage Low Pins CSBI, SCKI, SDI; VMODE = VREG l 0.5 V
Pins CTRL, BOOST, VMODE, TOS l 0.5 V
Pin WDT l 0.8 V
IIH Digital Input Current High Pins CSBI, SCKI, SDI; VMODE = VREG –1 0 1 µA
Pins CTRL, BOOST, VMODE, TOS –1 0 1 µA
Pin WDT, Timed Out –1 0 1 µA
IIL Digital Input Current Low Pins CSBI, SCKI, SDI; VMODE = VREG –1 0 1 µA
Pins CTRL, BOOST, VMODE, TOS –1 0 1 µA
Pin WDT, Not Balancing –1 0 1 µA

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LTC3300-1
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
+
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOL Digital Output Voltage Low Pin SDO, Sinking 500µA; VMODE = VREG; Read l 0.3 V
IOH Digital Output Current High Pin SDO at 6V l 100 nA
Current Mode Digital I/O Specifications
IIL1 Digital Input Current Low Pin CSBI; VMODE = V– l –1500 –1250 –1000 µA
Pin SCKI; VMODE = V– l –5 –2.5 0 µA
Pin SDI, VMODE = V–, Write l –5 –2.5 0 µA
Pin SDOI, TOS = V–, Read l 0 2.5 5 µA
IIH1 Digital Input Current High Pin CSBI; VMODE = V– l –5 –2.5 0 µA
Pin SCKI; VMODE = V– l –1500 –1250 –1000 µA
Pin SDI, VMODE = V–, Write l –1500 –1250 –1000 µA
Pin SDOI, TOS = V–, Read l 1000 1250 1500 µA
IOH1 Digital Output Current High Pin CSBO; TOS = V– l 0 2.5 5 µA
Pin SCKO; TOS = V– l 1000 1250 µA
Pin SDOI, TOS = V–, Write l 1000 1250 µA
Pin SDI, VMODE = V–, Read l –1000 µA
IOL1 Digital Output Current Low Pin CSBO; TOS = V– l 1000 1250 µA
Pin SCKO; TOS = V– l 0 2.5 5 µA
Pin SDOI, TOS = V–, Write l 0 2.5 5 µA
Pin SDI, VMODE = V–, Read l –5 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Dynamic supply current is higher due to gate charge being
may cause permanent damage to the device. Exposure to any Absolute delivered at the switching frequency during active balancing. See Gate
Maximum Rating condition for extended periods may affect device Drivers/Gate Drive Comparators and Voltage Regulator in the Operation
reliability and lifetime. section for more information on estimating these currents.
Note 2: The LTC3300-1 is tested under pulsed load conditions such Note 5: The zero current sense voltages given in the table are DC
that TJ ≈ TA. The LTC3300I-1 is guaranteed over the –40°C to 125°C thresholds. The actual zero current sense voltage seen in application will
operating junction temperature range and the LTC3300H-1 is guaranteed be closer to zero due to the slew rate of the winding current and the finite
over the –40°C to 150°C operating junction temperature. High junction delay of the current sense comparator.
temperatures degrade operating lifetimes; operating lifetime is derated Note 6: The mid-range value is the average of the minimum and maximum
for junction temperatures greater than 125°C. Note that the maximum readings within the group of six.
ambient temperature consistent with these specifications is determined by Note 7: This IC includes overtemperature protection intended to protect
specific operating conditions in conjunction with board layout, the rated the device during momentary overload conditions. The maximum junction
package thermal impedance and other environmental factors. The junction temperature may be exceeded when overtemperature protection is active.
temperature (TJ, in °C) is calculated from the ambient temperature Continuous operation above the specified maximum operating junction
(TA, in °C) and power dissipation (PD, in Watts) according to the formula: temperature may result in device degradation or failure.
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: When balancing more than one cell at a time, the individual cell
supply currents can be calculated from the values given in the table as
follows: First add the appropriate table entries cell by cell for the balancers
that are on. Second, for each additional balancer that is on, subtract 70µA
from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the
resultant sum for C6. For example, if all six balancers are on, the resultant
current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and
for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.

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 LTC3300-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

Minimum Cell Voltage Required

C6 Supply Current When Not Supply Current When Balancing for Primary Gate Drive vs
Balancing vs Temperature vs Temperature Normalized to 25°C Temperature
20 1.06 2.10
C6 = 21.6V 3.6V PER CELL
MATCH CURVE WITH TABLE ENTRY
1.04 2.05
18

IQ(ACTIVE)/IQ(ACTIVE AT 25°C)
CELL VOLTAGE RISING
1.02 2.00

VCELL(MIN) (V)
16
IQ(SD) (µA)

1.00 1.95 CELL VOLTAGE FALLING

14
0.98 TYP = 740µA 1.90
TYP = 560µA
12 TYP = 250µA
0.96 TYP = 70µA 1.85
TYP = 60µA
TYP = –70µA
10 0.94 1.80
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
33001 G01 33001 G02 33001 G03

Maximum Cell Voltage to Allow

Balancing vs Temperature VREG Load Regulation VREG Voltage vs Temperature
5.2 5.0 4.70
TA = 25°C IVREG = 10mA
5.1 4.69
CELL VOLTAGE RISING
5.0 4.9 4.68 C6 = 36V
4.9 4.67
VCELL(MAX) (V)

4.8 4.8 4.66 C6 = 9V

VREG (V)

VREG (V)
4.7 4.65
4.6 4.7 4.64
CELL VOLTAGE FALLING C6 = 36V
4.5 4.63
C6 = 9V
4.4 4.6 4.62
4.3 4.61
4.2 4.5 4.60
–50 –25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 50 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) IVREG (mA) TEMPERATURE (°C)
LT1372 • G10 33001 G05 33001 G06

VREG POR Voltage and Minimum

Secondary Gate Drive vs VREG Short-Circuit Current Limit
Temperature vs Temperature VRTONP, VRTONS vs Temperature
4.100 60 1.236
C6 = 21.6V C6 = 21.6V
59
4.075
1.224
58
4.050
57
VRTONP, VRTONS (V)

1.212
4.025 VREG RISING (POR) 56
IVREG (mA)
VREG (V)

4.000 55 1.200 VRTONP

54 VRTONS
3.975
1.188
53
3.950 VREG FALLING
(MIN SEC. GATE DRIVE 52
1.176
3.925 51

3.900 50 1.164
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
33001 G07 33001 G08 33001 G09

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LTC3300-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

VRTONP, VRTONS
vs External Resistance WDT Pin Current vs Temperature WDT Pin Current vs RTONS
1.236 85 240
TA = 25°C RTONS = 15k TA = 25°C
BALANCING
1.224 WDT = 0.5V 200
80
VRTONP, VRTONS (V)

1.212 160

IWDT (µA)

IWDT (µA)
1.200 75 120
BALANCING
SECONDARY OV WDT = 0.5V
1.188 WDT = 2V 80
VRTONS VRTONP 70
1.176 40 SECONDARY OV
WDT = 2V
1.164 65 0
1 10 100 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 45
RTONP, RTONS RESISTANCE (kΩ) TEMPERATURE (°C) RTONS (kΩ)
33001 G10 33001 G11 33001 G12

Peak Current Sense Threshold Zero Current Sense Threshold Primary Winding Switch Maximum
vs Temperature vs Temperature On-Time vs Temperature
55 5.0 8.4
VCELL = 3.6V RTONP = 20k
VCELL = 3.6V
RANDOM CELL SELECTED VCELL = 3.6V
RANDOM CELL SELECTED
2.5 8.0
53 PRIMARY
VZERO_P, VZERO_S (mV)

PRIMARY
VPEAK_P, VPEAK_S (mV)

0 7.6
51 tONP(MAX) (µs)
–2.5 7.2
SECONDARY
49 SECONDARY
–5.0 6.8

47 –7.5 6.4

–10.0 6.0
45 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
TEMPERATURE (°C)
33001 G14 33001 G15
33001 G13

Secondary Winding Switch Maximum On-Time Watchdog Timer Timeout Period

Maximum On-Time vs Temperature vs RTONP, RTONS vs Temperature
1.4 20 1.65
RTONS = 15k TA = 25°C
18
1.60
16
1.3
tONP(MAX),tONS(MAX) (µs)

14
1.55
tWD1 (SECONDS)
tONS(MAX) (µs)

12
PRIMARY
1.2 10 1.50
8
1.45
6
1.1
4
SECONDARY 1.40
2
1.0 0 1.35
–50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 45 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) RTONP, RTONS (kΩ) TEMPERATURE (°C)
33001 G16 33001 G17 33001 G18

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8 For more information www.linear.com/LTC3300-1

 LTC3300-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

CSBO Digital Output Current High CSBO Digital Output Current Low Balancer Efficiency
vs Temperature vs Temperature vs Cell Voltage
3.00 1500 93
TOS = V– TOS = V– DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A

CHARGE TRANSFER EFFICIENCY (%)

FOR 12-CELL STACK ONLY
1400
2.75 92

1300
IOH1 (µA)

IOL1 (µA)
2.50 91
1200

2.25 90 DISCHARGE, 12-CELL STACK

1100
DISCHARGE, 6-CELL STACK
CHARGE, 6-CELL STACK
CHARGE, 12-CELL STACK
2.00 1000 89
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
TEMPERATURE (°C) TEMPERATURE (°C) VOLTAGE PER CELL (V)
33001 G19 33001 G20 33001 G21

Balance Current vs Cell Voltage Typical Charge Waveforms Typical Discharge Waveforms
2.7
CHARGE, 12-CELL STACK
I1S I1P
2.6 50mV/DIV 50mV/DIV

I1P
BALANCE CURRENT (A)

I1S
2.5 DISCHARGE, 12-CELL STACK 50mV/DIV 50mV/DIV
PRIMARY SECONDARY
DRAIN DRAIN
2.4
DISCHARGE, 6-CELL STACK 50V/DIV 50V/DIV
SECONDARY PRIMARY
2.3 DC2064A DEMO BOARD DRAIN DRAIN
ICHARGE = IDISCHARGE = 2.5A 50V/DIV 33001 G23 50V/DIV
FOR 12-CELL STACK ONLY 2µs/DIV 2µs/DIV 33001 G24

2.2 DC2064A DEMO BOARD DC2064A DEMO BOARD

ICHARGE = 2.5A IDISCHARGE = 2.5A
CHARGE, 6-CELL STACK T=2 T=2
2.1 S = 12 S = 12
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
VOLTAGE PER CELL (V)
33001 G22

Protection for Broken Connection

Protection for Broken Connection to Secondary Stack While Changing Balancer Direction
to Cell While Charging Discharging “On the Fly”
~5.2V SCKI 2ms
~66V 5V/DIV
C1 PIN
SECONDARY CHARGING
1V/DIV 3.6V
STACK VOLTAGE I1P
CONNECTION TO CONNECTION TO DISCHARGING
10V/DIV 43.2V 50mV/DIV
C1 BROKEN STACK BROKEN

BALANCING
G1P G1P G1P
SHUTS OFF BALANCING
2V/DIV 2V/DIV 2V/DIV
SHUTS OFF

33001 G26
50µs/DIV 33001 G25
500µs/DIV 20µs/DIV 33001 G27

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LTC3300-1
PIN FUNCTIONS
Note: The convention adopted in this data sheet is to refer CSBI (Pin 16): Chip Select (Active Low) Input. The CSBI
to the transformer winding paralleling an individual battery pin interfaces to a rail-to-rail output logic gate if VMODE
cell as the primary and the transformer winding paralleling is tied to VREG. CSBI must be driven by the CSBO pin of
multiple series-stacked cells as the secondary, regardless another LTC3300-1 if VMODE is tied to V–. See Serial Port
of the direction of energy transfer. in the Applications Information section.
G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9, SCKI (Pin 17): Serial Clock Input. The SCKI pin interfaces
11): G1S through G6S are gate driver outputs for driving to a rail-to-rail output logic gate if VMODE is tied to VREG.
external NMOS transistors connected in series with the SCKI must be driven by the SCKO pin of another LTC3300-1
secondary windings of transformers whose primaries are if VMODE is tied to V–. See Serial Port in the Applications
connected in parallel with battery cells 1 through 6. For Information section.
the minimum part count balancing application employing SDI (Pin 18): Serial Data Input. When writing data to the
a single transformer (CTRL = VREG), G2S through G6S LTC3300-1, the SDI pin interfaces to a rail-to-rail output
are no connects.
logic gate if VMODE is tied to VREG or must be driven by
I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 10, 12): I1S the SDOI pin of another LTC3300-1 if VMODE is tied to V–.
through I6S are current sense inputs for measuring sec- See Serial Port in the Applications Information section.
ondary winding current in transformers whose primaries
SDO (Pin 19): Serial Data Output. When reading data
are connected in parallel with battery cells 1 through 6.
from the LTC3300-1, the SDO pin is an NMOS open-drain
For the minimum part count balancing application employ-
output if VMODE is tied to VREG. The SDO pin is not used
ing a single transformer (CTRL = VREG), I2S through I6S if VMODE is tied to V–. See Serial Port in the Applications
should be tied to V–. Information section.
RTONS (Pin 13): Secondary Winding Max tON Setting
WDT (Pin 20): Watchdog Timer Output (Active High). At
Resistor. The RTONS pin servos to 1.2V. A resistor to V–
initial power-up and when not attempting to execute a valid
programs the maximum on-time for all external NMOS
balance command, the WDT pin is high impedance and will
transistors connected in series with secondary windings.
be pulled high (internally clamped to ~5.6V) if an external
This protects against a short-circuited current sense re-
pull-up resistor is present. While balancing (or attempt-
sistor in any secondary winding. To defeat this function, ing to balance but not able to due to voltage/temperature
connect RTONS to VREG. The secondary winding OVP faults) and during normal communication activity, the WDT
threshold (see WDT pin) is also slaved to the value of the
pin is pulled low by a precision current source slaved to
RTONS resistor.
the RTONS resistor. However, if no valid command byte is
RTONP (Pin 14): Primary Winding Max tON Setting written for 1.5 seconds (typical), the WDT output will go
Resistor. The RTONP pin servos to 1.2V. A resistor to V– back high. When WDT is high, all balancers are off. The
programs the maximum on-time for all external NMOS watchdog timer function can be disabled by connecting
transistors connected in series with primary windings. WDT to V–. The secondary winding OVP function can also
This protects against a short-circuited current sense be implemented using this pin (See Operation section).
resistor in any primary winding. To defeat this function, V– (Pin 21): Connect V– to the most negative potential in
connect RTONP to VREG. the series of cells.
CTRL: (Pin 15): Control Input. The CTRL pin configures
I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37):
the LTC3300-1 for the minimum part count application
I1P through I6P are current sense inputs for measuring
employing a single transformer if CTRL is tied to VREG or
primary winding current in transformers connected in
for the multiple transformer application if CTRL is tied to
parallel with battery cells 1 through 6.
V–. This pin must be tied to either VREG or V–.

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 LTC3300-1
PIN FUNCTIONS
G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35, SCKO (Pin 44): Serial Clock Output. SCKO is a buffered
38): G1P through G6P are gate driver outputs for driving and one-shotted version of the serial clock input, SCKI,
external NMOS transistors connected in series with the when CSBI is low. SCKO drives the next IC higher in the
primary windings of transformers connected in parallel daisy chain. See Serial Port in the Applications Informa-
with battery cells 1 through 6. tion section.
C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39): CSBO (Pin 45): Chip Select (Active Low) Output. CSBO
C1 through C6 connect to the positive terminals of bat- is a buffered version of the chip select input, CSBI. CSBO
tery cells 1 through 6. Connect the negative terminal of drives the next IC higher in the daisy chain. See Serial Port
battery cell 1 to V–. in the Applications Information section.
BOOST+ (Pin 40): Boost+ Pin. Connects to the anode of VMODE (Pin 46): Voltage Mode Input. When VMODE is tied
the external flying capacitor used for generating sufficient to VREG, the CSBI, SCKI, SDI and SDO pins are configured
gate drive necessary for balancing the topmost battery cell as voltage inputs and outputs. This means these pins
in a given LTC3300-1 sub-stack. A Schottky diode from C6 accept VREG-referred rail-to-rail logic levels. Connect
to BOOST+ is needed as well. Alternately, the BOOST+ pin VMODE to VREG when the LTC3300-1 is the bottom device
can connect to one cell up in the above sub-stack (if pres- in a daisy chain.
ent). This pin is effectively C7. (Note: “Sub-stack” refers When VMODE is tied to V–, the CSBI, SCKI and SDI pins
to the 3-6 battery cells connected locally to an individual are configured as current inputs and outputs, and SDO is
LTC3300-1 as part of a larger stack.)
unused. Connect VMODE to V– when the LTC3300-1 is be-
BOOST– (Pin 41): Boost– Pin. Connects to the cathode of ing driven by another LTC3300-1 lower in the daisy chain.
the external flying capacitor used for generating sufficient This pin must be tied to either VREG or V­–.
gate drive necessary for balancing the topmost battery cell TOS (Pin 47): Top Of Stack Input. Tie TOS to VREG when
in a given LTC3300-1 sub-stack. Alternately, if the BOOST+ the LTC3300-1 is the top device in a daisy chain. Tie TOS
pin connects to the next higher cell in the above sub-stack
to V– when the LTC3300-1 is any other device in the daisy
(if present), this pin is a no connect. chain. When TOS is tied to VREG, the LTC3300-1 ignores
BOOST (Pin 42): Enable Boost Pin. Connect BOOST to VREG the SDOI input. When TOS is tied to V–, the LTC3300-1
to enable the boosted gate drive needed for balancing the expects data to be passed to and from the SDOI pin. This
top cell in a given LTC3300-1 sub-stack. If the BOOST+ pin pin must be tied to either VREG or V–.
can be connected to the next cell up in the stack (i.e., C1 VREG (Pin 48): Linear Voltage Regulator Output. This 4.8V
of the next LTC3300-1 in the stack), then BOOST should output should be bypassed with a 1µF or larger capacitor
be tied to V– and BOOST– no connected. This pin must to V–. The VREG pin is capable of supplying up to 40mA
be tied to either VREG or V–. to internal and external loads. The VREG pin does not sink
SDOI (Pin 43): Serial Data Output/Input. SDOI transfers current.
data to and from the next IC higher in the daisy chain when V– (Exposed Pad Pin 49): The exposed pad should be
writing and reading. See Serial Port in the Applications connected to a continuous (ground) plane biased at V– on
Information section. the second layer of the printed circuit board by several
vias directly under the LTC3300-1.

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LTC3300-1
BLOCK DIAGRAM
48 41 40
VREG BOOST – BOOST +
C6
C6
40mA
MAX VREG
BOOST BOOST
VOLTAGE THERMAL
4.8V SD GATE DRIVE 42
REGULATOR SHUTDOWN
GENERATOR

POR C6
V– 39
BOOST+

G6P
38

CSBO C5
45 C5 I6P
+

+
CONTROLLER
37

BALANCER
2
SCKO
– 50mV/0
44 –
0/50mV
+ I6S
2
SDOI
43 VREG

LEVEL-SHIFTING G6S
SERIAL 1
INTERFACE
V– PINS 3 TO 10,
DATA
6-CELL 25 TO 36
12
PACKET ERROR

SYNCHRONOUS
CRC/RCRC

CHECKING

16 FLYBACK
STATUS
CONTROLLER
12
BALANCER

C1
24
SDO C2
19
G1P
23
SDI
18
V– I1P
+
CONTROLLER

22
BALANCER

SCKI WATCHDOG ACTIVE 2

17 TIMER
– 50mV/0
–
0/50mV
CSBI + I1S
16 12
VREG
WDT RESET
20 G1S
11
5.6V
V– V–
V–
MAX ON-TIME
1.2V VOLT-SEC
RTONS CLAMPS

EXPOSED
V– PAD TOS VMODE CTRL V– RTONS RTONP
21 49 47 46 15 13 14
33001 BD

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12 For more information www.linear.com/LTC3300-1

 LTC3300-1
TIMING DIAGRAM
Timing Diagram of the Serial Interface

t1 t4
t2 t3 t6 t7

SCKI

SDI

t5

CSBI

t8

SDO

33001 TD

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LTC3300-1
OPERATION
Battery Management System (BMS) In the process of bringing the cells into balance, the over-
all stack is slightly discharged. The charger component
The LTC3300-1 multicell battery cell balancer is a key
provides a means for net charging of the entire stack from
component in a high performance battery management
an alternate power source.
system (BMS) for series-connected Li-Ion cells. It is de-
signed to operate in conjunction with a monitor, a charger, The last component in the BMS is a microprocessor/
and a microprocessor or microcontroller (see Figure 1). microcontroller which communicates directly with the
The function of the balancer is to efficiently transfer charge balancer, monitor, and charger to receive voltage, current,
to/from a given out-of-balance cell in the stack from/to and temperature information and to implement a balanc-
ing algorithm.
a larger group of neighboring cells (which includes that
individual cell) in order to bring that cell into voltage or There is no single balancing algorithm optimal for all
capacity balance with its neighboring cells. Ideally, this situations. For example, during net charging of the overall
charge would always be transferred directly from/to the stack, it may be desirable to discharge the highest voltage
entire stack, but this is impractical for voltage reasons cells first to avoid reaching terminal charge on any cell
when the number of cells in the overall stack is large. The before the entire stack is fully charged. Similarly, during
LTC3300-1 is designed to interface to a group of up to 6 net discharging of the overall stack, it may be desirable
series cells, so the number of LTC3300-1 ICs required to charge the lowest voltage cells first to keep them from
to balance a series stack of N cells is N/6 rounded up to reaching a critically low level. Other algorithms may
the nearest integer, with no limitation imposed on how prioritize fastest time to overall balance. The LTC3300-1
large N can be. For connecting an individual LTC3300-1 implements no algorithm for balancing the stack. Instead it
in the stack to fewer than 6 cells, refer to the Applications provides maximum flexibility by imposing no limitation on
Information section. the algorithm implemented as all individual cell balancers
can operate simultaneously and bidirectionally.
Because the balancing function entails switching large
(multiampere) currents between cells, precision voltage Unidirectional Versus Bidirectional Balancing
monitoring in the BMS is better served by a dedicated
monitor component such as the LTC6803-1 or one of its Most balancers in use today employ a unidirectional (dis-
family of parts. The LTC6803-1 provides for high precision charge only) approach. The simplest of these operate by
A/D monitoring of up to 12 series cells. The only voltage switching in a resistor across the highest voltage cell(s)
monitoring provided by the LTC3300-1 is a coarse “out- in the stack (passive balancing). No charge is recovered
of-range” overvoltage and undervoltage cell balancing in this approach -instead it is dissipated as heat in the
disqualification, which provides a safety shutoff in the resistive element. This can be improved by employing an
event Kelvin sensing to the monitor component is lost. energy storage element (inductive or capacitive) to transfer

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14 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
TOP OF STACK
+ CELL N
ICHARGE
C6 C5 C11 C12 ILOAD
+
CELL N – 1
C4 C10
+ CELL N – 2
LTC3300-1
BALANCER C3 C9
+ CELL N – 3
C2 C8
+ CELL N – 4
V– C1 C7
+ CELL N – 5
SERIAL
C6 LTC6803-1
COMMUNICATION + CELL N – 6
MONITOR
C6 C5 C5
+ CELL N – 7
C4 C4
+ CELL N – 8
LTC3300-1
C3 C3
BALANCER + CELL N – 9
C2 C2
+ CELL N – 10
V– C1 C1 V–
CN + CELL N – 11

SERIAL • • • SERIAL
CHARGER • • •
COMMUNICATION • • • COMMUNICATION

+ CELL 12
V– C6 C12
C5 C11
+ CELL 11
C4 C10
LTC3300-1 + CELL 10
BALANCER
C3 C9
+ CELL 9
C2 C8
+ CELL 8
V– C1 C7
+ CELL 7
LTC6803-1
SERIAL MONITOR
C6
COMMUNICATION + CELL 6
C6 C5 C5
+ CELL 5
C4 C4
LTC3300-1 + CELL 4
BALANCER C3
C3
+ CELL 3
C2 + C2
CELL 2
–
V C1
+ C1 V–
CELL 1
VCC
µP/µC 33001 F01

VEE SERIAL COMMUNICATION BUS

Figure 1. LTC3300-1/LTC6803-1 Typical Battery Management System (BMS)

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LTC3300-1
OPERATION
charge from the highest voltage cell(s) in the stack to other Synchronous Flyback Balancer
lower voltage cells in the stack (active balancing). This The balancing architecture implemented by the LTC3300‑1
can be very efficient (in terms of charge recovery) for the is bidirectional synchronous flyback. Each LTC3300-1
case where only a few cells in the overall stack are high, contains six independent synchronous flyback controllers
but will be very inefficient (and time consuming) for the that are capable of directly charging or discharging an
case where only a few cells in the overall stack are low. A individual cell. Balance current is scalable with external
bidirectional active balancing approach, such as employed components. Each balancer operates independently of
by the LTC3300-1, is needed to achieve minimum balanc- the others and provides a means for bidirectional charge
ing time and maximum charge recovery for all common
transfer between an individual cell and a larger group of
cell capacity errors.
adjacent cells. Refer to Figure 2.

Single-Cell Discharge Cycle for Cell 1 Single-Cell Charge Cycle for Cell 1

IPEAK_PRI = 2A IPEAK_SEC = 2A
VCC (I1P = 50mV) (I1S = 50mV)

IPRIMARY ISECONDARY
ICHARGE

VTOP_OF_STACK
5µs t t
+ CELL N ILOAD
~417ns
2A 2A

ISECONDARY
+ CELL 13 –ISECONDARY –IPRIMARY

(48V)
+ CELL 12 t 5µs t
~417ns
50mV
52.05V 52V 52V
48V 48V
+ CELL 2
IPRIMARY

T:1 (4V) VPRIMARY VSECONDARY

•
LPRI
+ CELL 1
10µH 4V 50mV 4V 50mV
t t
VSECONDARY
• VPRIMARY

G1S G1P 52V 50mV 52V 51.95V

48V 48V

I1S I1P
RSNS_SEC RSNS_PRI VSECONDARY VPRIMARY
25mΩ 25mΩ

4V 4V
50mV t 50mV t
33001 F02

Figure 2. Synchronous Flyback Balancing Example with T = 1, S = 12

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16 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
Cell Discharging (Synchronous) (detected at the In S pin), the secondary switch is turned
When discharging is enabled for a given cell, the primary off and current then flows in the primary side thus charging
side switch is turned on and current ramps in the primary the selected cell from the entire stack of secondary cells. As
winding of the transformer until the programmed peak with the discharging case, the primary-side synchronous
current (IPEAK_PRI) is detected at the In P pin. The primary switch is turned on to minimize power loss during the cell
side switch is then turned off, and the stored energy in charging phase. Once the primary current drops to zero,
the transformer is transferred to the secondary-side cells the primary switch is turned off and the secondary-side
causing current to flow in the secondary winding of the switch is turned back on thus repeating the cycle.
transformer. The secondary-side synchronous switch IPEAK_SEC is programmed using the following equation:
is turned on to minimize power loss during the transfer 50mV
period until the secondary current drops to zero (detected IPEAK _ SEC =
at In S). Once the secondary current reaches zero, the RSNS_ SEC

secondary switch turns off and the primary-side switch
is turned back on thus repeating the cycle. In this manner, Cell charge current and corresponding secondary-side
charge is transferred from the cell being discharged to all discharge current are determined to first order by the
of the cells connected between the top and bottom of the following equations:
secondary side—thereby charging the adjacent cells. In the IPEAK _ SEC ⎛ ST ⎞
example of Figure 2, the secondary-side connects across ICHARGE = ⎜⎝ ⎟ η
2 S+ T ⎠ CHARGE
12 cells including the cell being discharged.
IPEAK_PRI is programmed using the following equation: IPEAK _ SEC ⎛ T ⎞
ISECONDARY = ⎜⎝ ⎟
2 S+ T ⎠
50mV
IPEAK _PRI =
RSNS_PRI where S is the number of secondary cells in the stack, 1:T

is the transformer turns ratio from primary to secondary,
Cell discharge current (primary side) and secondary-side and ηCHARGE is the transfer efficiency from secondary-side
charge recovery current are determined to first order by stack discharge to the primary-side cell.
the following equations:
Each balancer’s charge transfer “frequency” and duty
I ⎛ S ⎞ factor depend on a number of factors including IPEAK_PRI,
IDISCHARGE = PEAK _PRI ⎜
2 ⎝ S+ T ⎟⎠ IPEAK_SEC, transformer winding inductances, turns ratio,
cell voltage and the number of secondary-side cells.
IPEAK _PRI ⎛ 1 ⎞
ISECONDARY = ⎜⎝ ⎟ η The frequency of switching seen at the gate driver outputs
2 S+ T ⎠ DISCHARGE is given by:
where S is the number of secondary-side cells, 1:T is the S VCELL
fDISCHARGE = •
transformer turns ratio from primary to secondary, and S+ T LPRI •IPEAK _PRI
ηDISCHARGE is the transfer efficiency from primary cell
discharge to the secondary side stack. S VCELL
fCHARGE = •
S+ T LPRI •IPEAK _ SEC • T
Cell Charging
where LPRI is the primary winding inductance.
When charging is enabled for a given cell, the secondary-
side switch for the enabled cell is turned on and current Figure 3 shows a fully populated LTC3300-1 application
flows from the secondary-side cells through the trans- employing all six balancers.
former. Once IPEAK_SEC is reached in the secondary side
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LTC3300-1
OPERATION
0.1µF 6.8Ω
UP TO •
–
CELL 12 ••
BOOST BOOST+
C6
1:1
10µF •
10µH 10µH

•
G6P
+
CELL 6
I6P
25mΩ
G6S

I6S
25mΩ

C5
1:1
10µF •
10µH 10µH

•
G5P
+
I5P CELL 5
25mΩ
G5S

I5S
25mΩ

C4
LTC3300-1 • •
C3 • •
• •
C2
1:1
10µF •
10µH 10µH

•
CSBO G2P
SCKO
+
CELL 2
SDOI I2P
25mΩ
SERIAL CSBI
COMMUNICATION SCKI G2S
RELATED SDI
PINS SDO I2S
25mΩ
TOS
VMODE C1
WDT 1:1
10µF •
10µH 10µH

•
G1P
+
I1P CELL 1

25mΩ
VREG G1S
BOOST
I1S
25mΩ

V–
CTRL RTONP RTONS
•
10µF 22.6k 6.98k •
•
33001 F03

Figure 3. LTC3300-1 6-Cell Active Balancer Module Showing Power Connections for the Multi-Transformer Application (CTRL = V–)
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18 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
Balancing High Voltage Battery Stacks TOP

Balancing series connected batteries which contain >>12 LTC3300-1

PRI POWER STAGES SEC
cells in series requires interleaving of the transformer sec- •
+
ondary connections in order to achieve full stack balancing CELL N

while limiting the breakdown voltage requirements of the •

•
primary- and secondary-side power FETs. Figure 4 shows FROM CELL N-12 •
•
SECONDARY
typical interleaved transformer connections for a multicell +
•

battery stack in the generic sense, and Figure 5 for the CELL N-6

specific case of an 18-cell stack. In these examples, the •

secondary side of each transformer is connected to the TO CELL 24

•
top of the cell that is 12 positions higher in the stack than LTC3300-1
•
•
the bottom of the lowest voltage cell in each LTC3300-1 SEC POWER STAGES PRI
•
sub-stack. For the top most LTC3300-1 in the stack, it is +
CELL 18
not possible to connect the secondary side of the trans-
•
former across 12 cells. Instead, it is connected to the top •
•
of the stack, or effectively across only 6 cells. Interleaving •
•

in this fashion allows charge to transfer between 6-cell +

CELL 13
sub-stacks throughout the entire battery stack. •
LTC3300-1
PRI POWER STAGES SEC
Max On-Time Volt-Sec Clamps •
+
The LTC3300-1 contains programmable fault protection CELL 12

clamps which limit the amount of time that current is •

•
allowed to ramp in either the primary or secondary wind- •
•
ings in the event of a shorted sense resistor. Maximum •
+
on time for all primary connections (active during cell CELL 7

discharging) and all secondary connections (active during LTC3300-1 •

SEC POWER STAGES PRI
cell charging) is individually programmable by connecting •
resistors from the RTONP and RTONS pins to V– according +
CELL 6
to the following equations: • •
+
R TONP CELL 5
tON(MAX)|PRIMARY = 7.2µs
20kΩ • •
+
CELL 4
R
tON(MAX)|SECONDARY = 1.2µs TONS • •
15kΩ +
CELL 3

For more information on selecting the appropriate • •

+
maximum on-times, refer to the Applications Information CELL 2

section. • •
+
CELL 1
To defeat this function, short the appropriate RTON pin(s) •
to VREG.
33001 F04

Figure 4. Diagram of Power Transfer Interleaving Through the

Stack, Transformer Connections for High Voltage Stacks
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For more information www.linear.com/LTC3300-1 19

LTC3300-1
OPERATION
0.1µF
6.8Ω

BOOST– BOOST+ C6

TO TRANSFORMER
+
CELL 18
SECONDARIES OF
BALANCERS 14 TO 18
C1
•1:1
10µF 10µH 10µH

LTC3300-1 •
G1P
+
I1P CELL 13
25mΩ
G1S
I1S
VREG 25mΩ
BOOST V–

BOOST+ C6
TO TRANSFORMER
+
CELL 12
SECONDARIES OF
BALANCERS 8 TO 12
C1
•1:1
10µF 10µH 10µH

LTC3300-1 •
G1P
+
I1P CELL 7
25mΩ
G1S
I1S
25mΩ
BOOST V–

BOOST+ C6
TO TRANSFORMER
+
CELL 6
SECONDARIES OF
BALANCERS 2 TO 6
C1
•1:1
10µF 10µH 10µH

LTC3300-1 •
G1P
+
I1P CELL 1
25mΩ
G1S
I1S
25mΩ
BOOST V–
33001 F05

Figure 5. 18-Cell Active Balancer Showing Power Connections,

Interleaved Transformer Secondaries and BOOST+ Rail Generation Up the Stack
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20 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
Gate Drivers/Gate Drive Comparators low pass filtered and the outputs are filtered so as to
All secondary-side gate drivers (G1S through G6S) are not transition unless the internal comparator state is
unchanged for 3µs to 6µs (typical). If insufficient gate drive
powered from the VREG output, pulling up to 4.8V when
on and pulling down to V– when off. All primary-side is detected while active balancing is in progress (perhaps,
gate drivers (G1P through G6P) are powered from their for example, if the stack is under heavy load), the affected
respective cell voltage and the next cell voltage higher in balancer(s) and only the affected balancer(s) will shut off.
the stack (see Table 1). An individual cell balancer will only The balance command remains stored in memory, and
be enabled if its corresponding cell voltage is greater than active balancing will resume where it left off if sufficient
2V and the cell voltage of the next higher cell in the stack gate drive is subsequently restored. This can happen if,
is also greater than 2V. For the G6P gate driver output, for example, the stack is being charged.
the next higher cell in the stack is C1 of the next higher
Cell Overvoltage Comparators
LTC3300-1 in the stack (if present) and is only used if the
boosted gate drive is disabled (by connecting BOOST = In addition to sufficient gate drive being required to enable
V–). If the boosted gate drive is enabled (by connecting balancing, there are additional comparators which disable
BOOST = VREG), only the C6 cell voltage is looked at to all active balancing if any of the six individual cell voltages
enable balancing of Cell 6. In the case of the topmost is greater than 5V. These comparators have a DC hysteresis
LTC3300-1 in the stack, the boosted gate drive must be of 500mV. For improved noise immunity, the inputs are
enabled. The boosted gate drive requires an external diode internally low pass filtered and the outputs are filtered so
from C6 to BOOST+ and a boost capacitor from BOOST+ to as to not transition unless the internal comparator state
BOOST–. For information on selecting these components, is unchanged for 3µs to 6µs (typical). If any cell voltage
refer to the Applications Information section. Also note goes overvoltage while active balancing is in progress,
that the dynamic supply current referred to in Note 4 of all active balancers will shut off. The balance command
the Electrical Characteristics table adds to the terminal remains stored in memory, and active balancing will resume
currents of the pins indicated in the Voltage When Off and where if left off if the cell voltage subsequently comes back
Voltage When On columns of Table 1. in range. These comparators will protect the LTC3300-1 if
a connection to a battery is lost while balancing and the
The gate drive comparators have a DC hysteresis of 70mV.
cell voltage is still increasing as a result of that balancing.
For improved noise immunity, the inputs are internally

Table 1
DRIVER OUTPUT VOLTAGE WHEN OFF VOLTAGE WHEN ON GATE DRIVE REQUIRED TO ENABLE BALANCING
G1P V- C2 (C2 – C1) ≥ 2V and (C1 – V–) ≥2V
G2P C1 C3 (C3 – C2) ≥ 2V and (C2 – C1) ≥2V
G3P C2 C4 (C4 – C3) ≥ 2V and (C3 – C2) ≥2V
G4P C3 C5 (C5 – C4) ≥ 2V and (C4 – C3) ≥2V
G5P C4 C6 (C6 – C5) ≥ 2V and (C5 – C4) ≥2V
G6P C5 If BOOST = VREG: BOOST+ (Generated) (C6 – C5) ≥ 2V
If BOOST = V–: BOOST+ = C7* (C7* – C6) ≥ 2V and (C6 – C5) ≥ 2V
*C7 is equal to C1 of the next higher LTC3300-1 in the stack if this connection is used.

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LTC3300-1
OPERATION
Voltage Regulator Thermal Shutdown
A linear voltage regulator powered from C6 creates a The LTC3300-1 has an overtemperature protection circuit
4.8V rail at the VREG pin which is used for powering which shuts down all active balancing if the internal silicon
certain internal circuitry of the LTC3300-1 including all 6 die temperature rises to approximately 155°C. When in
secondary gate drivers. The VREG output can also be used thermal shutdown, all serial communication remains active
for powering external loads, provided that the total DC and the cell balancer status (which contains temperature
loading of the regulator does not exceed 40mA at which information) can be read back. The balance command
point current limit is imposed to limit on-chip power dis- which had been being executed remains stored in memory.
sipation. The internal component of the DC load current This function has 10°C of hysteresis so that when the die
is dominated by the average gate driver current(s) (G1S temperature subsequently falls to approximately 145°C,
through G6S), each approximated by C • V • f, where C active balancing will resume with the previously execut-
is the gate capacitance of the external NMOS transistor, ing command.
V = VREG = 4.8V, and f is the frequency that the gate
driver output is running at. FET manufacturers usually Watchdog Timer Circuit
specify the C • V product as Qg (gate charge) measured The watchdog timer circuit provides a means of shutting
in coulombs at a given gate drive voltage. The frequency, down all active balancing in the event that communica-
f, is dependent on many terms, primarily the voltage of tion to the LTC3300-1 is lost. The watchdog timer initiates
each individual cell, the number of cells in the secondary when a balance command begins executing and is reset
stack, the programmed peak balancing current, and the to zero every time a valid 8-bit command byte (see Serial
transformer primary and secondary winding inductances. Port Operation) is written. The valid command byte can
In a typical application, the C • V • f current loading the be an execute, a write, or a read (command or status).
VREG output is expected to be low single-digit milliamperes “Partial” reads and writes are considered valid, i.e., it is
per driver. Note that the VREG loading current is ultimately only necessary that the first 8 bits have to be written and
delivered from the C6 pin. For applications involving very contain the correct address.
large balance currents and/or employing external NMOS
transistors with very large gate capacitance, the VREG Referring to Figure 6a, at initial power-up and when not
output may need to source more than 40mA average. For balancing, the WDT pin is high impedance and will be
information on how to design for these situations, refer pulled high (internally clamped to ~5.6V) if an external
to the Applications Information section. pull-up resistor is present. While balancing and during
normal communication activity, the WDT pin is pulled
One additional function slaved to the VREG output is low by a precision current source equal to 1.2V/RTONS.
the power-on reset (POR). During initial power-up and (Note: if the secondary volt-second clamp is defeated
subsequently if the VREG pin voltage ever falls below ap- by connecting RTONS to VREG, the watchdog function is
proximately 4V (e.g., due to overloading), the serial port also defeated.) If no valid command byte is written for
is cleared to the default power-up state with no balancers 1.5 seconds (typical), the WDT output will go back high.
active. This feature thus guarantees that the minimum gate When WDT is high, all balancers will be shut down but
drive provided to the external secondary side FETs is also the previously executing balance command still remains
4V. For a 10µF capacitor loading the output at initial power- in memory. From this timed-out state, a subsequent valid
up, the output reaches regulation in approximately 1ms. command byte will reset the timer, but the balancers will

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22 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
only restart if an execute command is written. To defeat out, externally pulling the WDT pin high will immediately
the watchdog function, simply connect the WDT pin to V–. pause balancing, and it will resume where it left off when
the pin is released.
Pause/Resume Balancing (via WDT Pin)
Secondary Winding OVP Function (via WDT pin)
The WDT output pin doubles as a logic input (TTL levels)
which can be driven by an external logic gate as shown in The precision current source pull-down on the WDT pin
Figure 6b (no watchdog), or by a PMOS/three-state logic during balancing can be used to construct an accurate
gate as shown in Figure 6c (with watchdog) to pause and secondary winding OVP protection circuit as shown in
resume balancing in progress. The external pull-up must Figure 6c. A second external resistor, scaled to RTONS
have sufficient drive capability to override the current source and connected to the transformer secondary winding, is
to ground at the WDT pin (=1.2V/RTONS). Provided that used to set the comparator threshold. An NMOS cascode
the internal watchdog timer has not independently timed device (with gate tied to VREG) is also needed to protect

VREG VREG
VTH = 1.4V LTC3300-1
LTC3300-1
RWDT WDT
WDT PAUSE/
RESUME

ACTIVE 5.6V
ACTIVE 5.6V
RTONS
RTONS 1.2V
1.2V RTONS
RTONS RTONS
RTONS
V–
33001 F06b
33001 F06a

(6a) Watchdog Timer Only (WDT = V– to Defeat) (6b) Pause/Resume Balancing Only

TO TRANSFORMER
SECONDARY WINDINGS
VREG
RSEC_OVP

LTC3300-1 PAUSE/
VREG
RESUME
WDT

EITHER/OR
ACTIVE 5.6V VREG VREG
RTONS PAUSE/
1.2V RESUME
RTONS
RTONS

33001 F06c

(6c) Watchdog Timer with Pause/Resume Balancing and Secondary Winding OVP Protection
Figure 6. WDT Pin Connection Options

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LTC3300-1
OPERATION
the WDT pin from high voltage. The secondary winding be daisy chained by connecting the high side port of the
OVP thresholds are given by: bottom device to the low side port of the top device. With
this arrangement, the master writes to or reads from the
VSEC|OVP(RISING) = 1.4V + 1.2V • (RSEC_OVP/RTONS)
cascaded devices as if they formed one long shift register.
VSEC|OVP(FALLING) = 1.4V + 1.05V • (RSEC_OVP/RTONS) The LTC3300-1 translates the voltage level of the signals
This comparator will protect the LTC3300-1 application between the low side and high side ports to pass data up
circuit if the secondary winding connection to the battery and down the battery stack.
stack is lost while balancing and the secondary winding
voltage is still increasing as a result of that balancing. The Physical Layer
balance command remains stored in memory, and active On the LTC3300-1, seven pins comprise the low side and
balancing will resume where it left off if the stack voltage high side ports. The low side pins are CSBI, SCKI, SDI
subsequently falls to a safer level. and SDO. The high side pins are CSBO, SCKO and SDOI.
CSBI and SCKI are always inputs, driven by the master
Single Transformer Application (CTRL = VREG) or by the next lower device in a stack. CSBO and SCKO
Figure 7 shows a fully populated LTC3300-1 application are always outputs that can drive the next higher device
employing all six balancers with a single shared custom in a stack. SDI is a data input when writing to a stack of
transformer. In this application, the transformer has six devices. For devices not at the bottom of a stack, SDI is a
primary windings coupled to a single secondary winding. data output when reading from the stack. SDOI is a data
Only one balancer can be active at a given time as all six output when writing to and a data input when reading from
share the secondary gate driver G1S and secondary current a stack of devices. SDO is an open-drain output that is
sense input I1S. The unused gate driver outputs G2S-G6S only used on the bottom device of a stack, where it may
must be left floating and the unused current sense inputs be tied with SDI, if desired, to form a single, bidirectional
I2S-I6S should be connected to V–. Any balance command port. The SDO pin on the bottom device of a stack requires
which attempts to operate more than one balancer at a time a pull-up resistor. For devices up in the stack, SDO should
will be ignored. This application represents the minimum be tied to the local V– or left floating.
component count active balancer achievable. To communicate between daisy-chained devices, the high
SERIAL PORT OPERATION side port pins of a lower device (CSBO, SCKO and SDOI)
should be connected through high voltage diodes to the
Overview respective low side port pins of the next higher device
(CSBI, SCKI and SDI). In this configuration, the devices
The LTC3300-1 has an SPI bus compatible serial port. communicate using current rather than voltage. To signal
Several devices can be daisy chained in series. There are a logic high from the lower device to the higher device,
two sets of serial port pins, designated as low side and the lower device sinks a smaller current from the higher
high side. The low side and high side ports enable devices device pin. To signal a logic low, the lower device sinks
to be daisy chained even when they operate at different a larger current. Likewise, to signal a logic high from
power supply potentials. In a typical configuration, the the higher device to the lower device, the higher device
positive power supply of the first, bottom device is con- sources a larger current to the lower device pin. To signal
nected to the negative power supply of the second, top
a logic low, the higher device sources a smaller current.
device. When devices are stacked in this manner, they can

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24 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
0.1µF
6.8Ω

•
BOOST– BOOST+ • UP TO CELL 12
•
C6 EACH
1:1 •

10µF 10µH

•
G6P
I6P
+ 25mΩ
CELL 6
C5
10µH
10µF
•
G5P
I5P
+ 25mΩ
CELL 5
C4
10µH
10µF
•
G4P
I4P
+ 25mΩ
CELL 4
C3
LTC3300-1
10µH
10µF
•
G3P
I3P
+ 25mΩ
CELL 3
C2
10µH
10µF
•
CSBO G2P
SCKO I2P
SDOI
+ 25mΩ
SERIAL CSBI CELL 2
COMMUNICATION SCKI C1
RELATED SDI
10µH
PINS SDO
10µF
TOS •
VMODE G1P
WDT
I1P
25mΩ
VREG G1S
BOOST I1S
G2S-G6S NC + 25mΩ
CELL 1
I2S-I6S
CTRL V–
33001 F07
RTONP RTONS

10µF 22.6k 6.98k

Figure 7. LTC3300-1 6-Cell Active Balancer Module Showing Power Connections For The Single Transformer Application (CTRL = VREG)
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LTC3300-1
OPERATION
Transmission Format (Write)

CSBI

SCKI

SDI MSB (CMD) LSB (CMD) MSB (DATA) LSB (DATA)

Transmission Format (Read)

CSBI

SCKI

SDI MSB (CMD) LSB (CMD)

SDO MSB (DATA) LSB (DATA)

33001 F08

Figure 8

See Figure 9. Since CSBO, SCKO and SDOI voltages are

close to the V– of the high side device, the V– of the high LOW SIDE PORT
side device must be at least 5V higher than that of the low VSENSE + ON HIGHER DEVICE
(WRITE) –
side device to guarantee current flows of the current mode
interface. It is recommended that high voltage diodes be READ 1
placed in series with the SPI daisy-chain signals as shown
if Figure 13. These diodes prevent reverse voltage stress
on the IC if a battery group bus bar is removed. See Bat-
HIGH SIDE PORT
tery Interconnection Integrity for additional information. WRITE ON LOWER DEVICE

Standby current consumed in the current mode serial

interface is minimized when CSBI is logic high. VSENSE
(READ)
+
–
The voltage mode pin (VMODE) determines whether the low
side serial port is configured as voltage mode or current 33001 F09

mode. For the bottom device in a daisy-chain stack, this Figure 9. Current Mode Interface

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26 For more information www.linear.com/LTC3300-1

 LTC3300-1
OPERATION
pin must be pulled high (tied to VREG). The other devices Table 2. Command Byte Bit Mapping
in the daisy chain must have this pin pulled low (tied to V–) (Defaults to 0x00 in Reset State)
to designate current mode communication. To designate 1 0 1 0 1 CMDA CMDB Parity Bit
(MSB) (LSB)
the top-of-stack device, the TOS pin on the top device of
a daisy chain must be tied high. The other devices in the Table 3. Command Bits
stack must have TOS tied low. See the application on the CMDA CMDB Communication Action
last page of this data sheet. 0 0 Write Balance Command (without Executing)
0 1 Readback Balance Command
Command Byte 1 0 Read Balance Status
1 1 Execute Balance Command
All communication to the LTC3300-1 takes place with CSBI
logic low. The first 8 clocked in data bits after a high-to- Write Balance Command
low transition on CSBI represent the command byte and If the command bits program Write Balance Command,
are level-shifted through all LTC3300-1 ICs in the stack all subsequent write data must be mod 16 bits (before
so as to be simultaneously read by all LTC3300-1 ICs in CSBI transitions high) or it will be ignored. The internal
the stack. The 8-bit command byte is written MSB first command holding register will be cleared which can be
per Table 2. The first 5 bits must match a fixed internal verified on readback. The current balance command being
address [10101] which is common to all LTC3300-1’s in executed (from the last previously successful write) will
the stack, or all subsequent data will be ignored until CSBI continue, but all active balancing will be turned off if an
transitions high and then low again. The 6th and 7th bits Execute Balance Command is subsequently written. Each
program one of four commands as shown in Table 3. The LTC3300-1 in the stack expects 16 bits of write data writ-
8th bit in the command byte must be set such that the ten MSB first per Table 4. Successive 16-bit write data is
entire 8-bit command byte has even parity. If the parity is shifted in starting with the highest LTC3300-1 in the stack
incorrect, the current balance command being executed and proceeding down the stack. In this manner, the first
(from the last previously successful write) is terminated 16 bits will be the write data for the topmost LTC3300-1 in
immediately and all subsequent (write) data is ignored until the stack and will have shifted through all other LTC3300-1
CSBI transitions high and then low again. Incorrect parity ICs in the stack. The last 16 bits will be the write data for
takes this action whether or not the address matches. This the bottom-most LTC3300-1 in the stack.
thereby provides a fast means to immediately terminate
balancing-in-progress by intentionally writing a command
byte with incorrect parity.

Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)
D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B CRC[3] CRC[2] CRC[1] CRC[0]
(MSB) (LSB)

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LTC3300-1
OPERATION
The first 12 bits of the 16-bit balance command are used The last 4 bits of the 16-bit balance command are used
to indicate which balancer (or balancers) is active and in for packet error checking (PEC). The 16 bits of write data
which direction (charge or discharge). Each of the 6 cell (12-bit message plus 4-bit CRC) are input to a cyclic re-
balancers is controlled by 2 bits of this data per Table 5. dundancy check (CRC) block employing the International
The balancing algorithm for a given cell is: Telecommunication Union CRC-4 standard characteristic
polynomial:
Charge Cell n: Ramp up to IPEAK in secondary winding,
ramp down to IZERO in primary winding. Repeat. x4 + x + 1
Discharge Cell n (Synchronous): Ramp up to Ipeak in In the write data, the 4-bit CRC appended to the message
primary winding, ramp down to IZERO in secondary must be selected such that the remainder of the CRC divi-
winding. Repeat. sion is zero. Note that the CRC bits in the Write Balance
Command are inverted. This was done so that an “all zeros”
Table 5. Cell Balancer Control Bits
command is invalid. The LTC3300-1 will ignore the write
Dn A Dn B Balancing Action (n = 1 to 6)
data if the remainder is not zero and the internal command
0 0 None holding register will be cleared which can be verified on
0 1 Discharge Cell n (Nonsynchronous) readback. The current balance command being executed
1 0 Discharge Cell n (Synchronous) (from the last previously successful write) will continue,
1 1 Charge Cell n but all active balancing will be turned off if an Execute Bal-
ance Command is subsequently written. For information
For nonsynchronous discharging of cell n, both the sec-
on how to calculate the CRC including an example, refer
ondary winding gate drive and (zero) current sense amp
to the Applications Information section.
are disabled. The secondary current will conduct either
through the body diode of the secondary switch (if pres- Readback Balance Command
ent) or through a substitute Schottky diode. The primary
will only turn on again after the secondary winding Volt- The bit mapping for Readback Balance Command is identi-
sec clamp times out. In a bidirectional application with a cal to that for Write Balance Command. If the command
secondary switch, it may be possible to achieve slightly bits program Readback Balance Command, successive
higher discharge efficiency by opting for nonsynchronous 16-bit previously written data (latched in 12-bit message
discharge mode (if the gate charge savings exceed the plus newly calculated 4-bit CRC) are shifted out in the
added diode drop losses) but the balancing current will be same order bitwise (MSB first) starting with the lowest
less predictable because the secondary winding Volt-sec LTC3300-1 in the stack and proceeding up the stack. Thus,
clamp must be set longer than the expected time for the the sequence of outcoming data during readback is:
current to hit zero in order to guarantee no current reversal. Command data (bottom chip), Command data (2nd chip
In the case where a Schottky diode replaces the secondary from bottom), …, Command data (top chip)
switch, it is possible to build a undirectional discharge-only
balancing application charging an isolated auxiliary cell This command allows for microprocessor verification of
as shown in Figure 19 in the Typical Applications section. written commands before executing. Note that the CRC
bits in the Readback Balance Command are also inverted.
In the CTRL = 1 application of Figure 7 employing a single This was done so that an “all zeros” readback is invalid.
transformer which can only balance one cell at a time, any
command requesting simultaneous balancing of more than
one cell will be ignored. All active balancing will be turned
off if an Execute Balance Command is subsequently written.

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 LTC3300-1
OPERATION
Read Balance Status read balance status are currently not used and will always
be logic zero. As an example, if balancers 1 and 4 are both
If the command bits program Read Balance Status, suc-
active with no voltage or temperature faults, the 12-bit
cessive 16-bit status data (12 bits of data plus associated
read balance status should be 100100111000.
4-bit CRC) are shifted out MSB first per Table 6. Similar
to a Readback Balance Command, the last 4 bits in each Execute Balance Command
16-bit balance status are used for error detection. The
first 12 bits of the status are input to a cyclic redundancy If the command bits program Execute Balance Command,
check (CRC) block employing the same characteristic the last successfully written and latched in balance com-
polynomial used for write commands. The LTC3300-1 mand will be executed immediately. All subsequent (write)
will calculate and append the appropriate 4-bit CRC to data will be ignored until CSBI transitions high and then
the outgoing 12‑bit message which can then be used for low again.
microprocessor error checking. The sequence of outcom-
ing data during readback is: Pause/Resume Balancing (via SPI Port)

Status data (bottom chip), Status data (2nd chip from The LTC3300-1 provides a simple means to interrupt bal-
bottom), …, Status data (top chip) ancing in progress (stack wide) and then restart without
having to rewrite the previous balance command to all
Note that the CRC bits in the Read Balance Status are LTC3300-1 ICs in the stack. To pause balancing, simply
inverted. This was done so that an “all zeros” readback write an 8-bit Execute Balance Command with the parity
is invalid. bit flipped: 10101110. To resume balancing, simply write
The first 6 bits of the read balance status indicate if there an Execute Balance Command with the correct parity:
is sufficient gate drive for each of the 6 balancers. These 10101111. This feature is useful if precision cell voltage
bits correspond to the right-most column in Table 1, but measurements want to be performed during balancing
can only be logic high for a given balancer following an with the stack “quiet.” Immediate pausing of balancing
execute command involving that same balancer. If a bal- in progress will occur for any 8-bit Command Byte with
ancer is not active, its Gate Drive OK bit will be logic low. incorrect parity.
The 7th, 8th, and 9th bits in the read balance status indicate The restart time is typically 2ms which is the same as the
that all 6 cells are not overvoltage, that the transformer delayed start time after a new or different balance command
secondary is not overvoltage, and that the LTC3300-1 die (tDLY_START). It is measured from the 8th rising SCKI edge
is not overtemperature, respectively. These 3 bits can only until the balancer turns on and is illustrated in G27 in the
be logic high following an execute command involving at Typical Performance Characteristics section.
least one balancer. The 10th, 11th, and 12th bits in the

Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)
Gate Gate Gate Gate Gate Gate Cells Sec Temp 0 0 0 CRC[3] CRC[2] CRC[1] CRC[0]
Drive 1 Drive 2 Drive 3 Drive 4 Drive 5 Drive 6 Not OV Not OV OK
OK OK OK OK OK OK
(MSB) (LSB)

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LTC3300-1
APPLICATIONS INFORMATION
External Sense Resistor Selection
LTC3300-1
The external current sense resistors for both primary G1P/GnP/G1S/GnS

and secondary windings set the peak balancing current 20µA R

I1P/InP/I1S/InS
according to the following formulas: C RSNS

50mV V–/Cn – 1/V–/V–

RSENSE|PRIMARY = n = 2 TO 6
IPEAK _PRI
33001 F10

Figure 10. Using an RC Network to Filter Current Sense Inputs to

50mV the LTC3300-1
RSENSE|SECONDARY =
IPEAK _ SEC
LTC3300-1 compared to the true sense resistor voltage.
Balancer Synchronization This error can be compensated for by selecting the R value
to add back this same drop using the typical current value
Due to the stacked configuration of the individual synchro- of 20µA out of the LTC3300-1 current sense pins at the
nous flyback power circuits and the interleaved nature of comparator trip point.
the gate drivers, it is possible at higher balance currents
for adjacent and/or penadjacent balancers within a group Setting Appropriate Max On-Times
of six to sync up. The synchronization will typically be to
The primary and secondary winding volt-second clamps
the highest frequency of any active individual balancer and
are intended to be used as a current runaway protection
can result in a slightly lower balance current in the other
feature and not as a substitute means of current control
affected balancer(s). This error will typically be very small
replacing the sense resistors. In order to not interfere with
provided that the individual cells are not significantly out
normal IPEAK/IZERO operation, the maximum on times must
of balance voltage-wise and due to the matched IPEAK/
be set longer than the time required to ramp to IPEAK (or
IZERO’s and matched power circuits. Balancer synchro- IZERO) for the minimum cell voltage seen in the application:
nization can be reduced by lowpass filtering the primary
and/or secondary current sense signals with a simple RC tON(MAX)|PRIMARY > LPRI • IPEAK_PRI/VCELL(MIN)
network as shown in Figure 10. A good starting point for tON(MAX)|SECONDARY > LPRI • IPEAK_SEC • T/(S • VCELL(MIN))
the RC time constant is one-tenth of the on-time of the
These can be further increased by 20% to account for
associated switch (primary or secondary). In the case
manufacturing tolerance in the transformer winding
of IPEAK sensing, phase lag associated with the lowpass
inductance and by 10% to account for IPEAK variation.
filter will result in a slightly lower voltage seen by the

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 LTC3300-1
APPLICATIONS INFORMATION
External FET Selection stack is desired for more efficient balancing, a transformer
In addition to being rated to handle the peak balancing with a higher turns ratio can be selected. For example, a
current, external NMOS transistors for both primary and 1:10 transformer would be optimized for up to 60 cells in
secondary windings must be rated with a drain-to-source the secondary stack. In this case the external FETs would
breakdown such that for the primary MOSFET: need to be rated for a higher voltage (see above). In all
cases the saturation current of the transformer must be
VSTACK + VDIODE selected to be higher than the peak currents seen in the
VDS(BREAKDOWN)|MIN > VCELL +
T application.
⎛ S⎞ V See Table 8 for a list of transformers that are recommended
= VCELL ⎜ 1+ ⎟ + DIODE
⎝ T⎠ T for use with the LTC3300-1.
and for the secondary MOSFET: Table 8
VDS(BREAKDOWN)|MIN > VSTACK + T ( VCELL + VDIODE ) PART NUMBER MANUFACTURER
TURNS PRIMARY
RATIO* INDUCTANCE ISAT
= VCELL ( S+ T ) + T VDIODE 750312504 (SMT) Würth Electronics 1:1 3.5µH 10A
750312677 (THT) Würth Electronics 1:1 3.5µH 10A
where S is the number of cells in the secondary winding MA5421-AL Coilcraft 1:1 3.4µH 10A
stack and 1:T is the transformer turns ratio from primary
CTX02-18892-R Coiltronics 1:1 3.4µH 10A
to secondary. For example, if there are 12 Li-Ion cells in
XF0036-EP13S XFMRS Inc 1:1 3µH 10A
the secondary stack and using a turns ratio of 1:2, the
LOO-321 BH Electronics 1:1 3.4µH 10A
primary FETs would have to be rated for greater than 4.2V
DHCP-X79-1001 TOKO 1:1 3.4µH 10A
(1 + 6) + 0.5 = 29.9V and the secondary FETs would have
C128057LF GCI 1:1 3.4µH 10A
to be rated for greater than 4.2V (12 + 2) + 2V = 60.8V.
T10857-1 Inter Tech 1:1 3.4µH 10A
Good design practice recommends increasing this voltage *All transformers listed in the table are 8-pin components and can be
rating by at least 20% to account for higher voltages present configured with turns ratios of 1:1, 1:2, 2:1, or 2:2.
due to leakage inductance ringing. See Table 7 for a list of
Snubber Design
FETs that are recommended for use with the LTC3300-1.
Careful attention must be paid to any transient ringing
Table 7
seen at the drain voltages of the primary and secondary
PART NUMBER MANUFACTURER IDS(MAX) VDS(MAX)
winding FETs in application. The peak of the ringing should
SiR882DP Vishay 60A 100V
not approach and must not exceed the breakdown voltage
SiS892DN Vishay 25A 100V
rating of the FETs chosen. Minimizing leakage inductance
IPD70N10S3-12 Infineon 70A 100V present in the application and utilizing good board layout
IPB35N10S3L-26 Infineon 35A 100V techniques can help mitigate the amount of ringing. In
RJK1051DPB Renesas 60A 100V some applications, it may be necessary to place a series
RJK1054DPB Renesas 92A 100V resistor + capacitor snubber network in parallel with each
winding of the transformer. This network will typically
Transformer Selection
lower efficiency by a few percent, but will keep the FETs
The LTC3300-1 is optimized to work with simple 2-wind- in a safer operating region. Determining values for R and
ing transformers with a primary winding inductance of C usually requires some trial-and-error optimization in the
between 1 and 20 microhenries, a 1:2 turns ratio (primary application. For the transformers shown in Table 8, good
to secondary), and the secondary winding paralleling up starting point values for the snubber network are 330Ω
to 12 cells. If a larger number of cells in the secondary in series with 100pF.

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LTC3300-1
APPLICATIONS INFORMATION
Boosted Gate Drive Component Selection cell voltage from increasing past 6V. Therefore, the mini-
(BOOST = VREG) mum differential bypass capacitor value for full broken
connection protection is:
The external boost capacitor connected from BOOST+ to
BOOST– supplies the gate drive voltage required for turning
CBYPASS(MIN) =
(ICHARGE +IDISCHARGE ) • 6µs
on the external NMOS connected to G6P. This capacitor 6V – 5V
is charged through the external Schottky diode from C6
to BOOST+ when the NMOS is off (G6P = BOOST– = C5). If ICHARGE and IDISCHARGE are set nominally equal, then
When the NMOS is to be turned on, the BOOST– driver approximately 12µF of real capacitance per amp of balance
switches the lower plate of the capacitor from C5 to C6, current is required.
and the BOOST+ voltage common modes up to one cell
Protection from a broken connection to a cluster of sec-
voltage higher than C6. When the NMOS turns off again,
ondary windings is provided local to each LTC3300-1 in
the BOOST– driver switches the lower plate of the capaci-
the stack by the secondary winding OVP function (via
tor back to C5 so that the boost capacitor is refreshed.
WDT pin) described in the Operation section. However,
A good rule of thumb is to make the value of the boost because of the interleaving of the transformer windings
capacitor 100 times that of the input capacitance of the up the stack, it is possible for a remote LTC3300-1 to still
NMOS at G6P. For most applications, a 0.1µF/10V capacitor act on the cell voltage seen locally by another LTC3300-1
will suffice.The reverse breakdown of the Schottky diode at the point of the break which has shut itself off. For this
must only be greater than 6V. To prevent an excessive and reason, each cluster of secondary windings must have
potentially damaging surge current from flowing in the a dedicated connection to the stack separate from the
boosted gate drive components during initial connection of individual cell connection that it connects to.
the battery voltages to the LTC3300-1, it is recommended
to place a 6.8Ω resistor in series with the Schottky diode Using the LTC3300-1 with Fewer Than 6 Cells
as shown in Figure 3. The surge current must be limited To balance a series stack of N cells, the required number
to 1A to avoid potential damage. of LTC3300-1 ICs is N/6 rounded up to the nearest integer.
Additionally, each LTC3300-1 in the stack must interface
Sizing the Cell Bypass Caps for Broken Connection
to a minimum of 3 cells (must include C4, C5, and C6).
Protection
Thus, any stack of 3 or more cells can be balanced us-
If a single connection to the battery stack is lost while bal- ing an appropriate stack of LTC3300-1 ICs. Unused cell
ancing, the differential cell voltages seen by the LTC3300-1 inputs (C1, C1 + C2, or C1 + C2 + C3) in a given LTC3300
power circuit on each side of the break can increase or -1 sub-stack should be shorted to V– (see Figure 11).
decrease depending on whether charging or discharging However, in all configurations, the write data remains at
and where the actual break occurred. The worst-case 16 bits. The LTC3300-1 will not act on the cell balancing
scenario is when the balancers on each side of the break bits for the unused cell(s) but these bits are still included
are both active and balancing in opposite directions. In in the CRC calculation.
this scenario, the differential cell voltage will increase
rapidly on one side of the break and decrease rapidly Supplementary Voltage Regulator Drive (>40mA)
on the other. The cell overvoltage comparators working The 4.8V linear voltage regulator internal to the LTC3300-1
in conjunction with appropriately-sized differential cell is capable of providing 40mA at the VREG pin. If additional
bypass capacitors protect the LTC3300-1 and its associated current capability is required, the VREG pin can be back-
power components by shutting off all balancing before driven by an external low cost 5V buck DC/DC regulator
any local differential cell voltage reaches its absolute powered from C6 as shown in Figure 12. The internal
maximum rating. The comparator threshold (rising) is 5V, regulator of the LTC3300-1 has very limited sink current
and it takes 3µs to 6μs for the balancing to stop, during capability and will not fight the higher forced voltage.
which the bypass capacitor must prevent the differential 33001fb

32 For more information www.linear.com/LTC3300-1

 LTC3300-1
APPLICATIONS INFORMATION
• • •
• • •
• • •

+ + +
C6 CELL n + 4 C6 CELL n + 3 C6 CELL n + 2
C5 C5 C5
+ + +
CELL n + 3 CELL n + 2 CELL n + 1
C4 C4 C4
LTC3300-1 + LTC3300-1 + LTC3300-1 +
CELL n + 2 CELL n + 1 CELL n
C3 C3 C3
+ +
CELL n + 1 CELL n
C2 C2 C2
+
CELL n
C1 C1 C1
V– V– V–

• • •
• • •
• • • 33001 F11

(11a) Sub-Stack Using Only 5 Cells (11b) Sub-Stack Using Only 4 Cells (11c) Sub-Stack Using Only 3 Cells

Figure 11. Battery Stack Connections For 5, 4 or 3 Cells

C6

LTC3300-1

IOUT > 40mA

4.8V
VIN L 5V VREG LINEAR
SW
VOLTAGE
BUCK RFB2 REGULATOR
CIN DC/DC
FB COUT V–
GND
RFB1 33001 F12

Figure 12. Adding External Buck DC/DC for >40mA VREG Drive

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LTC3300-1
APPLICATIONS INFORMATION
Fault Protection battery system during its useful lifespan. Table 9 shows
the various situations that should be considered when
Care should always be taken when using high energy
planning protection circuitry. The first four scenarios
sources such as batteries. There are numerous ways
are to be anticipated during production and appropriate
that systems can be misconfigured when considering
protection is included within the LTC3300-1 device itself.
the assembly and service procedures that might affect a

Table 9. LTC3300-1 Failure Mechanism Effect Analysis

SCENARIO EFFECT DESIGN MITIGATION
Top cell (C6) input connection loss to LTC3300-1. Power will come from highest connected cell Clamp diodes at each pin to C6 and V– (within IC)
input or via data port fault current. provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Bottom cell (V–) input connection loss to Power will come from lowest connected cell Clamp diodes at each pin to C6 and V– (within IC)
LTC3300-1. input or via data port fault current. provide alternate power path. Diode conduction at
data ports will impair communication with higher
potential units.
Random cell (C1-C5) input connection loss to Power-up sequence at IC inputs/differential Clamp diodes at each pin to C6 and V– (within IC)
LTC3300-1. input voltage overstress. provide alternate power path. Zener diodes across
each cell voltage input pair (within IC) limit stress.
Disconnection of a harness between a sub-stack Loss of all supply connections to the IC. Clamp diodes at each pin to C6 and V– (within
of battery cells and the LTC3300-1 (in a system of IC) provide alternate power path if there are other
stacked groups). devices (which can supply power) connected to
the LTC3300-1. Diode conduction at data ports
will impair communication with higher potential
units.
Secondary winding connection loss to battery Secondary winding power FET could be WDT pin implements a secondary winding OVP
stack. subjected to a higher voltage as bypass circuit which will detect overvoltage and terminate
capacitor charges up. balancing.
Shorted primary winding sense resistor. Primary winding peak current cannot be Maximum ON-time set by RTONP resistor will shut
detected to shut off primary switch. off primary switch if peak current detect doesn’t
occur.
Shorted secondary winding sense resistor. Secondary winding peak current cannot be Maximum ON-time set by RTONS resistor will
detected to shut off secondary switch. shut off secondary switch if peak current detect
doesn’t occur.
Data link disconnection between stacked LTC3300-1 Break of daisy-chain communication (no stress If the watchdog timer is enabled, all balancers
units. to ICs). Communication will be lost to devices above the fault will be turned off after 1.5
above the disconnection. The devices below the seconds. The individual WDT pins will go Hi-Z and
disconnection are still able to communicate and be pulled up by external resistors.
perform all functions.
Data error (noise margin induced or otherwise) Incoming checksum will not agree with the Since the CRC remainder will not be zero, the
occurs during a write command. incoming message when read in by any LTC3300-1 will not execute the write command,
individual LTC3300-1 in the stack. even if an execute command is given. All
balancers with nonzero remainders will be off.
Data error (noise margin induced or otherwise) Outgoing checksum (calculated by Since the CRC remainder (calculated by the
occurs during a read command. the LTC3300‑1) will not agree with the host) will not be zero, the data cannot be trusted.
outgoing message when read in by the host All balancers will remain in the state of the last
microprocessor. previously successful write.

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34 For more information www.linear.com/LTC3300-1

 LTC3300-1
APPLICATIONS INFORMATION
Battery Interconnection Integrity diodes labeled ZCLAMP are higher voltage devices with an
initial reverse breakdown of 25V snapping back to 22V.
The FMEA scenarios involving a break in the stack of battery
The forward voltage drop of all Zeners is 0.5V.
cells are potentially the most damaging. In the case where
the battery stack has a discontinuity between groupings The internal protection diodes shown in Figure 14 are
of cells balanced by LTC3300-1 ICs, any load will force a power devices which are intended to protect against
large reverse potential on the daisy-chain connection. This limited-power transient voltage excursions. Given that
situation might occur in a modular battery system during these voltages exceed the absolute maximum ratings of
initial installation or a service procedure. The daisy-chain the LTC3300-1, any sustained operation at these voltage
ports are protected from the reverse potential in this levels will damage the IC.
scenario by external series high voltage diodes required
in the upper port data connections as shown in Figure 13. Initial Battery Connection to LTC3300-1
During the charging phase of operation, this fault would In addition to the above-mentioned internal protection
lead to forward biasing of daisy-chain ESD clamps that diodes, there are additional lower voltage/lower current
would also lead to part damage. An alternative connection diodes across each of the six differential cell inputs (not
to carry current during this scenario will avoid this stress shown in Figure 14) which protect the LTC3300-1 during
from being applied (Figure 13). initial installation of the battery voltages in the application.
These diodes have a breakdown voltage of 5.3V with 20kΩ
Internal Protection Diodes of series resistance and keep the differential cell voltages
Each pin of the LTC3300-1 has protection diodes to help below their absolute maximum rating during power-up
prevent damage to the internal device structures caused when the cell terminal currents are zero to tens of mi-
croamps. This allows the six batteries to be connected in
by external application of voltages beyond the supply rails
any random sequence without fear of an unconnected cell
as shown in Figure 14. The diodes shown are conventional
input pin overvoltaging due to leakage currents acting on
silicon diodes with a forward breakdown voltage of 0.5V.
its high impedance input. Differential cell-to-cell bypass
The unlabeled Zener diode structures have a reverse-
capacitors used in the application must be of the same
breakdown characteristic which initially breaks down at
nominal value for full random sequence protection.
9V then snaps back to a 7V clamping potential. The Zener

+ LTC3300-1
(NEXT HIGHER IN STACK)
V–

SDO SDI SCKI CSBI

PROTECT OPTIONAL
AGAINST REDUNDANT RSO7J
BREAK CURRENT ×3
HERE PATH
SDOI SCKO CSBO

C6
+ LTC3300-1
(NEXT LOWER IN STACK)
33001 F13

Figure 13. Reverse-Voltage Protection for the Daisy Chain (One Link Connection Shown)

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LTC3300-1
APPLICATIONS INFORMATION
VREG
48

WDT
20
SDO
19
LTC3300-1
SDI
18
SCKI
17
CSBO CSBI
45 16
TOS
47
SCKO
44
VMODE
46
SDOI
43
BOOST
42

BOOST+ CTRL
40 15

RTONP
14

BOOST– RTONS
41 13

C6
39

G6P G6S
38 1
I6P I6S
37 2
C5
36

G5P G5S
35 3
I5P I5S
34 4
C4
33 ZCLAMP

G4P ZCLAMP G4S

32 5
I4P I4S
31 6
C3
30

G3P G3S
29 7
ZCLAMP
I3P I3S
28 8
C2 ZCLAMP
27

G2P G2S
26 9
I2P I2S
25 10
C1
24

G1P G1S
23 11
I1P I1S
22 12

4Ω

EXPOSED PAD V–
49 21 33001 F14

Figure 14. Internal Protection Diodes

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 LTC3300-1
APPLICATIONS INFORMATION
Analysis of Stack Terminal Currents in Shutdown the CSBI/SCKI/SDI pins. To the extent that the 16μA and
As given in the Electrical Characteristics table, the qui- 7.5μA currents match perfectly chip-to-chip in a long series
escent current of the LTC3300-1 when not balancing is stack, the resultant stack terminal currents in shutdown
16μA at the C6 pin and zero at the C1 through C5 pins. are as follows: 23.5μA out of the top of stack node, 7.5μA
All of this 16μA shows up at the V– pin of the LTC3300-1. out of the node 6 cells below top of stack, 7.5μA into the
In addition, the SPI port when not communicating (i.e., node 6 cells above bottom of stack, and 23.5μA into the
CSBI = 1) contributes an additional 2.5μA per high side bottom of stack node. All other intermediate node cur-
line (CSBO/SCKO/SDOI), or 7.5μA to the V– pin current rents are zero. This is shown graphically in Figure 15. For
of each LTC3300-1 in the stack which is not top of stack the specific case of a 12-cell stack, this reduces to only
(TOS = 0). This additional current does not add to the local 23.5µA out of the top of stack node and 23.5µA into the
C6 pin current but rather to the C6 pin current of the next bottom of stack node.
higher LTC3300-1 in the stack as it is passed in through

TOP OF STACK

+ 23.5µA
CELL N C6 LTC3300-1
C5
ALL C4
ZERO C3
C2 16µA
+ C1
CELL N – 6 V– TOS = 1
3
+
CELL N – 7 7.5µA C6 LTC3300-1
C5
ALL C4
ZERO C3
C2 16µA 7.5µA
+ C1
CELL N – 12 0µA V–
3

3
+ 0µA LTC3300-1
CELL 12 C6
C5
ALL C4
ZERO C3
C2
16µA 7.5µA
C1
+ V–
CELL 7
3
+ LTC3300-1
CELL 6 7.5µA C6
C5
ALL C4
ZERO C3
C2 16µA 7.5µA
C1
+ V –
CELL 1
BOTTOM OF STACK 33001 F15

23.5µA

Figure 15. Stack Terminal Currents in Shutdown

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LTC3300-1
APPLICATIONS INFORMATION
How to Calculate the CRC desired balance command calls for simultaneous charging
of Cell 1 and synchronous discharging of Cell 4. The 12-bit
One simple method of computing an n-bit CRC is to perform
message (MSB first) will be 110000010000. Appending
arithmetic modulo-2 division of the n+1 bit characteristic
4 zeros results in 1100000100000000 for the dividend.
polynomial into the m bit message appended with n ze-
ros (m+n bits). Arithmetic modulo-2 division resembles The long division is shown in Figure 16a with a resultant
normal long division absent borrows and carries. At each CRC of 1101. Note that the CRC bits in the write balance
intermediate step of the long division, if the leading bit command are inverted. Thus the correct 16-bit balance
of the dividend is a 1, a 1 is entered in the quotient and command is 1100000100000010. Figure 16b shows the
the dividend is exclusive-ORed bitwise with the divisor. If same long division procedure being used to check the
the leading bit of the dividend is a 0, a 0 is entered in the CRC of data (command or status) read back from the
quotient and the dividend is exclusive-ORed bitwise with LTC3300-1. In this scenario, the remainder after the long
n zeros. This process is repeated m times. At the end of division must be zero (0000) for the data to be valid. Note
the long division, the quotient is disregarded and the n- that the readback CRC bits must be inverted in the dividend
bit remainder is the CRC. This will be more clear in the before performing the division.
example to follow. An alternate method to calculate the CRC is shown in
For the CRC implementation in the LTC3300-1, n = 4 and Figure 17 in which the balance command bits are input to
m = 12. The characteristic polynomial employed is x4 + x a combinational logic circuit comprised solely of 2-input
+ 1, which is shorthand for 1x4 + 0x3 + 0x2 + 1x1 + 1x0, exclusive-OR gates. This “brute force” implementation is
resulting in 10011 for the divisor. The message is the first easily replicated in a few lines of C code.
12 bits of the balance command. Suppose for example the

READBACK = 1100000100000010
DIVIDEND = 1100000100001101
110101101011 110101101011
(a) 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 (b) 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1
10011 10011
10110 10110
10011 10011
01010 01010
00000 00000
10101 10101
10011 10011
01100 01100
00000 00000
11000 11000
10011 10011
10110 10110
10011 10011
01010 01010
00000 00000
10100 10101
10011 10011
01110 01101
00000 00000
11100 11010
10011 10011
11110 10011
10011 10011
REMAINDER = 1 1 0 1 = 4-BIT CRC REMAINDER = 0
33001 F16
0 0 1 0 = 4-BIT CRC INVERTED

Figure 16. (a) Long Division Example to Calculate CRC for

Writes. (b) Long Division Example to Check CRC for Reads

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 LTC3300-1
APPLICATIONS INFORMATION
“Ø”
“Ø”
D6B

D5B

CRC [3]
D3B
D1B
CRC [3]
D2A

D5A

CRC [2]
D3A
D1A CRC [2]

D4B

CRC [1]
D2B

CRC [1]
D4A

D6A

“Ø”

“Ø” CRC [0]

CRC [0]
33001 F17

Figure 17. Combinational Logic Circuit Implementation of The CRC Calculator

Serial Communication Using the LTC6803 and LTC6804 The Typical Application shown on the back page of this
data sheet shows the serial communication connections for
The LTC3300-1 is compatible with and convenient to
a joint LTC3300-1/LTC6804-1 BMS. Each stacked 12-cell
use with all LTC monitor chips, such as the LTC6803 and
module contains two LTC3300-1 ICs and a single LTC6804‑1
LTC6804. Figure 20 in the Typical Applications section
monitor IC. The upper LTC3300-1 in each module is con-
shows the serial communications connections for a joint
figured with VMODE = 0, TOS = 1, and receives its serial
LTC3300-1/LTC6803-1 BMS using a common micropro-
communication from the lower LTC3300-1 in the same
cessor SPI port. The SCKI, SDI, and SDO lines of the
module, which itself is configured with VMODE = 1, TOS
lowermost LTC3300-1 and LTC6803-1 are tied together. The
= 0. The LTC6804-1 in the same module is configured to
CSBI lines, however, must be separated to prevent talking
provide an effective SPI port output at its GPIO3, GPIO4,
to both ICs at the same time. This is easily accomplished
and GPIO5 pins which connect directly to the low side
by using one of the GPIO outputs from the LTC6803-1
communication pins (CSBI, SDI=SDO, SCKI) of the lower
to gate and invert the CSBI line to the LTC3300-1. In this
LTC3300-1. Communication to the lowermost LTC6804-1
setup, communicating to the LTC6803-1 is no different
and between monitor chips is done via the LTC6820 and
than without the LTC3300-1, as the GPIO1 output bit is
the isoSPI™ interface. In this application, unused battery
normally high. To talk to the LTC3300-1, written commands
cells can be shorted from the bottom of any module (i.e.,
must be “bookended” with a GPIO1 negation write to the
outside the module, not on the module board) as shown
LTC6803-1 prior to talking to the LTC3300-1 and with
without any decrease in monitor accuracy.
a GPIO1 assertion write after talking to the LTC3300-1.
Communication “up the stack” passes between LTC3300-1
ICs and between LTC6803-1 ICs as shown.
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LTC3300-1
APPLICATIONS INFORMATION
PCB Layout Considerations 2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to
The LTC3300-1 is capable of operation with as much as exposed pad) should be bypassed with a 1µF or larger
40V between BOOST+ and V–. Care should be taken on capacitor as close to the LTC3300-1 as possible. This
the PCB layout to maintain physical separation of traces is in addition to bulk capacitance present in the power
at different potentials. The pinout of the LTC3300-1 was stages.
chosen to facilitate this physical separation. There is no 3. Pin 21 (V–) is the ground sense for current sense resis-
more than 8.4V between any two adjacent pins with the tors connected to I1S-I6S and I1P (seven resistors).
exception of two instances (VMODE to CSBO, BOOST to Pin 21 should be Kelvined as well as possible with low
SDOI/BOOST–). In both instances, one of the pins (VMODE, impedance traces to the ground side of these resistors
BOOST) is pin-strapped in the application to V– or VREG before connecting to the LTC3300-1 exposed pad.
and does not need to route far from the LTC3300-1. The
4. Cell inputs C1 to C5 are the ground sense for current
package body is used to separate the highest voltage
sense resistors connected to I2P-I6P (five resistors).
(e.g., 25.2V) from the lowest voltage (0V). As an example,
These pins should be Kelvined as well as possible
Figure 18 shows the DC voltage on each pin with respect
with low impedance traces to the ground side of these
to V– when six 4.2V battery cells are connected to the
resistors.
LTC3300-1.
5. The ground side of the maximum on-time setting resis-
tors connected to the RTONS and RTONP pins should
BOOST+ 25.2V TO 29.4V

be Kelvined to Pin 21 (V–) before connecting to the

BOOST– 21V TO 25.2V

G6P 21V TO 29.4V

LTC3300-1 exposed pad.

TOS 0V/4.8V
VMODE 0V/4.8V

BOOST 0V/4.8V
CSBO 24.5V
SCKO 24.5V
SDOI 24.5V

C6 25.2V
VREG 4.8V

I6P 21V

6. Trace lengths from the LTC3300-1 gate drive outputs

(G1S-G6S and G1P-G6P) and current sense inputs
0V TO 4.8V
0V
G6S—PIN 1
I6S
C5
G5P
21V
16.8V TO 25.2V
(I1S-I6S and I1P-I6P) should be as short as possible.
0V TO 4.8V G5S I5P 16.8V
0V I5S C4 16.8V
7. The boosted gate drive components (diode and ca-
0V TO 4.8V G4S G4P 12.6V TO 21V pacitor), if used, should form a tight loop close to the
LTC3300-1 C6, BOOST+, and BOOST– pins.
0V I4S LTC3300-1 I4P 12.6V
0V TO 4.8V G3S (EXPOSED PAD = 0V) C3 12.6V
0V I3S G3P 8.4V TO 16.8V
0V TO 4.8V G2S I3P 8.4V 8. For the external power components (transformer, FETs
0V
0V TO 4.8V
I2S
G1S
C2
G2P
8.4V
4.2V TO 12.6V
and current sense resistors), it is important to keep the
0V I1S I2P 4.2V area encircled by the two high speed current switching
RTONS
RTONP

loops (primary and secondary) as tight as possible.

CTRL
CSBI
SCKI

WDT
SDO

G1P
SDI

I1P
V–

C1

33001 F18
This is greatly aided by having two additional bypass
1.2V
1.2V
0V/4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V TO 4.8V
0V
0V
0V TO 8.4V
4.2V

capacitors local to the power circuit: one differential

cell to cell and one from the transformer secondary to
local V–.
Figure 18. Typical Pin Voltages for Six 4.2V Cells
A representative layout incorporating all of these recom-
Additional “good practice” layout considerations are as mendations is implemented on the DC2064A demo board
follows: for the LTC3300-1 (with further explanation in its accom-
panying demo board manual). PCB layout files (.GRB) are
1. The VREG pin should be bypassed to the exposed pad
also available from the factory.
and to V–, each with 1µF or larger capacitors as close
to the LTC3300-1 as possible.

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40 For more information www.linear.com/LTC3300-1

 LTC3300-1
TYPICAL APPLICATIONS
0.1µF 6.8Ω • • • • •
• • • • •
• • • • •
BOOST– BOOST+ 1:1
C6 •
+
CELL 6 10µH 10µH

10µF •

G6P

I6P
25mΩ
1:1
C5 •
+
CELL 5 10µH 10µH

10µF •

G5P

I5P
25mΩ
C4
• • •
C3 • • •
• • •
LTC3300-1 1:1
C2 •
+
CELL 2 10µH 10µH
CSBO
SCKO 10µF •
SDOI

SERIAL CSBI G2P

COMMUNICATION SCKI
RELATED SDI I2P
PINS SDO 25mΩ
1:1
TOS C1 •
VMODE +
WDT CELL 1 10µH 10µH ISOLATED
+ 12V LEAD ACID
10µF • AUXILIARY
CELL
G1P

I1P
25mΩ
G1S-G6S NC

VREG I1S-I6S
BOOST V–
CTRL RTONP RTONS ISOLATION
BOUNDARY 33001 F19

10µF 28k 41.2k

Figure 19. LTC3300-1 Unidirectional Discharge-Only Balancing Application to Charge an Isolated Auxiliary Cell

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For more information www.linear.com/LTC3300-1 41

LTC3300-1
TYPICAL APPLICATIONS
TOP OF BATTERY STACK

+
C6 CELL 24 C12
NC SDOI C5 C11 SDOI NC
NC SCKO C4 + C10 SCKO NC
CELL 23
NC CSBO C3 C9 CSBO NC
LTC3300-1 C2 + C8
CSBI C1 CELL 22 C7
SCKI VREG
+
SDI TOS CELL 21
NC SDO VMODE CVREG4
V– +
CELL 20

+ LTC6803-1
D9 D8 D7 CELL 19
C6
+
CELL 18
C6
SDOI C5 C5 GPIO2 NC
SCKO C4 + C4 GPIO1 NC
CELL 17
CSBO C3 C3
LTC3300-1 C2 + C2
CSBI C1 CELL 16 C1 CSPI
SCKI VREG VREG SCKI
+
SDI TOS CELL 15 TOS SDI
NC SDO VMODE CVREG3 CVREG6 VMODE SDO NC
V – + V–
CELL 14

D6 D5 D4
+ D12 D11 D10
CELL 13

+
C6 CELL 12 C12
SDOI C5 C11 SDOI
SCKO C4 + C10 SCKO
CELL 11
CSBO C3 C9 CSBO
LTC3300-1 C2 + C8
CSBI C1 CELL 10 C7
SCKI VREG
+
SDI TOS CELL 9
NC SDO VMODE CVREG2
V – +
CELL 8

D3 D2 D1
+ LTC6803-1
CELL 7
C6
+
CELL 6
C6
SDOI C5 C5 GPIO2 NC
DIGITAL SCKO C4 + C4 GPIO1
3V ISOLATOR CELL 5
CSBO C3 C3
V1+ V2+ VREG1 OR VREG5 LTC3300-1 C2 + C2
CSBI C1 CELL 4 C1 CSBI
CS
SCKI VREG VREG1 VREG5 VREG SCKI
MPU +
SDI TOS CELL 3 TOS SDI
CLK SDO VMODE CVREG1 CVREG5 VMODE SDO
V – + V–
CELL 2
MOSI

MOSO +
CELL 1
V1– V2–

33001 F20

Figure 20. LTC3300-1/LTC6803-1 Battery and Serial Communication Connections for a 24-Cell Stack

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42 For more information www.linear.com/LTC3300-1

 LTC3300-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)

0.70 ±0.05

5.15 ±0.05
5.50 REF
6.10 ±0.05 7.50 ±0.05
(4 SIDES)

5.15 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

7.00 ±0.10 0.75 ±0.05 R = 0.115

R = 0.10 TYP
(4 SIDES) TYP 47 48

0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35

5.15 ±0.10
5.50 REF
(4-SIDES)

5.15 ±0.10

(UK48) QFN 0406 REV C

0.200 REF
0.25 ±0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) BOTTOM VIEW—EXPOSED PAD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

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For more information www.linear.com/LTC3300-1 43

LTC3300-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1832 Rev B)
7.15 – 7.25
5.50 REF

48 37
1 36

0.50 BSC
C0.30

5.50 REF

7.15 – 7.25
0.20 – 0.30
3.60 ± 0.05
3.60 ± 0.05

12 PACKAGE OUTLINE 25
13 24

1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9.00 BSC
7.00 BSC 3.60 ± 0.10
48 37 37 48

SEE NOTE: 3
1 36 36 1

C0.30
9.00 BSC

7.00 BSC
3.60 ±0.10
A A

12 25 25 12

C0.30 – 0.50

13 24 24 13
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
1.60
11° – 13° 1.35 – 1.45 MAX
R0.08 – 0.20 GAUGE PLANE
0.25
0° – 7°

LXE48 LQFP 0410 REV B

11° – 13°
0.50
0.09 – 0.20 0.17 – 0.27 0.05 – 0.15
1.00 REF BSC
SIDE VIEW
0.45 – 0.75

SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH 4. DRAWING IS NOT TO SCALE
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
33001fb

44 For more information www.linear.com/LTC3300-1

 LTC3300-1
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 6/13 Added Tray ordering option for LXE package 3
Modified transformer part number in Table 8 31
B 12/13 Add new bullet Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors 1
Change part number XF0036-EP135 to XF0036-EP13S 31

33001fb

45
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of itsinformation www.linear.com/LTC3300-1
circuits as described herein will not infringe on existing patent rights.
LTC3300-1
TYPICAL APPLICATIONS
LTC3300-1/LTC6804-1 Serial Communication Connections

DATA

12-CELL
LTC3300-1 MODULE 2

ISO OUT
3
9 CELLS
LTC6804-1
LTC3300-1
SCKI GPIO5
SDI GPIO4 ISO IN
SDO
CSBI GPIO3

12-CELL
LTC3300-1 MODULE 1

ISO OUT
3 LTC6820
12 CELLS
LTC6804-1 isoSPI
LTC3300-1
SCKI GPIO5
SDI GPIO4 ISO IN 4
ISO SPI
SDO
CSBI GPIO3

33001 TA02

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC6801 Independent Multicell Battery Stack Monitor Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or
Overvoltage, Companion to LTC6802, LTC6803 and LTC6804
LTC6802-1/LTC6802-2 Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 1st Generation:
Superseded by the LTC6803 and LTC6804 for New Designs
LTC6803-1/LTC6803-3 Multicell Battery Stack Monitors Measures Up to 12 Series-Connected Battery Cells, 2nd Generation:
LTC6803-2/LTC6803-4 Functionally Enhanced and Pin Compatible to the LTC6802
LTC6804-1/LTC6804-2 Multicell Battery Monitors Measures Up to 12 Series-Connected Battery Cells, 3rd Generation:
Higher Precision Than LTC6803 and Built-In isoSPI Interface
LTC6820 isoSPI Isolated Communications Interface Provides an Isolated Interface for SPI Communication Up to 100m Using a
Twisted Pair, Companion to the LTC6804

33001fb

Linear Technology Corporation

46
LT 1213 REV B • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC3300-1
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3300-1  LINEAR TECHNOLOGY CORPORATION 2013