Chapter 7
Chapter 7
SLIDES FOR
CHAPTER 7
MULTI-LEVEL GATE CIRCUITS
NAND AND NOR GATES
This chapter in the book includes:
Objectives
Study Guide
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circuits Using NAND and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate Circuits
7.5 Circuit Conversion Using Alternative Gate Symbols
7.6 Design of Two-Level, Multiple-Output Circuits
7.7 Multiple-Output NAND and NOR Circuits
Problems
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Tree Diagrams
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Example
Find a circuit of AND and OR gates to realize
f (a, b, c, d) = Ʃ m(1, 5, 6, 10, 13, 14)
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Figure 7-3
©2010 Cengage Learning
This leads
directly to a
two-level
AND-OR gate
circuit.
Figure 7-4
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Factoring yields
f = c′d(a′ + b) + cd′(a + b)
Figure 7-5
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Figure 7-6
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Figure 7-7
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NAND gates
Figure 7-8(a) shows a three-input NAND gate. The small circle (or
“bubble”) at the gate output indicates inversion, so the NAND gate
is equivalent to an AND gate followed by an inverter, as shown in
Figure 7-8(b). The gate output is
F = (ABC)′ = A′ + B′ + C′
NOR gates
Figure 7-9(a) shows a three-input NOR gate. The small circle at the
gate output indicates inversion, so the NOR gate is equivalent to an
OR gate followed by an inverter. The gate output is
F = (A + B + C)′ = A′B′C′
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NAND Gates
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Figure 7-11a:
Eight Basic Forms for
Two-Level Circuits
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Figure 7-11b:
Eight Basic Forms for
Two-Level Circuits
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From this example, it is clear that the NAND-NOR form can realize
only a product of literals and not a sum of products.
Section 7.3 (p. 199)
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F = l1 + l2 + • • • + P 1 + P 2 + • • •
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Equivalent
gate symbols
based on
DeMorgan′s
Laws
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Figure 7-15:
NAND Gate Circuit
Conversion
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Figure 7-16:
Conversion to
NOR Gates
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Figure 7-17:
Conversion of AND-OR
Circuit to NAND Gates
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Realization of functions
separately (9 Gates)
Figure 7-19:
Realization of Equations
(7-22)
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Realization of functions
with shared gates (lower
overall cost) (7 Gates)
Figure 7-21
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Minimal Solution
In this example,
the best solution
is obtained by
not combining
the circled 1 with
adjacent 1’s.
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Figure 7-23
©2010 Cengage Learning
The procedure
for design of
single-output,
multi-level
NAND- and
NOR-gate
circuits also
applies to
multiple-output
circuits
Figure 7-24:
Multi-Level Circuit
Conversion to
NOR Gates
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