Nehru Arts and Science College

(Autonomous)
PG and Research Department of Electronics
VLSI Design and VHDL Programming
UNIT-I

MOS Transistor

A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several

layers of conducting and insulating materials to form a sandwich-like structure. These structures
are manufactured using a series of chemical processing steps involving oxidation of the silicon,
selective introduction of dopants, and deposition and etching of metal wires and contacts.
Transistors are built on nearly flawless single crystals of silicon, which are available as thin flat
circular wafers of 15–30 cm in diameter. CMOS technology provides two types of transistors
(also called devices): an n-type transistor (nMOS) and a p-type transistor (pMOS). Transistor
operation is controlled by electric fields so the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections and symbols
of these transistors are shown in Figure 1.a and b. The n+ and p+ regions indicate heavily doped
n- or p-type silicon.

Fig 1.a

Fig 1.b

Each transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2, better known as glass), and the silicon wafer, also called the substrate, body, or
bulk. Gates of early transistors were built from metal, so the stack was called metaloxide-
semiconductor, or MOS. Since the gate has been formed from polycrystalline silicon
polysilicon), but the name stuck. (Interestingly, metal gates reemerged in 2007 to solve materials
problems in advanced manufacturing processes.) An nMOS transistoris built with a p-type body
and has regions of n-type semiconductor adjacent to the gate called the source and drain. They
are physically equivalent and for now we will regard them as interchangeable. The body is
typically grounded. A pMOS transistor is just the opposite, consisting of p-type source and drain
regions with an n-type body. In a CMOS technology with both flavors of transistors, the
Substrate is either n-type or p-type. The other flavor of transistor must be built in a special well
in which dopant atoms have been added to form the body of the opposite type. The gate is a
control input: It affects the flow of electrical current between the source and drain. Consider an
nMOS transistor. The body is generally grounded so the p–n junctions of the source and drain to
body are reverse-biased. If the gate is also grounded, no current flows through the reverse-biased
junctions. Hence, we say the transistor is OFF. If the gate voltage is raised, it creates an electric
field that starts to attract free electrons to the underside of the Si–SiO2 interface. If the voltage is
raised enough, the electrons outnumber the holes and a thin region under the gate called the
channel is inverted to act as an n-type semiconductor. Hence, a conducting path of electron
carriers is formed from source to drain and current can flow. We say the transistor is ON. For a
pMOS transistor, the situation is again reversed. The body is held at a positive voltage. When the
gate is also at a positive voltage, the source and drain junctions are reverse-biased and no current
flows, so the transistor is OFF. When the gate voltage is lowered, positive charges are attracted
to the underside of the Si–SiO2 interface. A sufficiently low gate voltage inverts the channel and
a conducting path of positive carriers is formed from source to drain, so the transistor is ON.
Notice that the symbol for the pMOS transistor has a bubble on the gate, indicating that the
transistor behavior is the opposite of the nMOS.
MOS Switch
The positive voltage is usually called VDD or POWER and represents a logic 1 value in
digital circuits. In popular logic families of the 1970s and 1980s, VDD was set to 5 volts.
Smaller, more recent transistors are unable to withstand such high voltages and have used
supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and so forth. The low voltage is called
GROUND (GND) or VSS and represents a logic 0. It is normally 0 volts.
In summary, the gate of an MOS transistor controls the flow of current between the
source and drain. Simplifying this to the extreme allows the MOS transistors to be viewed as
simple ON/OFF switches. When the gate of an nMOS transistor is 1, the transistor is ON and
there is a conducting path from source to drain. When the gate is low, the nMOS transistor is
OFF and almost zero current flows from source to drain. A pMOS transistor is just the opposite,
being ON when the gate is low and OFF when the gate is high. This switch model is illustrated in
Figure 2., where g, s,and d indicate gate, source, and drain. This model will be our most common
one when discussing circuit behavior.

Fig 2

CMOS Logic

INVERTER Gates

Figure shows the schematic and symbol for a CMOS inverter or NOT gate using one
nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and the triangle at
the bottom indicates GND. When the input A is 0, the nMOS transistor is OFF and the pMOS
transistor is ON. Thus, the output Y is pulled up to 1 because it is connected to VDD but not to
GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y is pulled down to ‘0.’
This is summarized in Table 1.1.

The NAND Gate

Figure (a) shows a 2-input CMOS NAND gate. It consists of two series nMOS transistors
between Y and GND and two parallel pMOS transistors between Y and VDD. If either input A or
B is 0, at least one of the nMOS transistors will be OFF, breaking the path from Y to GND. But at
least one of the pMOS transistors will be ON, creating a path from Y to VDD. Hence, the output
Y will be 1. If both inputs are 1, both of the Nmos transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be 0. The truth table is given in Table 1.2 and the
symbol is shown in Figure (b). Note that by DeMorgan’s Law, the inversion bubble may be
placed on either side of the gate. In the figures in this book, two lines intersecting at a T-junction
are connected. Two lines crossing are connected if and only if a dot is shown.
k-input NAND gates are constructed using k series nMOS transistors and k parallel pMOS
transistors.
CMOS Logic Gates
The inverter and NAND gates are examples of static CMOS logic gates, also called
complementary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to
connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD), as

shown in Figure
The networks are arranged such that one is ON and the The pull-up and pull-down networks in
the inverter each consist of a single transistor. The NAND gate uses a series pull-down network
and a parallel pullup network. More elaborate networks are used for more complex gates. Two or
more transistors in series are ON only if all of the series transistors are ON. Two or more
transistors in parallel are ON if any of the parallel transistors are ON. This is illustrated in Figure
(a) for nMOS and pMOS transistor pairs. By using combinations of these constructions, CMOS
combinational gates can be constructed.

Fig (a)
Although such static CMOS gates are most widely used.In general, when we join a pull-up
network to a pull-down network to form a logic gate as shown in Figure (a), they both will
attempt to exert a logic level at the output. The possible levels at the output are shown in Table
1.3. From this table it can be seen that the output of a CMOS logic gate can be in four states. The
1 and 0 levels have been ncountered with the inverter and NAND gates, where either the pull-up
or pull-down is OFF and the other structure is ON. When both pull-up and pull-down are OFF,
the highimpedance or floating Z output state results. This is of importance in multiplexers,
memory elements, and tristate bus drivers. The crowbarred (or contention) X level exists when
both pull-up and pull-down are simultaneously turned ON. Contention between the two networks
results in an indeterminate output level and dissipates static power. It is usually an unwanted
condition.

The NOR Gate

A 2-input NOR gate is shown in Figure .The nMOS transistors are in parallel to pull the
output low when either input is high. The pMOS transistors are in series to pull the output high
when both inputs are low, as indicated in Table 1.4. The output is never crow barred or left
floating.

Compound Gates
A compound gate performing a more complex logic function in a single stage of logic is
formed by using a combination of series and parallel switch structures. For example, the
derivation of the circuit for the function Y = (A · B) + (C · D) is shown in Figure .

This function is sometimes called AND-OR-INVERT-22, or AOI22 because it performs

the NOR of a pair of 2-input ANDs. For the nMOS pull-down network, take the uninverted
expression ((A · B) + (C · D)) indicating when the output should be pulled to ‘0.’ The AND
expressions (A · B) and (C · D) may be implemented by series connections of switches, as shown
in Figure (a). Now ORing the result requires the parallel connection of these two structures,
which is shown in Figure (b). For the pMOS pull-up network, we must compute the
complementary expression using switches that turn on with inverted polarity. By DeMorgan’s
Law, this is equivalent to interchanging AND and OR operations. Hence, transistors that appear
in series in the pull-down network must appear in parallel in the pull-up network. Transistors that
appear in parallel in the pulldown network must appear in series in the pull-up network. This
principle is called conduction complements and has already been used in the design of the
NAND and NOR gates. In the pull-up network, the parallel combination of A and B is placed in
series with the parallel combination of C and D. This progression is evident in Figure (c) and
Figure (d). Putting the networks together yields the full schematic (Figure (e)).
Multiplexer
Multiplexers are key components in CMOS memory elements and data manipulation
structures. A multiplexer chooses the output from among several inputs based on a select signal.
A 2-input, or 2:1 multiplexer, chooses input D0 when the select is 0 and input D1 when the select
is 1. The truth table is given in Table 1.6; the logic function is Y = S · D0 + S · D1.

Two transmission gates can be tied together to form a compact 2-input multiplexer, as
shown in Figure (a). The select and its complement enable exactly one of the two transmission
gates at any given time. The complementary select S is often not drawn in the symbol, as shown
in Figure (b). Again, the transmission gates produce a non restoring multiplexer. We could build
a restoring, inverting multiplexer out of gates in several ways. One is the compound gate of

connected as shown in Figure (a).

Another is to gang together two tri state inverters, as shown in Figure (b). Notice that the
schematics of these two approaches are nearly identical, save that the pull-up network has been
slightly simplified and permuted in Figure (b). This is possible because the select and its
complement are mutually exclusive. The tristate approach is slightly more compact and faster
because it requires less internal wire. Again, if the complementary select is generated within the
cell, it is omitted from the symbol (Figure (c)). Larger multiplexers can be built from multiple 2-
input multiplexers or by directly ganging together several tri states. The latter approach requires
decoded enable signals for each tri state; the enables should switch simultaneously to prevent
contention. 4-input (4:1) multiplexers using each of these approaches are shown in Figure.

In practice, both inverting and non inverting multiplexers are simply called multiplexers or
muxes.

Wafer Processing
The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm
to 300 mm (12––a dinner plate!) in diameter and less than 1 mm thick. Wafers are cut from
boules, cylindrical ingots of single-crystal silicon, that have been pulled from a crucible of pure
molten silicon. This is known as the Czochralski method and is currently the most common
method for producing single-crystal material. Controlled amounts of impurities are added to the
melt to provide the crystal with the required electrical properties. A seed crystal is dipped into
the melt to initiate crystal growth. The silicon ingot takes on the same crystal orientation as the
seed. A graphite radiator heated by radio-frequency induction surrounds the quartz crucible and
maintains the temperature a few degrees above the melting point of silicon (1425 °C). The
atmosphere is typically helium or argon to prevent the silicon from oxidizing. The seed is
gradually withdrawn vertically from the melt while simultaneously being rotated, as shown in
Figure .
The molten silicon attaches itself to the seed and recrystallizes

Consider a simple fabrication process to illustrate the concept. The process begins with
the creation of an n-well on a bare p-type silicon wafer. Figure 1.36 shows cross-sections of the
wafer after each processing step involved in forming the n-well; Figure 1.36(a) illustrates the
bare substrate before processing. Forming the n-well requires adding enough Group V dopants
into the silicon substrate to change the substrate from p-type to n-type in the region of the well.
To define what regions receive n-wells, we grow a protective layeroxide over the entire wafer,
then remove it where we want the wells. We then add the ntype dopants; the dopants are blocked
by the oxide, but enter the substrate and form the wells where there is no oxide. The next
paragraph describes these steps in detail. The wafer is first oxidized in a high-temperature
(typically 900–1200 °C) furnace that causes Si and O2 to react and become SiO2 on the wafer
surface (Figure 1.36(b)). The oxide must be patterned to define the n-well. An organic
photoresist2 that softens where

exposed to light is spun onto the wafer (Figure (c)). The photoresist is exposed through the n-
well mask (Figure (b)) that allows light to pass through only where the well should be. The
softened photoresist is removed to expose the oxide (Figure (d)).The oxide is etched with
hydrofluoric acid (HF) where it is not protected by the photoresist (Figure (e)), then the
remaining photoresist is stripped away using a mixture of acids called piranha etch (Figure (f )).
The well is formed where the substrate is not covered with oxide. Two ways to add dopants are
diffusion and ion implantation. In the diffusion process, the wafer is placed in a furnace with a
gas containing the dopants. When heated, dopant atoms diffuse into the substrate. Notice how the
well is wider than the hole in the oxide on account of lateral diffusion (Figure (g)). With ion
implantation, dopant ions are accelerated through an electric field and blasted into the substrate.
In either method, the oxide layer prevents dopant atoms from entering the substrate where no
well is intended. Finally, the remaining oxide is stripped with HF to leave the bare wafer with
wells in the appropriate places.

Epitaxy,Deposition and Implantation

Epitaxy involves growing a single-crystal film on the silicon surface (which is already a
single crystal) by subjecting the silicon wafer surface to an elevated temperature and a source of
dopant material. Epitaxy can be used to produce a layer of silicon with fewer defects than the
nativewafer surface and also can help prevent latchup. Foundries may provide a choice of epi
(with epitaxial layer) or non-epi wafers. Microprocessor designers usually prefer to use epi
wafers for uniformity of device performance.
Deposition involves placing dopant material onto the silicon surface and then driving it
into the bulk using a thermal diffusion step. This can be used to build deep junctions. A step
called chemical vapor deposition (CVD) can be used for the deposition. As its name suggests,
CVD occurs when heated gases react in the vicinity of the wafer and produce a product that is
deposited on the silicon surface. CVD is also used to lay down thin films of material later in the
CMOS process. Ion implantation involves bombarding the silicon substrate with highly
energized donor or acceptor atoms. When these atoms impinge on the silicon surface, they travel
below the surface of the silicon, forming regions with varying doping concentrations. At elevated
temperature (>800 °C) diffusion occurs between silicon regions having different densities of
impurities, with impurities tending to diffuse from areas of high concentration to areas of low
concentration. Therefore, it is important to keep the remaining process steps at as low a
temperature as possible once the doped areas have been put into place.However, a high-
temperature annealing step is often performed after ion implantation to redistribute dopants more
uniformly. Ion implantation is the standard well and source/drain implant method used today.

CMOS Processing Technology

The following are main CMOS technologies:
n-well process
p-well process
twin-well process
Silicon-on-insulator

p-well process

In a p-well process, the nMOS transistors are built in a p-well and the pMOS transistor
isplaced in the n-type substrate. The p-well process is widely used, therefore the fabrication of p-
well process is very vital for CMOS devices. The fabrication steps of p-well process has been
developed keeping in view of fig. 5.5. Here, the basic processing steps are similar to NMOS.
Step-1 : the p-devices are formed on n-type substrate by proper masking and diffusion. Such
structure is comprised n-type substrate in which p-devices are integrated. Therefore, to
accommodate n-type devices, a deep p-well is diffused into the n0type substrate. The
formation of p-type well is depicted in fig. 5.5.
Step-2:Because the p-well doping concentration and depth affects the breakdown voltage and
threshold voltages of n-transistors, the diffusion must carried out with special
precautions. For obtaining low threshold voltages (typically 0.6 to 1.0V), one should
require either deep diffusion or high well resistivity. But the deep wells will require large
spacing between n-and p-types transistors, therefore a compromise is to be made.
Step-3 – The p-well so formed serves as substrate for n-type devices within the n-substrate. But
the areas are isolated from each other, except the voltage polarity. Similar to n-well, here
also two substrate connections i.e., VDD and VSS, are needed because, in effect, there will
be two substrates. The VDD and VSS requirement is depicted in fig.

In the other respects, i.e., masking, patterning and diffusion, the process is similar to NMOS
fabrication.
Summary of the p-well process is given as below –

 Mask 1 – defines the areas in which the deep p-well diffusions are to take place.
 Mask 2 – Defines the thin oxide regions, namely those areas where the thick oxide is to
be stripped and thin oxide grown to accommodate p-and n- transistors and diffusion
wires.

 Mask 3 – Used to pattern the poly silicon layer that is deposited after the thin oxide.
 Mask 4 – A p-plus mask is used (to be in effect ‘anded’ with Mask 2) to define all areas
where p-diffusion is to take place.
 Mask 5 – This is generally performed using the negative form to the p-plus mask and,
with mask2, defines those areas where n-type diffusion is to take place.
 Mask 6 – Contact cuts are defined.
 Mask 7 – the metal layer pattern is defined by this mask.
 Mask 8 – an overall passivation (over glass) layer is now applied and mask 8 is define the
openings for access to bonding pads.