Design of Communication ICs

台大電子所 李致毅教授
Professor Jri Lee
National Taiwan University
 關於這堂課…

三不
不點名, 不小考, 不交作業
成績計算
TBD
上課時間地點
Monday 234, 博理112
助教
吳克中/王懷德, 博理R424
參考書籍
“Design of Integrated Circuits for Optical communications”(30%)
“RF Microelectronics” (30%)
期刊論文/發明專利/吾所獨見而創獲者(40%)
 關於這堂課…

授課內容
Wireline: TIA, LA, MUX/DEMUX, Equalizer, CDR
Wireless: LNA, PA, Mixer, Frequency Synthesizer
General: Oscillator, Frequency Divider, PLL
授課方式
投影片+ 板書
專題演講 (3~4次)
Nasdaq Index over the Past Decade

dot com crash

 It is a Communication World

Among the 33 sessions of ISSCC 2007, more than

half of them are communication-related:
Wireline: 3~5 Analog: 1
Wireless/RF: 7-9 Technology Direction: 1
Baseband: 1 Data conversion: 2
One of the fields that updates itself most frequently.
Example: Bluetooth, WLAN.
Oscillators/PLLs speed up 10 times per decade.
Market/capital/technology oriented.
 Wireline Communication
Optical Backplane Cable/Wire
SONET/OC Chip-to-Chip Ethernet
PON Board-to-Board Twisted Pair

Exploring the (electronic) bandwidth limitation

=> use raw, un-modulated data (e.g., NRZ)
In this course, we primarily focus on the (analog)
front-end designs.
 Why Optical Fibers?

Modern optical communication fibers exhibit

a bandwidth of 25 to 50 GHz and a loss of
only 0.15 to 0.2 dB/km, presenting an
overwhelming advantage over other media.

Optical communications provide an ultimate

solution for carrying large volumes of data
across a long distance.
Comparison of Modern Communication Systems

Data Rate Loss (Range)

GSM 9.6 kb/s 500 m

WLAN(802.11a) 54 Mb/s 100 m

UWB 200 Mb/s 10 m

Twisted-Pair 12 Mb/s (ADSL) 200 dB/km

Coaxial 100 Mb/s 500 dB/km

Fiber (OC-192) 10 Gb/s 0.2 dB/km

Fiber provides ultimate bandwidth solution.

 Typical Optical Communication Systems

A transmitter, a receiver, and fiber channel are included.

Individual blocks pose difficult challenges.
 Basic Concepts of Random Binary Data

sin( πfTb ) 2
x (t ) = ∑ bk p(t − kTb ) Sx (f ) = Tb [ ]
k πfTb

The spectrum exhibits no power at frequency of

1/Tb and its harmonics, suggesting difficulties on
clock recovery.
Generation of Pseudo Random Binary Data

Length = 23 −1

m
A sequence of length 2 −1 contains at most
m-bit runs.
Longer sequence can be obtained by extending
the number of shift registers.
PRBS 215 − 1: y15 ⊕ y14 ⊕ 1 ,
PRBS 223 − 1: y23 ⊕ y18 ⊕ 1 .
 Spectrum of PRBS

Pseudo Random Data Sequence

= Combination of Periodic Pulses

The longer the random patterns, the closer the impulses.

Distinction between NRZ and RZ Data

RZ data occupies twice as much bandwidth.

Transimpedance Amplifiers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

General Considerations
Open-Loop TIAs
Feedback TIAs
High Performance TIAs
Case Study
 Jitter Due to Bandwidth Limitation

Insufficient bandwidth leads to deterministic jitter

−Tb T1 − T2 −τ −Tb
T1 = τ ln2 T2 = τ ln[2(1 − exp )] = ln(1 − exp )
τ Tb Tb τ
 ISI Due to Bandwidth Limitation

ΔV −Tb
ISI = = exp
V0 τ

Intersymbol Interference (ISI):

defining the vertical eye closure.
For a simple RC network with f−3dB = 0.7 Rb, data
jitter equals 0.28 % and ISI = 1.23 %.
Practical TIAs contain multiple poles/zeros, making
the analysis complex and requiring simulations.
 Noise Effect

∞ 1 − x2 VPP
Pc,tot = ∫ exp dx = Q ( )
V0 σ n
2π 2 2σ n
∞ 1 − u2 1 − x2
Q( x ) = ∫ exp du ≈ exp for x > 3
x
2π 2 x 2π 2
−12
For a BER of 10 , SNR needs to be around 14.
Noise issue becomes more severe for low
supply-voltage designs.
 Single-Register TIAs

RT(Transimpedance Gain) = RL
kT
In,in = 2
2

RL CD
1
Data Rate =
2πRLCD

Simplest way to convert current into voltage.

Direct trade off between speed and noise ⇒
seeking circuits that provide low input resistance
(high bandwidth) and high gain.
 Typical TIA Specs for OC-192 (10 Gb/s)

Gain > 1 kΩ

Bandwidth > 9 GHz

Sensitivity < -18 dBm

Maximum Input > 3 dBm

Peaking < 2 dB

Challenges:
High Gain High Bandwidth
Large Input Range Good PSRR
Low Noise Reasonable Power
 Open-Loop TIAs

Common Gate Common Base

RT = RD R T = RC
1 RD 1 RC
Rin ≈ + Rin ≈ +
gm + gmb (gm + gmb )ro gm gmro

Satisfying (input) impedance matching.

Comparable gain (consumes voltage headroom, too).
 High Frequency Response of Open-Loop TIAs
Common Gate Common Base

Vout (gm1 + gmb1 )RD Vout gm1RC

= =
Iin (gm1 + gmb1 + Cin s )(RDCout s + 1) Iin (gm1 + Cin s )(RDCout s + 1)

Input pole dominates (Cin ~ 250 fF).

Multiple tradeoffs make it difficult to achieve broad
band and high gain simultaneously.
Noise Performance of Common-Gate Stages
1
I 2
n,in = 4kT ( γgm2 + )
RD
= In,2 M2 + In,2 RD

4kT 8kTγ VDD

+ <
2
I n,R D In,2 M2 ID2

Noise Currents of M2 and RD are referred to the

input with unity gain and trade with each other.
Noise can’t be arbitrarily small ⇒ performance
limitation exists.
For more information about noise, check: “Design
of Analog CMOS Integrated Circuits”, Chap 7.
High Frequency Noise Analysis of CG Stages

1 1
I 2
n,in,tot = 4kTγ ( gm1ωp,out + gm2 ωp,in )
4 2
gm1 + gmb1
ωp,in =
Cin
1
ωp,out =
RDCout

Little flexibility can be achieved in CG/CB TIAs.

CG/CB architecture bears intrinsic limitation in
many aspects.
 Feedback TIAs

Consider a shunt-shunt feedback system:

RD Reasonable
RT =
1 + RD gmF Gain
Rin,open
Rin =
1 + RD gmF Impedance
Rout,open Matching
Rout =
1 + RD gmF

Many restrictions in CG/CB topology would be released.

 First-Order Feedback TIAs

ARF
RT = −
A + 1+ RFCD s
A
f−3dB =
2πRFCD
Ideal
Opamp

RF does not need to carry a bias current, relaxing

the voltage headroom limitation.
 Noise Performance of Feedback TIAs

Vn,RF + (RFCD s + 1)Vn,A

Vn,out =
1 + RFCD s A

4kT Vn,2A
In,2 in = + 2
RF RF

(when CD = 0)

Noise can be reduced by increasing RF .

Vn,RF approaches AVn,A as the frequency goes to
infinity ⇒ inaccurate opamp model (it should have
a finite bandwidth).
High Frequency Performance of Feedback TIAs

A0
A(s ) =
1 + s ω0

A0 ω0
CD
RT =
RFCD + 1 ω0 ( A0 + 1)ω0
s +
2
s+
RFCD ω0 RFCD

For maximum flatten response

1 2 A0
=
⇒ ζ = , −3dB 2πR C
f
2 F D

Bandwidth is greater than that of first order

TIA by 41%.
CMOS Realization of Feedback TIA

gm1RD
RT = RF
1 + gm1RD
RF
Rin =
1 + gm1RD
1 gm2
Rout =
1 + gm1RD
4kT 4kT γ 1 γ
In,2 in = + 2 ( + 2 + 2 2
)
RF RF gm1 gm1RD gm2 gm1RD

Generally inversely proportional to RF.

High-Frequency Behavior of Feedback TIA

TIA may oscillate due to the three poles around

the feedback loop.
CD and CL are nontrivial.
 Modified Feedback TIA

Split the feedback loop with output port.

Adding internal buffer.
 Power Supply Rejection Issue

Photodiode provides a single-ended current,

leading to a single-ended TIA design and
poor power supply rejection.

∂Vout 1
=
∂VDD 1 + gm1RD

Common issue for all single-ended circuits.

 Differential TIAs

‘‘Pseudo’’ Differential

Issues:
Unequal gain and phase shift at high frequencies.
Input noise current 2 times higher.
Generating only “pseudo” differential output.
Single-Ended to Differential Conversion

Average of Vx

Time constant of tens of microseconds

requires large external capacitor.
Data pattern dependent.
 High-Gain Techniques

Providing extra current without IR drop.

Noise inevitably becomes higher.
(Under what condition?)
 Capacitive Coupling

Relax the voltage-headroom requirement.

Some standards need very long runs,
leading to external large R and C.
Stability is of concern.
 Feedback TIA without Source Follower

Vout gmRF − 1
=− R D ≈ −RF
Vin gmRD + 1
RF + RD
Rin =
gmRD + 1
1
Rout = RD
gm

4kTγ 4kT 4kT

I 2
n,in = 2
+ 2 2 +
gmRF gmRF RD RF

Degenerate the source follower.

Tradeoffs between gain, stability, noise, and robustness.
 Inductive Peaking

Vout s + 2ζωn ωn
= −gmRD 2
1 Vin s + 2ζωn + ωn2 2π
f−3dB =
2πRDCL 1.79
f−3dB = for ζ = 1
2πRDCL 2
 Automatic Gain Control

Large input current may degrade the response be

pulling one or more current source into triode region.
Necessitating dynamic tracking mechanism to adjust
it in real time.
 Automatic Gain Control

Since
1 RFCD ω0
ζ=
2 A0 + 1
system may become unstable as RF goes down.
⇒ Need to reduce A0 so as to maintain a
relatively constant ζ.
 Case Study (I)

Korramabadi et. al. [ISSCC, 96]

 Case Study (II)

Wu et. al. [JSSC, 03]

 Case Study (III)

Park et. al. [JSSC, 04]

 Case Study (IV)

Chen et. al. [JSSC, 05]

Limiting Amplifiers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Introduction
Design Challenges
Loss of Signal Detection
Broadband Techniques
Case Study
 General Considerations

Requirement
High Gain (40~60dB)
Broad Bandwidth ( ≥ 0.7× Data Rate)
Low Noise (300 ~ 400 μVrms)
Small Offset Voltage
Well-Behaved Response to Large Signals
 Challenges of Noise

Example: OC-192 Receiver (Data Rate ≈ 10Gb/s)

For TIA output noise = 1 mVrms and LA contributes

10% of noise ⇒ LA input noise = 330 μVrms
For a bandwidth of 10 GHz ⇒ Vn,LA < 3 nV/ Hz
 Offset Due to Mismatches

Random asymmetries (e.g., device mismatches)

in LA result in finite offset.
Offset degrades sensitivity and causes pulse-
width distortion, necessitating cancellation
technique.
Offset may totally destroy the output in high-
gain systems (Why?).
 Offset Cancellation Technique

[Vos,in − Vos,outGmFR1 ]A = Vos,out

A
Vos,out = Vos,in
1 + AGmFR1
Vos,in
≈
GmFR1

Vout AGmR1(1 + sCF RF )

=
Vin 1 + AGmFR1 + sCF RF

Offset cancellation introduces one zero and one pole.

Lower corner defined by standards, usually very low.
 First Order Realization of Gain Stages

1
ω0 =
RoutCL

BWtot = ω 0 21/n − 1

Cascading identical amplifying stages.

Trade bandwidth with gain since the latter increases
in a way faster than the former decreases.
 Optimization of Stage Numbers
For a given technology, the gain-bandwidth
product is relatively constant.

GBW
⇒ BWtot = 1/n
21/n − 1
Atot
⇒ nopt = 2 lnAtot

For Atot = 50 dB, nopt = 11

However, noise and power issues limit the number
of stage to 5.
 Large Swing Effect

Small-signal gain-bandwidth analysis is pessimistic!

The last few stages switch with large input.

⇒ The speed of a cascade of stages is limited by
only that of one stage.
 AM/PM Conversion

I out = α 1Vin + α 3Vin3

3 3
Vout (t ) = A1(α 1Vm + α 3Vm3 )sin(ωt + θ1 ) − A3 α 3Vm3 sin(3ωt + θ 2 )
4 4

Noise on input signal amplitudes translates to

variations of output zero crossings, i.e., jitter.
Broadband Technique (I): Inductive Peaking

Vout s + 2ζω n ωn
1 = −gmRD 2
f−3dB = Vin s + 2ζω n s + ωn2 2ζ
2πRDCL
1.79
f−3dB = for ζ = 1/ 2
2πRDCL
Most Efficient method; no extra power consumption.
Area consuming (although has been moderated in
advanced technology).
Broadband Technique (II): Miller Capacitor Cancellation

CGD,eff = (1 + gmRD )CGD

C1,eff = (1 − gmRD )C1
gmRD + 1
⇒ C1 = CGD ≈ CGD
gmRD − 1

Mismatch or process variation matters.

Efficient only for high gain.
Button-plate parasitics degrade the performance.
Broadband Technique (III): Cherry-Hooper Amplifiers
gm2
ωp,X ≈
Vout g CX
= gm1RF − m1
Vin gm2 gm2
ωp,Y ≈
CY

Increase the bandwidth significantly in a cost of

minor gain loss.
Voltage headroom might be an issue in low
supply technologies.
Broadband Techniques (IV): Voltage-Current Feedback

Voltage-current (shunt-shunt) feedback can be

further applied to multiple stages.
Watch level shifting in BJT.

Double Triple
Broadband Techniques (V): f T Doubler

Vout = gm (Vin1 − Vin2 )RD

Double IR drop, voltage headroom issue.

Parasitics on tail current sources degrade the
performance.
Still quite useful in output buffer designs.
Broadband Technique (VI): Capacitive Degeneration

Vout gm (1 + R sC s s ) RD
=
Vin g R 1 + sCL RD
R sC s s + 1 + m s
2

If RSCS = RDCL, bandwidth increases by a factor of

(1+gmRS/2) whereas gain decreases by the same amount.
Broadband Technique (VII): Distributed Amplification

Z 0L l
Av = gm n ≈ πfT
2 v
Voltage gain is proportional to physical length l.
With ideal T-lines, distributed amplifiers would
achieve infinite gain with infinite bandwidth!
 Modified Distributed Amplifiers

Cascade and segmented structure helps to

improve the performance.
Realization of Monolithic Transmission Lines

mm-wave techniques become practical in deep-

submicron CMOS.
T-lines are lossy but still useful.
 Challenges of Distributed Amplifiers

Transmission Line Loss.

Output resistance of transistors.
Miller capacitance.
Propagation velocity mismatches.
Routing difficulties in differential
realization.
PVT variations.

⇒ Nevertheless, T-line based distributed amplifiers still

provide promising applications.
Case Study

[Galal et al., 2003]

 Equalizers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Introduction
Pre-Emphasis and Drivers
Post-Emphasis and Equalizers
Design of Building Blocks
Case Study

Reference: “Digital Communications” by John

Proakis (4th Edition).
High-Speed Data Transfer (Electrical)

[Courtesy, Srikanth Gondi]

Serial Link Architecture

[Courtesy, Srikanth Gondi]

Intersymbol Interference (ISI)

[Courtesy, Srikanth Gondi]

Universal Expression of Wire Loss

Coefficients ks and kd vary

significantly for different media.
For example, backplane traces
suffer from skin effect more
seriously.
Loss Mechanisms in Microstrips

[Courtesy, Srikanth Gondi]

Time-Domain Analysis of Pre-Emphasis

c
d
ISI occurs!

Insufficient bandwidth leads to ISI.

What happen if we force point d to zero?
 Time-Domain Analysis of Pre-Emphasis

Two-Tap FIR Filter

ISI gets reduced by boosting transition bits.

Time-Domain Analysis of Pre-Emphasis

1
1- α

Amplitude
100 % Eye
Opening

No Jitter
0
-α
0 0.5 1
Time (ns)

For any arbitrary τ, we choose α = exp(−Tb/τ)

Complete eye opening and zero transition jitter!
(Of course, it is too good to be true!!)
 Frequency Response of Two-Tap FIR

z (t ) = x (t ) − αx (t − Tb ) H (s ) = 1 − αe − sTb

[
Z (s ) = X (s ) 1 − αe − sTb ] H (s ) = 1 + α 2 − 2αcosωTb
 Multi-Tap FIR Filter with Zero-Forcing

Impulse response reveals what appears in the output.

Since the actual waveform is a linear combination of
all taps, properly selecting coefficients can eliminate
ISI.
 Zero-Forcing Technique
N
⎧1 for k = 0
Since yk = ∑
n=- N
an x k −n = ⎨
⎩0 elsewhere
, we have

⎡ x0 x -1 L x - N L x - 2 N -1 x - 2N ⎤ ⎡ a- N ⎤ ⎡0⎤
⎢ ⎥⎢ ⎥
⎢ x1 x0 L x - N +1 L x - 2 N x -2N +1 ⎥ ⎢a-N +1 ⎥ ⎢⎢0⎥⎥
⎢ M M ⎥⎢ M ⎥ ⎢ M ⎥
⎢ ⎥⎢ ⎥ ⎢ ⎥
⎢ xN x N -1 L x0 L x - N -1 x - N ⎥ ⎢ a0 ⎥ = ⎢ 1⎥
⎢ M M ⎥⎢ M ⎥ ⎢ M ⎥
⎢ ⎥⎢ ⎥ ⎢ ⎥
⎢ x 2 N -1 x 2N - 2 L x N -1 L x -2 x -1 ⎥ ⎢ aN -1 ⎥ ⎢0⎥
⎢x x 2 N -1 L L x 0 ⎥⎦ ⎢⎣ aN ⎥⎦ ⎢⎣0⎥⎦
⎣ 2N xN x -1

Zero ISI requires infinite length.

Zero forcing only occurs at sampling points (discrete
behavior), issues such as transition jitter are not
considered here.
Equalizer Filter Design

[Courtesy, Srikanth Gondi]

Second Order Structures

[Courtesy, Srikanth Gondi]

Equalizer Filter: Intuitive Approach

[Courtesy, Srikanth Gondi]

Parallel Path Approach

[Courtesy, Srikanth Gondi]

Review of Prior Art

[Courtesy, Srikanth Gondi]

RC Source Degeneration

[Courtesy, Srikanth Gondi]

Conventional Filter Stage
Filter Stage with Inductive Peaking
Problem of Adaptation

[Courtesy, Srikanth Gondi]

Rectifier & Integrator

[Courtesy, Srikanth Gondi]

 Case Study I

[Choi, 04]
Dual loop architecture to balance low- and
high-frequency parts.
Case Study II

[Gondi, 05]
Case Study II

[Gondi, 05]
 Oscillators (I)

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Barkhausen Criteria
Ring Oscillators
LC Oscillators
Colpitts Oscillator
Tuning Techniques
 BarkhausenCriteria

H (jω0 ) ≥ 1, ∠ H (jω0 ) = 180°

Poles locate at the y-axis.

Necessary but not sufficient.
Loop gains are typically chosen to be at least 2
or 3 to ensure oscillation. Oscillators adjust
themselves to satisfy the criteria.
 Evolution of Ring Oscillators

Barkhausen criteria is achievable only when the

number of stage is greater than 2.
 Three-Stage Ring Oscillator

A03
H (s ) =
(1 + s )3
ω0
A0 = gmRD , ω0 = 1
RDCL
⇒ tan-1(ωosc
ω0 ) = 60°
ωosc = 3ω 0
A0
⇒ =1
1+
ω 2
osc
ω20
A0 ≥ 2

Tuning can be included by adjusting RD or CL.

 Three-Stage Ring Oscillator
A03
(1 + s )3
Vout ω0
=
Vin A03
1+
(1 + s )3
ω0
Vout A03 s1 = (− A0 − 1)ω0
H (s ) = (s ) =
Vin (1 + s )3 ⎡ A0 (1 ± j 3 ) ⎤
ω0 s2,3 =⎢ − 1⎥ ω0
⎢⎣ 2 ⎥⎦

A0 − 2 A 3
Vout ∝ exp( ω0t ) cos( 0 ω 0t )
2 2
 Large Signal Analysis

A0 3ω0
≠ 6TD
2

In reality, the signal “saturates” to make the

average loop gain equal to unity.
The actual oscillation frequency is determined by
large signal behavior.
 Four-Stage Ring Oscillators

A04
H (s ) =
(1 + s ) 4
ω0
ωosc = ω0
A0 ≥ 2

The number of stages in a ring oscillator is determined

by speed, power and noise performance.
 CMOS Realizations without Resistors

Overcome voltage
headroom issue.

If poly resistors are available then use them.

 Quality Factor of Inductors

Definitions

ω0
(i) Q =
Δω
Energy Stored
(ii) Q = 2π
Energy Dissipated Per Cycle
ω0 dφ
(iii) Q = ⋅
2 dω

Three definitions are equivalent.

 Equivalent Circuit of an LC Tank

LS = LP

ωLS
RS = RP = Q ⋅ ωLP
Q

Q is a function of inductance and frequency.

Q is around 3-5 for large inductors (>5nH). Smaller
inductors typically achieve a higher Q.
 LC Oscillators

Barkhausen criteria can be easily satisfied.

Oscillation frequency = ω1. Minimum phase noise point.
 Another Approach to Oscillation

Cross-coupled differential pair can be recognized as

negative resistors.
 One Port Oscillators

Three possible realizations

As long as a negative equivalent resistance can be

found, an oscillator can be made.
 Colpitts Oscillator

Vout RpLp s (gm + C2 s )

=
Iin RpC1C2Lp s 3 + (C1 + C2 )Lp s 2 + [ gmLp + Rp (C1 + C2 )]s + gmRp

C1 C2 2
gmRp = (1 + ) ≥ 4 (@ C1 = C2 )
C2 C1
1
ωR = (if Cp included)
CC
Lp (Cp + 1 2 )
C1 + C2
Oscillates under proper conditions.
 Voltage-Controlled Oscillator

Tradeoffs:
Center Frequency Tuning Linearity
Tuning Range Output Amplitude
Power Dissipation Supply Rejection
Phase Noise
 Ring VCO – Output Swing Control

Replica biasing “servos” the on-resistance to vary

the frequency while maintaining the constant output
swing.
Ring VCO – Delay Variation by Positive Feedback

Current steering topology keeps the swing constant.

It may suffer from voltage headroom issue.
 Ring VCO – Current-Folding Topology

Folding the current saves one stacking stages.

Ring VCO – Delay Variation by Interpolation

Stability issue?
Large tuning range
Oscillation Frequency of Simple LC Oscillator

Rp = Q ⋅ ωosc L = 1
gm
1
ωosc =
Cp CGS
2L( + )
2 2
 Oscillation Frequency of LC Oscillator
If Cp is insignificant compared with CGS, then
1
ωosc ≈
LCGS
1
=
1
CGS
gmQωosc
= QωT ωosc

⇒ ωosc = Q ⋅ ωT

An LC oscillator could theoretically operate at

arbitrarily high frequency as long as the inductor
provides a sufficiently high Q.
In reality, neither Cp is negligible nor can an on-chip
inductor achieve very high Q, nor negligible Cp.
 Oscillators (II)

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outlines

General Considerations
Inductor Designs
Varactor Designs
Quadrature Oscillators
Distributed Oscillators
 Basic LC Oscillators

Cross-coupled pair provides negative resistance

to compensate inductor loss.

Advantages:
Large Swing Low Supply Voltage
Higher Frequency Lower Phase Noise
 Operation Theory

Barkhausen Criteria:

H ( jω) ≥ 1

∠H(jω) = 360°

Necessary but not sufficient conditions.

Require 2~3 times larger loop gain to ensure oscillation.
 Monolithic Inductors

Inductance calculation involves EM field equations.

Spiral turns achieve higher inductance by mutual
coupling between turns.
Optimum values of inductance, parasitics, and Q
require reiterative designs with software simulations.
 Inductor Loss Mechanisms

Ohm Loss
⇒ Arises from the series resistance of the metal wire:
comprising the spiral.
⇒ Modern VLSI technologies provide a sheet
resistance of 20 to 70 mΩ/ .

Skin Effect
⇒ Current tends to concentrate on the edge at high
frequencies, changing the magnetic flux and the
inductance.
⇒ Inductor Q decreases as well.
Losses due to Capacitive and Magnetic Coupling

Finite substrate resistance results in loss.

A high-resistance (i.e., lightly-doped) substrate
minimizes the loss in both cases.
 Inductor Design Techniques

Ground Shield

⇒ Isolate the substrate from capacitive coupling.

⇒ Eddy current is reduced as well since a large
portion of EM field lines terminates at ground
shield.
 Inductor Design Techniques

Differential Structures

⇒ Improve Q by reducing the substrate loss.

 Inductor Design Techniques

Stacked Structures:

⇒ Increase the self-resonance frequency by lowering

the equivalent capacitance.
 Monolithic Varactors (I)

MOS Varactor

CGS presents a monotonic variation with a dynamic

range of 2~3 times.
 Monolithic Varactors (II)

Reverse-Biased pn Junction

C0
C var =
VR
(1 + )m
φB
Approximately 2-2.5 times variation range.
 VCO with MOS Varactors

VCO with current source on top maximize the tuning

range. (Why?)
VCO with pn-Junction Varactors
 Quadrature Oscillators

Two identical oscillators coupled together to create

quadrature outputs.
Quadrature LC VCO Analysis

(−αY + X ) H (s ) = X
( −α X + Y ) H ( s ) = Y
⇒ X 2 +Y 2 = 0
⇒ X = ± jY , ∠H (s ) = ± tan-1α
 Quadrature LC VCO Analysis

Actually a series resistance RS must be incorporated

to model the Ohm loss at low frequencies.

System adjusts itself to have only one solution; the

other diminishes due to insufficient loop gain.
 Quadrature VCO Tuning

Varactor Tuning Bias-Current Tuning

Tuning can be achieved in different ways.

 Drawbacks of Quadrature VCO

May still be prone to frequency ambiguity under

mismatches.
Operating away from the resonance of the tank;
raising the phase noise.
May lose quadrature phase locking if the coupling
factor between oscillators becomes too small.

Nonetheless, it is still popular

and can be extended to semi-
quadrature operation.

Semi-quadratre is also possible.

 Distributed Oscillators

πfT
AV =
2fosc
πfT
fosc =
2

Difficult to achieve multiphase operation due to

unequal amplitudes.
 LC VCO Topologies

(Kim & Kim, ISSCC ’00) (Rogers & Long, ISSCC ’02)

Operates away from Resistors dissipate

tank resonance. energy in each cycle.
Requires knowledge of
tank Q and oscillator
mismatches to set the
coupling factor.
Case Study (I)

[Lee, ’03]
Case Study (I)
Case Study (II)

[Savoj, ’01]
Frequency Dividers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Introduction
Static Dividers
Miller Dividers
Injection Dividers
Prescalers
Case Study
Full-Rate Divider Applications
Full-Rate Divider Applications

Wireless Frontend

I/Q mismatch of great importance.

Very high speed.
 Static Dividers

Edge-triggered flipflop toggle between the two states

by “negative feedback”.
Wide range of operation (almost from DC to the
circuit’s bandwidth).
Overlapped clock may cause racing.
Rising/falling time of CKin matters.
 Implementation of Flipflops

Almost any type (digital or analog) can serve:

• Multiplexer-Based • TSPC
• Pseudostatic • CML (Current-Steering)
• C2MOS
 CML Latch

Speed limited by RC time constant.

Meta-Stability
 Regeneration of Meta-Stable Points

FF-based divider fails when it can not flip the state in

one (input) clock cycle.
 Superdynamic Flipflop

Allows different current for sampling and regeneration.

 Free-Running Frequency

At fCK1 the divider behaves as a ring oscillator (with the

cross-coupled pair providing sufficient phase shift),
and requires little input power.
Static and Dynamic Dividers
Conventional Dynamic Divider
Analysis of Dynamic (Miller) Divider

+ y = β yA cos ωint
dy
R1C1
dt
⎛ βA ⎞
sin ωint ⎟⎟
t
y (t ) = y (0) exp ⎜⎜ − +
⎝ R1C1 R1C1ωin ⎠

Decays to zero with a time constant of R1C1.

Divider doesn’t work without proper delay
along the loop.
 Analysis of Dynamic Divider

90° phase shift satisfies the division requirement.

Usually an emitter follower is needed to provide the
required phase shift.
Rough Estimation of Operation Range

3f0 f
The LPF must (1) filter out , (2) preserve 0 .
2 2
f0,max 3f0,min
≅ fc and ≅ fc
2 2
2fc
< f0 < 2fc
3
Dynamic Divider with Bandpass Load
Frequency Range for Correct Division
Intuitive Understanding of Bandpass Division

ωint + αcos 3ωint

y ∝ cos ⇒ 0 < α < 1/3.
2 2

Actually, ⇒ 0 < α < 1/(2√3 ).

Reference: “A 40-GHz Frequency Divider in 0.18-um CMOS

Technology”, JSSC, April 2004.
RF-Port and LO-Port Feedback
RF-Port Feedback
LO-Port Feedback
 Injection-Locked Divider

Injecting signal at twice the oscillation frequency.

f0 A inj 4
Locking range ≅ ⋅ ⋅
2Q A osc 3π
 Modified Injection-Locked Divider

1
2π ⋅ 2f0 =
LCP

Resonate out parasitic capacitance at node P to allow

stronger signal injection to the divider.
 Multi-Modulus Divider

Some applications require programmable division.

Example: Integer-N Frequency Synthesizer.

Channel Spacing = 1 MHz, Channel Number = 128

 Pulse-Swallow Divider

Prescaler divides the input frequency by N＋1 or N

based on the modulus control.
Program counter divides the prescaler output by P
(fixed).
Swallow counter divides the prescaler output by S
(programmable).
 Pulse-Swallow Divider

Start from reset, prescaler divides by N＋1 until

swallow counter is full.
After (N＋1)S pulses at the input, the modulus
control changes to N.
Continues to count until program counter is full.
⇒ Total pulses at the input = (N＋1)S＋N(P－S) =
NP＋S.
 Prescaler (Dual-Modulus Dividers)
÷3/2 Divider

When MC=0 ⇒ OR Gate transparent ⇒ ÷3

 Prescaler (Dual-Modulus Dividers)
÷3/2 Divider

When MC=1 ⇒ A=1, B=C ⇒ degenerates to ÷2 circuit

 Higher Modulus Prescaler
÷8/9 Divider

÷15/16 Divider
Case Study

[Lee, ‘07]
Mixers, Multiplexers, and Demultiplexers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Mixers
• Passive and Active
• Bipolar and CMOS
Muxes
• 2-to-1
• N-to-1
Demuxes
Case Study
 Performance Metrics of Mixers
NF 8-12 dB
IIP3 0-5 dBm
Rin 50 Ω
(Standalone)
Gain 10-15 dB
LO-RF Isolation
LO-IF Isolation

Voltage and Power Conversion Gains:

V IF P IF
AV = AP =
V RF P RF
AV and AP need not to be equal because the source
and load impedances are different.
 Passive Mixers

*LO signal with 50% duty cycle

V IF = V RF ⋅ S (t )

Voltage conversion gain = 1/π ≈ −6.4 dB

Tradeoff: sinusoidal LO (no higher-order harmonics) vs.
squarewave LO (abrupt transition)
 Active Mixers
Differential realization
2
V IF = gm1 ⋅V RF ⋅ RD ⋅
π
Voltage conversion
2
gain = gm1 ⋅ RD ⋅
π
Single-Ended Differential
LO signal couples to IF.
Gradual LO ⇒ RF
signal appears as
common-mode ⇒
reduce conversion gain.
1 2
Conv. gain = Conv. gain =
π π
Single-Balance and Double-Balance Mixers
Single-Balanced Double-Balanced

Single Double
Noise Lower Higher
LO-IF Feedthrough Higher Lower
Even-Order Distortion Higher Lower
Conversion Gain Lower Higher(2x)
 Bipolar Mixers

2
AV = gm1 ⋅ RC ⋅
π
Linearity
Power Consumption Incorporating single-ended/
differential conversion.
LO-IF Feedthrough
LO-RF Feedthrough
 Linearization Technique

Does n matters if constant Gm is of importance?

 CMOS Mixers

Most of the bipolar design concepts can be

applied to CMOS directly, ⇒ only LO
requirement differs.
Small LO signal ⇒ lower conversion gain,
higher noise, higher nonlinearity.
To make the switching sharp for a given LO
⇒ increase the width of the differential pair or
reduce the bias current ⇒ lower speed or
lower gain.
 2-to-1 Selector

Finite rising and falling edges ⇒ timing issues

Deterministic Jitter of MUX
 Deterministic Jitter of MUX

V0
τ [ ln(V0 − VS ) − ln ]
2
 Output Data Cleanup with Flipflop

Data skew and clock imbalance would cause

output distortion directly.
A full-rate FF can remedy this.
 Sampling Alignment Using Latches

Usually requires latches to provide 0.5 UI phase shift.

N-to-1 Multiplexer with Tree Structure

⇒ and also, clock distribution.

 Demultiplexer

Reverse operation of MUX.

Much more relaxed clock/data phase requirement.
Usually work with CDR.
 Case Study (I)

[Ishii, JSSC02]
Tree structure. InP technology.
Timing requirement relaxes as speed goes down.
 Case Study (II)

[Tanabe, JSSC’01]
Phase-Locked Loops

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Introduction
Simple PLLs
Charge-Pump PLLs
Nonidealities
Applications
Phase-Locked Loops and their Versatileness

Phase-locking technique provides an unique

ability in phase/frequency acquisition, creating
numerous important applications in electronics,
communication, and instrumentation.

Playing indispensable roles in communications

and computation systems.
Examples:
Frequency synthesis
Clock and data recovery
Clock generation and distribution
 XOR Gate as a Phase Detector

An XOR gate can serve as a phase detector by

examining the difference of rising/falling times.
Work only for periodic signals.
 Response of XOR as a Phase Detector

Periodic input/output characteristic implies

limited capture range. (Why?)
 Simple PLL

ω out = ωin

Phase relationship is undetermined.

 Response of Simple PLL to a Phase Step

Integration of the shadow part of ωout equals φ1.

Response of Simple PLL to a Frequency Step

ωout changes from ω1 to ω2 eventually.

VPD changes as well.
 Dynamic Behavior of Simple PLLs

Φ out
H (s ) open = (s ) open
Φ in
1 K VCO
= K PD
s s
1+
ωLPF

K PD K VCO
H (s ) closed = ωn = ωLPFK PD K VCO
s2
ωLPF + s + K PD K VCO
ω n2 1 ωLPF
= ζ=
s 2 + 2ζω n s + ωn2 2 K PDK VCO

Typical second order transfer function.

 Dynamic Behavior of Simple PLLs

s1,2 = (−ζ ± ζ 2 − 1)ω n

1
ζω n = ω LPF
2

Decaying envelope determines the settling time.

Settling time and noise suppression present a
critical trade-off.
RF applications usually require an under- or
critical-damped response.
 Stability of Simple PLLs

Small ζ leads to ringing For 45o phase margin,

(unstability). KPDKVCO = √2 ω LPF
 Charge-Pump PLLs

Simple PLL suffers from numbers of drawbacks

that prohibit it from high-performance applications:

• critical trade-off between settling and noise

• finite and undetermined phase error
• limited acquisition range

Charge-pump PLLs can relax the tradeoffs, and

produce zero phase error.
Large acquisition range can be achieved by
introducing frequency acquisition loop.
 Phase/Frequency Detector (PFD)

For periodic signals, phase and frequency acquisition

can be merged.
Necessitating reset technique.
 Linear PFD
Linear PFD detects the phase (frequency) error and
generates an output proportional to the difference.

Non-periodic characteristic suggests infinite capture

range because it “swallows” extra pulse if needed.
Linear PFD with Charge Pump
Dynamic Behavior of Charge-Pump PLLs

Φ out I ⎛ 1 ⎞ K VCO
(s ) open = P ⎜⎜ Rp + ⎟⎟
Φ in 2π ⎝ CP s ⎠ s

2ζωn s + ωn2
H (s ) =
s 2 + 2ζωn s + ωn2

I P K VCO
ωn =
2πCP

RP I PCP K VCO
ζ=
2 2π

Resistor RP must be introduced to create a zero.

 Comparison of 1st and 2nd Order PLLs

First-order PLLs are unconditionally unstable.

Second-order can be stable if proper design applies.
 Root Locus of 2nd Order PLLs

s1,2 = −ζωn ± ωn ζ 2 − 1

ζ = cosψ

The two poles split at origin, go around a circle,

2
merge again at − RPCP , and finally move along the
real axis in opposite directions.
 Third-Order Charge Pump PLLs

VCO control line experiences a large jump due to

current charging or discharging through RP.
A small capacitor C2 is therefore introduced to
suppress the ripple.
It should impose only negligible influence on loop
parameters.
 Dead-Zone in PFD & Charge Pump

A PFD/CP circuit provides no corrective feedback,

leading to substantial jitter.
Fortunately, type IV PFD produces coincident pulses
and dead-zone issue is eliminated.
Current Mismatch Issue in Charge Pumps

Periodic ripple on VCO control line are observed

due to current mismatches and/or channel-length
modulation.
Control line ripple induces spurs (sidebands) directly.
Charge Sharing Issue in Charge Pumps

Charge equalization can be used

during idle time to minimize the effect.
Charge injection of the switches still
cause mismatches.
Case Study - SSB-Based Phase Detector

[Lee, ISSCC07]

Near-dc output VPD applies to (V/I)PD .

Finite image would appear at 2ωin .
Frequency Synthesizers

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

Introduction
Integer-N Synthesizer
Fractional-N Synthesizer
• Accumulator-Based
• Σ−Δ Modulated
Direct Digital Synthesizer
Case Study
Integer-N Synthesizers
 Introducing Divide Ratio M

I p K VCO
(RpCp s + 1)
2πC p
H (s) =
I p K VCO I p K VCO
s +
2
Rp s +
2π M 2 πC p M
Ip
K VCO Rp I pC p K VCO
4 πM ωn = ,ξ =
2πC p M 2 2π M
Decay τ = (ξωn ) =
-1

Rp IpK VCO

1
Settling time ∝ ⇐ critical in channel selection.
ξωn
Closed-loop synthesizer fails to serve in special
applications such as frequency hopping and instant
locking.
 Reference Feedthrough and Sidebands

V out (t ) ≅ A0 cosω0t + [ cos(ω0 + ωm )t − cos(ω0 − ωm )t ]

A0V mK VCO
2ωm

Control line ripple introduces jitter too (how to

estimate it?)
Sidebands interfere with adjacent channels.
 Noise Transfer Function

∼ωn ∼ωn

Input and VCO noise shaped by low-pass and

high-pass filtering with loop bandwidth (~ωn).
 Limitation of Integer-N Synthesizers

Φ out s2
(s) = 2
Φ VCO s + 2ξωn + ωn2

Loop bandwidth < fref /10. (why?)

Channel resolution determined by fref .
⇒ Very low loop bandwidth.
⇒ Having difficulty in suppressing
VCO noise.
 Limitation of Integer-N Synthesizers

Other issues of integer-N synthesizers:

• Reference feed-through • Large divide ratio
• Finite frequency resolution • High noise floor
Nonetheless, integer-N is still the most popular one
due to its simplicity.
Do we have any other choice?
• (Almost) infinite resolution
• Shaped noise profile
• Reasonable complexity and power consumption

⇒ Fractional-N (ΣΔ) Synthesizers

 Fractional-N Synthesizers

Fractional-N
• Modulating the divide
ratio such that the
averaged modulus equals
N+k, where 0 ≤ k ≤ 1

Example:
fref = 1 MHz, N = 10
⇒ fout = 10.1 MHz
 Fractional-N Synthesizers

Accumulator-Based Fractional-N

Carry out bit asserted whenever overflow happens.

Break constraint of integer divide ratio.
 Example of Accumulator-Based Fractional-N

N=4.25
=(3*4+1*5)/4

Drawback: [Courtesy, M. Perrott]

• Reference spurs exist since PFD output varies periodically.
⇒ Techniques such as phase interpolation could
suppress the spurious tones by predicting and
canceling the phase error.
⇒
Ripple Reduction Using Phase Interpolation

[Courtesy, M. Perrott]

Phase error cancels based on accumulator residue.

 Σ-Δ Modulation
Noise shaping: pushing quantization noise to high
frequencies.

2
fout 2
Snf (f ) ≅ 4 Q (f )
N
⇒ The PSD of frequency
quantization noise resembles
that of the quantization noise.
 Σ-Δ Modulator
Σ−Δ Modulator provides a unity gain path and well-
defined noise profile.

Y (z ) = U (z ) + R (z )
= X (z ) + [H (z ) − 1]E (z ) + R (z )
= X (z ) + [H (z ) − 1]R (z ) + R (z )
= X (z ) + H (z )R (z )

⇒ Signal Transfer Function (STF) = 1

Noise Transfer Function (NTF) = H(z)
Different order gives different shaping.
Choice of H(z)
Easy to
implement.

Well-defined
shaping for
different m.
First-Order Σ-Δ Modulator

[Courtesy, M. Perrott]
Second-Order Σ-Δ Modulator

[Courtesy, M. Perrott]
Third-Order Σ-Δ Modulator

[Courtesy, M. Perrott]
Noise Analysis on Σ−Δ Frequency Synthesizers

Total noise is the combination of the three sources.

 Well-Designed Σ−Δ Synthesizers

Loop bandwidth low enough so that PFD and VCO

noise dominate.
Higher order Σ-Δ modulator shapes the quantization
further but PFD and VCO noise unaffected.
 Impact of Loop Bandwidth

Increase loop bandwidth => more PFD noise, more

Σ-Δ noise, less VCO noise.
The rule of thumb is to take the advantage of Σ-Δ
modulator without degrading other performance.
 Direct Digital Frequency Synthesizers
Can we synthesize a clock directly from database?

Advantages: Drawbacks:
• Instant switching (f and φ) • Speed
• Ultra low phase noise ( ≈ Xtal ) • Waveform distortion
• Direct modulation
 General Realization of DDFS

Truncation and amplitude quantization cause spurs.

ROM size (1/4 waveform).
DAC resolution/speed.
Unwanted modulation when fout becomes comparable
with fck.
 General Issues of DDFS

fck = 800MHz, fout = 18MHz

SFDR Rolloff

Highly distorted
[Yang et al, JSSC04]
fck = 800MHz, fout = 328MHz
 Case Study

3-bit Prescaler

[Tiebout, ISSCC04]

13GHz Fractional-N PLL.

Second order modulator.
Clock and Data Recovery

Professor Jri Lee

台大電子所 李致毅教授

Electrical Engineering Department

National Taiwan University
 Outline

General Considerations
Linear Phase Detector
Binary Phase Detector
CDR Architecture
 Edge Detection

Extracting clock from NRZ data is not trivial at all,

since its spectrum contains no power at the
frequency of data rate.
A circuit detecting the data transition is essential
for clock recovery.
 CMOS Realization of Edge Detectors

Gilbert cell with capacitive degeneration may

achieve differentiation and rectification at high
speed.
 Alternative Solution for Edge Detection

Proper delay must be set to obtain clear pulses.

PVT variation matters.
 Phase Detection
A more efficient way is to detect the data transition
and determine whether it is early or late with respect
to its corresponding clock phase.

Finite acquisition range Binary characteristic

(Why?)
Simple CDR with Single-FF Phase Detector

Drawbacks:
Continue to increase or decrease the VCO
control voltage even when no data edge is
present ⇒ large jitter.
Large skews may cause improper sampling.
Finite capture range (lack of frequency
acquisition loop).
 Hogge Phase Detector

[Hogge, ’85]

Linear operation.
Complete pulses must be generated within
approximately 1/4 of a bit period.
Suitable for low to moderate frequency.
Non-idealities of Hogge Phase Detector

FF delay requires compensation.

ΔT may not track the FF delay well across a wide
range of temperature and supply variations.
Generating a delay of several tens of picoseconds
is not easy in terms of power and/or area.
 Tri-Wave Issue

UP and DOWN pulses are not

aligned in time, creating tri-
waves on the VCO control lines.
 Alexander (Bang-Bang) Phase Detector

[Alexander, ’76]
Binary operation simplifies the phase comparison and
increases the speed.
Abruptly toggling between two states rather than gently
waggling around zero.
 Complete CDR using Alexander PD

Both Hogge and Alexander PDs provide automatic

data retiming and tri-state output (i.e., no net current
during long runs).
Both Hogge and Alexander PDs have only limited
capture range and require frequency acquisition loop.
 Half-Rate Hogge Phase Detector

C ⊕ D serves as a reference.
Clock duty cycle plays crytical roles (must be 50%).
 Half Rate Alexander Phase Detector

Clock with quadrature phases is a must.

Many other ways to implement sub-rate CDRs
(how about quarter rate?)
 CDR Architecture

For most CDRs, the acquisition range is roughly

equal to the loop bandwidth, which is about 1/1000
of the data rate.
Such a small range mandates the use of additional
frequency acquisition loop.

One set of system parameters must satisfy two loops.

 Alternative CDR Architectures

FD loop pushes the oscillation frequency to roughly-right

position.
PD loop then takes over to lock the phase.
Lock detector is required to shut down the FD upon lock.
 Alternative CDR Architectures

Adjustable Parameters

Proper logic and timing control is required for a

smooth switching.
But after all, it is the PD loop that determines the
performance in lock.
Case Study – 40Gb/s Over-Sampling CDR

[Nedovic, ISSCC07]

3x over sampling.
Quarter-rate VCO.