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CD4015

The CD4015BM/CD4015BC contains two identical, 4-stage, serial-input/parallel-output registers with independent ``Data'', ``Clock,'' and ``Reset'' inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the ``Reset'' input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS.
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0% found this document useful (0 votes)
173 views

CD4015

The CD4015BM/CD4015BC contains two identical, 4-stage, serial-input/parallel-output registers with independent ``Data'', ``Clock,'' and ``Reset'' inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the ``Reset'' input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS.
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CD4015BM/CD4015BC Dual 4-Bit Static Shift Register

June 1996

CD4015BM/CD4015BC Dual 4-Bit Static Shift Register


General Description Features
The CD4015BM/CD4015BC contains two identical, 4-stage, Y Wide supply voltage range 3.0V to 18V
serial-input/parallel-output registers with independent Y High noise immunity 0.45 VDD (typ.)
‘‘Data’’, ‘‘Clock,’’ and ‘‘Reset’’ inputs. The logic level pres- Y Low power TTL Fan out of 2 driving 74L
ent at the input of each stage is transferred to the output of compatibility or 1 driving 74LS
that stage at each positive-going clock transition. A logic Y Medium speed operation 8 MHz (typ.) clock rate
high on the ‘‘Reset’’ input resets all four stages covered by Fully static design @V
Y
DD b VSS e 10V
that input. All inputs are protected from static discharge by a
series resistor and diode clamps to VDD and VSS.
Applications
Y Serial-input/parallel-output data queueing
Y Serial to parallel data conversion
Y General purpose register

Connection Diagram and Truth Table


Dual-In-Line Package

TL/F/5948 – 1

CL U D R Q1 Qn
L 0 0 0 Qnb1
L 1 0 1 Qnb1
K X 0 Q1 Qn (No change)
X X 1 0 0
U Level change

X e Don’t care case

Order Number CD4015B

C1996 National Semiconductor Corporation TL/F/5948 RRD-B30M76/Printed in U. S. A. http://www.national.com


Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating
If Military/Aerospace specified devices are required, Conditions
please contact the National Semiconductor Sales
DC Supply Voltage (VDD) a 3 to a 15 VDC
Office/Distributors for availability and specifications.
Input Voltage (VIN) 0 to VDD VDC
DC Supply Voltage (VDD) b 0.5 to a 18 VDC
Operating Temperature Range (TA)
Input Voltage (VIN) b 0.5 to VDD a 0.5 VDC
CD4015BM b 55§ C to a 125§ C
Storage Temperature Range (TS) b 65§ C to a 150§ C CD4015BC b 40§ C to a 85§ C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§ C

DC Electrical Characteristics CD4015BM (Note 2)


b 55§ C a 25§ C a 125§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V, VIN e VDD or VSS 5 0.005 5 150 mA
Current VDD e 10V, VIN e VDD or VSS 10 0.010 10 300 mA
VDD e 15V, VIN e VDD or VSS 20 0.015 20 600 mA
VOL Low Level VDD e 5V 0.05 0 0.05 0.05 V
Output Voltage VDD e 10V
VDD e 15V ( lIOl k 1 mA 0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
VOH High Level VDD e 5V 4.95 4.95 5 4.95 V
Output Voltage VDD e 10V
VDD e 15V (l l IO k 1 mA 9.95
14.95
9.95
14.95
10
15
9.95
14.95
V
V
VIL Low Level VDD e 5V, VO e 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Input Voltage VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level VDD e 5V, VO e 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Input Voltage VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e 5V, VO e 0.4V 0.64 0.51 0.88 0.36 mA
Current (Note 3) VDD e 10V, VO e 0.5V 1.6 1.3 2.25 0.9 mA
VDD e 15V, VO e 1.5V 4.2 3.4 8.8 2.4 mA
IOH High Level Output VDD e 5V, VO e 4.6V b 0.64 b 0.51 b 0.88 b 0.36 mA
Current (Note 3) VDD e 10V, VO e 9.5V b 1.6 b 1.3 b 2.25 b 0.9 mA
VDD e 15V, VO e 13.5V b 4.2 b 3.4 b 8.8 b 2.4 mA
IIN Input Current VDD e 15V, VIN e 0V b 0.1 b 10 b 5 b 0.1 b 1.0 mA
VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

http://www.national.com 2
DC Electrical Characteristics CD4015BC (Note 2)
b 55§ C a 25§ C a 125§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V, VIN e VDD or VSS 20 0.005 20 150 mA
Current VDD e 10V, VIN e VDD or VSS 40 0.010 40 300 mA
VDD e 15V, VIN e VDD or VSS 80 0.015 80 600 mA
VOL Low Level VDD e 5V 0.05 0 0.05 0.05 V
Output Voltage VDD e 10V 0.05 0 0.05 0.05 V
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VDD e 5V 4.95 4.95 5 4.95 V
Output Voltage VDD e 10V 9.95 9.95 10 9.95 V
VDD e 15V 14.95 14.95 15 14.95 V
VIL Low Level VDD e 5V, VO e 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Input Voltage VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level VDD e 5V, VO e 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Input Voltage VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e 5V, VO e 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) VDD e 10V, VO e 0.5V 1.3 1.1 2.25 0.9 mA
VDD e 15V, VO e 1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level Output VDD e 5V, VO e 4.6V b 0.52 b 0.44 b 0.88 b 0.36 mA
Current (Note 3) VDD e 10V, VO e 9.5V b 1.3 b 1.1 b 2.25 b 0.9 mA
VDD e 15V, VO e 13.5V b 3.6 b 3.0 b 8.8 b 2.4 mA
IIN Input Current VDD e 15V, VIN e 0V b 0.3 b 10 b 5 b 0.3 b 1.0 mA
VDD e 15V, VIN e 15V 0.3 10b5 0.3 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

3 http://www.national.com
AC Electrical Characteristics*
TA e 25§ C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units


CLOCK OPERATION
tPHL, tPLH Propagation Delay Time VDD e 5V 230 350 ns
VDD e 10V 80 160 ns
VDD e 15V 60 120 ns
tTHL, tTLH Transition Time VDD e 5V 100 200 ns
VDD e 10V 50 100 ns
VDD e 15V 40 80 ns
tWL, tWM Minimum Clock VDD e 5V 160 250 ns
Pulse-Width VDD e 10V 60 110 ns
VDD e 15V 50 85 ns
trCL, tfCL Clock Rise and VDD e 5V 15 ms
Fall Time VDD e 10V 15 ms
VDD e 15V 15 ms
tSU Minimum Data VDD e 5V 50 100 ms
Set-Up Time VDD e 10V 20 40 ms
VDD e 15V 15 30 ms
fCL Maximum Clock VDD e 5V 2 3.5 MHz
Frequency VDD e 10V 4.5 8 MHz
VDD e 15V 6 11 MHz
CIN Input Capacitance Clock Input 7.5 10 pF
Other Inputs 5 7.5 pF
RESET OPERATION
tPHL(R) Propagation Delay Time VDD e 5V 200 400 ns
VDD e 10V 100 200 ns
VDD e 15V 80 160 ns
tWH(R) Minimum Reset VDD e 5V 135 250 ns
Pulse Width VDD e 10V 40 80 ns
VDD e 15V 30 60 ns
*AC Parameters are guaranteed by DC correlated testing.

Logic Diagrams

TL/F/5948 – 2

http://www.national.com 4
Logic Diagrams (Continued)

Terminal No. 16 e VDD


Terminal No. 8 e GND TL/F/5948 – 3

Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-In-Line Package (J)


Order Number CD4015BMJ or CD4015BCJ
NS Package Number J16A

5 http://www.national.com
CD4015BM/CD4015BC Dual 4-Bit Static Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)


Order Number CD4015BMN or CD4015BCN
NS Package Number N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor


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1111 West Bardin Road Fax: a49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
This datasheet has been downloaded from:

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