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Priya Bajpai CV

Priya Bajpai is a digital design engineer with over 1 year of experience in FPGA design. She currently works for Granite River Labs in Bangalore developing IPs, interfacing with protocols like I2C and SPI, and exploring FPGA architectures. She has a M.Tech in VLSI from C-DAC Noida and B.Tech in ECE from B.N. College of Engineering. Her technical skills include Verilog, VHDL, Vivado, and embedded systems.

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satya mishra
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104 views3 pages

Priya Bajpai CV

Priya Bajpai is a digital design engineer with over 1 year of experience in FPGA design. She currently works for Granite River Labs in Bangalore developing IPs, interfacing with protocols like I2C and SPI, and exploring FPGA architectures. She has a M.Tech in VLSI from C-DAC Noida and B.Tech in ECE from B.N. College of Engineering. Her technical skills include Verilog, VHDL, Vivado, and embedded systems.

Uploaded by

satya mishra
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CURRICULUM VITAE

PRIYA BAJPAI
Email Id : [email protected]
Mobile No. : +91-7503762323/9451019091

CAREER OBJECTIVE:
Proactive, self-driven and result oriented individual having FPGA designing experience looking
forward to play a more challenging role day by day in VLSI field.

CURRENT PROFILE:
Company : Granite River labs Technologies Pvt. Ltd.
Company Location : Bangalore
Domain : Digital (VLSI) Designing
Designation : RTL Design Engineer
Period : June 2016 to Present (1 Year +)
Work Experience Description:
 I2C Protocol , SPI Protocol.
 AXI Interconnect Protocol.
 ADC, DAC, IO Expander, LCD Driver interfacing using I2C or SPI protocol .
 Worked on Vivado IPs and designed custom IPs.
 Explored BRAM , FIFO , DMA interfacing for DDR on Vivado Xilinx Tool.

PROFILE SUMMARY:

 Currently I am working as FPGA Design Engineer at Granite River Labs, Bangalore (From 14th
June 2016 till present)

 Five month Internship as a VLSI (FPGA) Engineer (Trainee) at Technolexis, Hyderabad in 4th
semester of M. Tech. (January 2016 to May 2016).

 I have teaching experience of 1 Year and 6 Months in S.K.I.T.M. Sitapur. (October 2012 to April
2014).

ACADEMIC DETAILS:

BOARD / PERCENTAGE OF YEAR OF


QUALIFICATION INSTITUTION
UNIVERSITY MARKS PASSING

IPU, Delhi 80% 2016


M.Tech. (VLSI) C-DAC,Noida

B.N. College of Engineering and


B.Tech. (ECE) UPTU, Lucknow 73% 2012
Technology, Lucknow
M.Tech. Projects:

Title- “Implementation of Face Detection Algorithm using Verilog code on programmable


logic of ZYNQ FPGA” .

External Guide- Mukesh Chauhan , Director R&D at TECHNOLEXIS, Hyderabad.


Internal Guide- Ravi Payal , Senior Technical Officer at C-DAC Noida.

Description-Skin color based Face Detection Algorithm using Verilog language,


transferring the image ( RGB 5:6:5 ) with help of I2C camera(OV7670) to the processor
of ZYBO then showing the modified image on display with the help of VGA interface.

TECHNICAL SKILLS:

Software Language : C , Embedded C


Hardware Language(s) : VHDL , Verilog
Hardware Tool Expertise : Xilinx Vivado , Xilinx ISE , Lattice Diamond , Modelsim , Questa
Software Tool Expertise : Xilinx SDK (Software Development Kit)
FPGA Development Kit Expertise: ZED Board , ZYBO(ZYNQ Board)
Embedded Kit Expertise : Ardunio
Lab Equipment Expertise : Oscilloscopes, Power Supplies, Signal Generator etc
Qualified Exam : GATE

EXTRA ACTIVITIES:
 One month embedded system training from Regal Technology in B.Tech.
TECHNICAL SKILLS:
Lucknow.
 I have done NITTTR (National Institute of Technical Teacher’s Training &
Research) workshop in M.Tech.

 Extra Verilog Projects –


 Simulation of synchronous FIFO using Verilog code
 CRC (Cyclic Redundancy Check)
 Traffic light controller
 Smart toll gate
 HDLC Protocol

 Course Done in M.Tech. –


 Low Power VLSI Design
 Analog Mixed Signal Design
 System On Chip
 VLSI Test and Testability
 MEMS IC integration
 Algorithm Analysis and Design
 VLSI Technology
 Advanced VLSI Design
 Secured Hardware Design
 Advanced Computer Arhitecture
PERSONAL DETAILS:
Father’s Name : Saran Swaroop Bajpai
Date of Birth : 7th January 1992
Languages Known : English and Hindi
Address : Priya Bajpai , C/O Manoj Kumar Bajpai,
19-Najeerganj , Daliganj , Lucknow , U.P.
Pin Code-226020

DECLARATION:
It is hereby declared that the above mentioned information is true and correct to the best of my
knowledge and belief.

Place: Bangalore Priya Bajpai

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