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Experiment 3 Make File: Compiler Process

The makefile document describes the compiler process which involves three stages: compiler, assembler, and linker. It also discusses how makefiles provide a way for separate compilation by describing file dependencies and allowing the use of the make utility. A sample makefile structure is shown using rules and automatic variables. Conditionals and options for makefiles are also outlined.

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87 views3 pages

Experiment 3 Make File: Compiler Process

The makefile document describes the compiler process which involves three stages: compiler, assembler, and linker. It also discusses how makefiles provide a way for separate compilation by describing file dependencies and allowing the use of the make utility. A sample makefile structure is shown using rules and automatic variables. Conditionals and options for makefiles are also outlined.

Uploaded by

Muddassir Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT 3

Make File
Compiler Process:
 Compiler Stage: All C++ language code in the .cpp file is converted into a lower-level
language called Assembly language; making .s files.
 Assembler Stage: The assembly language code made by the previous stage is then
converted into object code which are fragments of code which the computer understands
directly. An object code file ends with .o.
 Linker Stage: The final stage in compiling a program involves linking the object code to
code libraries which contain certain "built-in" functions, such as cout. This stage
produces an executable program, which is named a.out by default.

Makefiles:
 Provide a way for separate compilation.
 Describe the dependencies among the project files.
 The make utility.

Using makefiles:
Naming:
 makefile or Makefile are standard
 other name can be also used

Running make:
make
make –f filename – if the name of your file is not “makefile” or “Makefile”
Sample makefile:
Makefiles main element is called a rule:

Example:
my_prog : eval.o main.o
g++ -o my_prog eval.o main.o (-o to specify executable file name)
eval.o : eval.c eval.h
g++ -c eval.c (-c to compile only (no linking))
main.o : main.c eval.h
g++ -c main.c
Variables:

Automatic variables:
Automatic variables are used to refer to specific part of rule components.
eval.o : eval.c eval.h
g++ -c eval.c
$@ - The name of the target of the rule (eval.o).
$< - The name of the first dependency (eval.c).
$^ - The names of all the dependencies (eval.c eval.h).
$? - The names of all dependencies that are newer than the target
make options:
-f filename - when the makefile name is not standard
-t - (touch) mark the targets as up to date
-q - (question) are the targets up to date, exits with 0 if true
-n - print the commands to execute but do not execute them
/ -t, -q, and -n, cannot be used together /
-s - silent mode
-k - keep going – compile all the prerequisites even if not able to link them !!
Conditionals (directives):
Possible conditionals are:
if ifeq ifneq ifdef ifndef
All of them should be closed with endif.
Complex conditionals may use elif and else.
Example:
libs_for_gcc = -lgnu
normal_libs =
ifeq ($(CC),gcc)
libs=$(libs_for_gcc) #no tabs at the beginning
else
libs=$(normal_libs) #no tabs at the beginning
endif
In-Lab Question: Create the following classes in separate files (using .h and .cpp files)
Student, Teacher, Course.
A student has a list of courses that he is enrolled in.
A teacher has a list of courses that he is teaching.
A course has a list of students that are studying it, and a list of teachers that are teaching the
course.
Create some objects of all classes in main function and populate them with data.
Now compile all classes using makefile.

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