Lecture 17 Another 3-bit up counter: now with T flip flops

◆ Logistics
■ Lab 7 this week
■ HW6 is due Friday 1. Draw a state diagram
■ Office Hours
µ Mine: Friday 10:00-11:00 as usual 2. Draw a state-transition table
µ Sara: Thursday 2:30-3:20 CSE 220
µ Josh: Thursday 3:30-4:20 CSE 002
■ Midterm delayed until next Wednesday
3. Encode the next-state functions
µ Will cover material up to Friday’s lecture ■ Minimize the logic using K-maps
◆ Last two lectures 4. Implement the design
■ Registers, Counters, Counter Finite State Machines (FSM)
■ Sequential Verilog
◆ Today
■ Another counter FSM
■ Timing issues
µ Timing terminology and issues and solutions (e.g. clock skew)
µ Asynchronous inputs and issues and solutions (e.g. debouncing)

CSE370, Lecture 17 1 CSE370, Lecture 17 2

1. Draw a state diagram 2. Draw a state-transition table

◆ Like a truth-table
■ State encoding is easy for counters → Use count value

001 010 011

current state next state
010 011
0 000 001 1
001
000 3-bit up-counter 100 1 001 010 2
2 010 011 3
000 3-bit up-counter 100 3 011 100 4
111 110 101 4 100 101 5
111 110 101 5 101 110 6
6 110 111 7
7 111 000 0

CSE370, Lecture 17 3 CSE370, Lecture 17 4

3. Encode the next state functions 4. Implement the design

T flip-flops Ti = 1 iff Ni ≠ Ci T0 C2

T Q T0 := 1 1 1 1 1
T1 := C0
C0 1 1 1 1
C1
T2 := C0 C1

C2 C1 C0 N2 N1 N0 T2 T1 T0 T1 C2
0 0 0 0 0 1 0 0 1 C0 C1 C2
0 0 1 0 1 0 0 1 1
0 0 0 0
C0 1 1 1 1 1 T Q T Q T Q
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1 C1 CLK
1 0 0 1 0 1 0 0 1
T2 C2
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1 0 0 0 0
1 1 1 0 0 0 1 1 1 C0 0 1 1 0
CSE370, Lecture 17 C1 5 CSE370, Lecture 17 6
The “WHY” slide Latches versus flip-flops

◆ Timing issues
■ For sequential logic, “timing” is critical because for the same inputs,
the output could be different at different times (like T-flip flops). In D Q CLK
order to achieve desired outputs, timing has to be taken into
consideration. Q
D
■ Transistors, chips, and even wires have their own delays. Because
of this, nothing could ever be perfectly synchronized. It is important CLK
to understand how fast a clock can tick based on these delays and Qff
what the common issues are in making computers to run fast and
accurately. D Q Qlatch
■ There are synchronous and asynchronous inputs. For example, Q
typing on the keyboard, you are putting in asynchronous inputs to
the computer. Asynchronous inputs can change the outputs behavior of latch is the same unless input
immediately regardless of the clock state, and it is important to know CLK
changes while the clock is high
how to handle that.
For most applications, it is not good to see
CSE370, Lecture 17 7 CSE370, Lecture 17 Input changes instantaneously at the output 8

The master-slave D
(polarity reversed from previous class)
Master-Slave D implements D flip-flop

Master D latch Slave D latch D Q CLK

Input D Q D Q Output Q
D
CLK
CLK Qff
master-slave D flip-flop
D Q Qlatch’
Q
Because of the timing issue, it was good Qmasterslave
to use two latches as master-slave CLK
configuration or use one flip-flop.
For most applications, it is not good to see
CSE370, Lecture 17 9 CSE370, Lecture 17 10
Input changes instantaneously at the output

Timing terminology and constraints for a FF Cascading flip-flops

■ Setup time tsu: Amount of time the input must be stable before the ◆ Flip-flop propagation delays exceed hold times
clock transitions high (or low for negative-edge triggered FF)
■ Hold time th: Amount of time the input must be stable after the clock
■ Second stage commits its input before Q0 changes
transitions high (or low for negative-edge triggered FF)
■ Clock width tw : Minimum clock width that must be met in order for FF
to work properly
■ Propagation delays tp-lh and tp-hl: Propagation delay (high to low, low to In
IN Q0 Q1
high) (longer than hold time) D Q D Q tsu tsu
> > Q0
tsu th
tsu th tp-lh tp-hl
D Q D
CLK Q1
Q
tw Order can’t be reversed else
CLK Q1 will not have its required hold time Clk th th
CLK
Q tp-hl , tp-lh > th
tp-hl
tp-lh tp + tsu < tcycle
CSE370, Lecture 17 11 CSE370, Lecture 17 12
 Side note: Clock skew System considerations

◆ Goal: Clock all flip-flops at the same time ◆ Use edge-triggered flip-flops wherever possible
■ Difficult to achieve in high-speed systems ■ Avoid latches
µ Clock delays (wire, buffers) are comparable to logic delays ■ Most common: Master-slave D
■ Problem is called clock skew
◆ Basic rules for correct timing
■ Clock flip-flops synchronously (all at the same time)
IN CLK0 clocks first flipflop µ No flip-flop changes state more than once per clock cycle
Q0 CLK1 clocks second flipflop µ FF propagation delay > hold time
Q1
CLK1 should align with ■ Avoid mixing positive-edge triggered and negative-edge
CLK0
CLK0, but is delayed triggered flip-flops in the same circuit
CLK1
due to clock skew

Original state: IN = 0, Q0 = 1, Q1 = 1
Next state: Q0 = 0, Q1 = 0 (should be Q1 = 1)

■ Avoiding clock skew: design identical delays

CSE370, Lecture 17 13 CSE370, Lecture 17 14

Asynchronous versus synchronous Asynchronous inputs

◆ Asynchronous ◆ Clocked circuits are synchronous

■ State changes occur when state inputs change ■ Circuit changes state only at clock edges
■ Feedback elements may be wires or delays ■ Signals (voltages) settle in-between clock edges

◆ Synchronous ◆ Unclocked circuits or signals are asynchronous

■ State changes occur synchronously ■ No master clock
■ Feedback elements are clocked ■ Real-world inputs (e.g. a keypress) are asynchronous

Asynchronous Synchronous ◆ Synchronous circuits have asynchronous inputs

■ Reset signal, memory wait, user input, etc.
Combinational Combinational
Logic Logic
■ Inputs “bounce”
■ Inputs can change at any time
µ We must synchronize the input to our clock
µ Inputs will violate flip-flop setup/hold times

CSE370, Lecture 17
Clock CSE370, Lecture 17
15 16

Debouncing Synchronizer failure

◆ Switch inputs bounce ◆ Occurs when FF input changes near clock edge
■ i. e. don’t make clean transitions ■ Input is neither 1 or 0 when clock goes high
■ Output may be neither 0 or 1
◆ Can use RS latch for debouncing µ May stay undefined for a long time
■ Eliminates dynamic hazards ■ Undefined state is called metastability
■ “Cleans-up” inputs

3.3V D
0V
R 1
Q 0
3.3V CLK

S 1
Q' 0
3.3V Q

0V logic 0 logic 1

CSE370, Lecture 17 17 CSE370, Lecture 17 18

Minimizing synchronizer failures Handling asynchronous inputs

◆ Failure probability can never be zero ◆ Never fan-out asynchronous inputs

■ Cascade two (or more) flip-flops ■ Synchronize at circuit boundary
µ Effectively synchronizes twice ■ Fan-out synchronized signal
µ Both would have to fail for system to fail

Synchronizer

Async Q0 Async Q0
D Q D Q D Q
Input Input
asynchronous synchronized
D Q D Q
input input Clock Clock

Clk Q1 Q1
D Q D Q

Clock Clock

CSE370, Lecture 17 19 CSE370, Lecture 17 20

Summary:
Timing issues with asynchronous inputs
◆ For sequential logic circuits, timing issues have to be
considered.
◆ Inputs are often asynchronous and can cause
problems.
◆ Different amount of delay at different part of the
circuit can cause problems also.
◆ Solutions:
■ Cascade flip flops in series
■ Incorporate RS latch for debouncing
■ Design to keep timing alignment in mind (length of wires, etc)

CSE370, Lecture 17 21